PRU Opcode Port
opcodes/ * Makefile.am: Add PRU source files. * configure.ac: Add PRU target. * disassemble.c (disassembler): Register PRU arch. * pru-dis.c: New file. * pru-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
This commit is contained in:
Dimitar Dimitrov
Alan Modra
parent
889294f6ff
commit
1114684964
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@ -1,3 +1,13 @@
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2016-12-31 Dimitar Dimitrov <dimitar@dinux.eu>
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* Makefile.am: Add PRU source files.
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* configure.ac: Add PRU target.
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* disassemble.c (disassembler): Register PRU arch.
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* pru-dis.c: New file.
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* pru-opc.c: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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2016-12-29 Yao Qi <yao.qi@linaro.org>
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* avr-dis.c: Include "bfd_stdint.h"
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@ -223,6 +223,8 @@ TARGET_LIBOPCODES_CFILES = \
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pj-opc.c \
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ppc-dis.c \
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ppc-opc.c \
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pru-dis.c \
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pru-opc.c \
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riscv-dis.c \
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riscv-opc.c \
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rl78-decode.c \
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@ -525,6 +525,8 @@ TARGET_LIBOPCODES_CFILES = \
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pj-opc.c \
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ppc-dis.c \
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ppc-opc.c \
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pru-dis.c \
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pru-opc.c \
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riscv-dis.c \
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riscv-opc.c \
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rl78-decode.c \
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@ -931,6 +933,8 @@ distclean-compile:
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pj-opc.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ppc-dis.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ppc-opc.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pru-dis.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pru-opc.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/riscv-dis.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/riscv-opc.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rl78-decode.Plo@am__quote@
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@ -12683,6 +12683,7 @@ if test x${all_targets} = xfalse ; then
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bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;;
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bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
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bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
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bfd_pru_arch) ta="$ta pru-dis.lo pru-opc.lo" ;;
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bfd_pyramid_arch) ;;
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bfd_romp_arch) ;;
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bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;;
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@ -307,6 +307,7 @@ if test x${all_targets} = xfalse ; then
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bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;;
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bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
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bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
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bfd_pru_arch) ta="$ta pru-dis.lo pru-opc.lo" ;;
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bfd_pyramid_arch) ;;
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bfd_romp_arch) ;;
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bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;;
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@ -73,6 +73,7 @@
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#define ARCH_pdp11
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#define ARCH_pj
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#define ARCH_powerpc
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#define ARCH_pru
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#define ARCH_rs6000
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#define ARCH_rl78
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#define ARCH_rx
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@ -375,10 +376,14 @@ disassembler (bfd *abfd)
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disassemble = print_insn_little_powerpc;
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break;
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#endif
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#ifdef ARCH_pru
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case bfd_arch_pru:
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disassemble = print_insn_pru;
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break;
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#endif
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#ifdef ARCH_riscv
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case bfd_arch_riscv:
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disassemble = print_insn_riscv;
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break;
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#endif
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#ifdef ARCH_rs6000
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case bfd_arch_rs6000:
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@ -175,6 +175,8 @@ pj-dis.c
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pj-opc.c
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ppc-dis.c
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ppc-opc.c
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pru-dis.c
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pru-opc.c
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riscv-dis.c
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riscv-opc.c
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rl78-decode.c
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@ -0,0 +1,286 @@
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/* TI PRU disassemble routines
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Copyright (C) 2014-2016 Free Software Foundation, Inc.
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/pru.h"
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#include "libiberty.h"
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#include <string.h>
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#include <assert.h>
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/* No symbol table is available when this code runs out in an embedded
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system as when it is used for disassembler support in a monitor. */
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#if !defined (EMBEDDED_ENV)
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#define SYMTAB_AVAILABLE 1
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#include "elf-bfd.h"
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#include "elf/pru.h"
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#endif
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/* Length of PRU instruction in bytes. */
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#define INSNLEN 4
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/* Return a pointer to an pru_opcode struct for a given instruction
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opcode, or NULL if there is an error. */
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const struct pru_opcode *
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pru_find_opcode (unsigned long opcode)
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{
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const struct pru_opcode *p;
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const struct pru_opcode *op = NULL;
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const struct pru_opcode *pseudo_op = NULL;
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for (p = pru_opcodes; p < &pru_opcodes[NUMOPCODES]; p++)
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{
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if ((p->mask & opcode) == p->match)
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{
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if ((p->pinfo & PRU_INSN_MACRO) == PRU_INSN_MACRO)
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pseudo_op = p;
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else if ((p->pinfo & PRU_INSN_LDI32) == PRU_INSN_LDI32)
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/* ignore - should be caught with regular patterns */;
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else
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op = p;
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}
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}
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return pseudo_op ? pseudo_op : op;
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}
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/* There are 32 regular registers, each with 8 possible subfield selectors. */
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#define NUMREGNAMES (32 * 8)
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static void
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pru_print_insn_arg_reg (unsigned int r, unsigned int sel,
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disassemble_info *info)
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{
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unsigned int i = r * RSEL_NUM_ITEMS + sel;
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assert (i < (unsigned int)pru_num_regs);
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assert (i < NUMREGNAMES);
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(*info->fprintf_func) (info->stream, "%s", pru_regs[i].name);
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}
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/* The function pru_print_insn_arg uses the character pointed
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to by ARGPTR to determine how it print the next token or separator
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character in the arguments to an instruction. */
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static int
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pru_print_insn_arg (const char *argptr,
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unsigned long opcode, bfd_vma address,
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disassemble_info *info)
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{
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long offs = 0;
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unsigned long i = 0;
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unsigned long io = 0;
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switch (*argptr)
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{
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case ',':
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(*info->fprintf_func) (info->stream, "%c ", *argptr);
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break;
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case 'd':
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pru_print_insn_arg_reg (GET_INSN_FIELD (RD, opcode),
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GET_INSN_FIELD (RDSEL, opcode),
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info);
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break;
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case 'D':
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/* The first 4 values for RDB and RSEL are the same, so we
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can reuse some code. */
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pru_print_insn_arg_reg (GET_INSN_FIELD (RD, opcode),
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GET_INSN_FIELD (RDB, opcode),
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info);
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break;
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case 's':
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS1, opcode),
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GET_INSN_FIELD (RS1SEL, opcode),
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info);
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break;
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case 'S':
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS1, opcode),
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RSEL_31_0,
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info);
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break;
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case 'b':
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io = GET_INSN_FIELD (IO, opcode);
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if (io)
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{
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i = GET_INSN_FIELD (IMM8, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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}
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else
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{
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS2, opcode),
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GET_INSN_FIELD (RS2SEL, opcode),
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info);
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}
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break;
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case 'B':
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io = GET_INSN_FIELD (IO, opcode);
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if (io)
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{
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i = GET_INSN_FIELD (IMM8, opcode) + 1;
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(*info->fprintf_func) (info->stream, "%ld", i);
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}
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else
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{
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS2, opcode),
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GET_INSN_FIELD (RS2SEL, opcode),
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info);
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}
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break;
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case 'j':
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io = GET_INSN_FIELD (IO, opcode);
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if (io)
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{
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/* For the sake of pretty-printing, dump text addresses with
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their "virtual" offset that we use for distinguishing
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PMEM vs DMEM. This is needed for printing the correct text
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labels. */
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bfd_vma text_offset = address & ~0x3fffff;
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i = GET_INSN_FIELD (IMM16, opcode) * 4;
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(*info->print_address_func) (i + text_offset, info);
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}
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else
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{
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS2, opcode),
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GET_INSN_FIELD (RS2SEL, opcode),
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info);
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}
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break;
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case 'W':
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i = GET_INSN_FIELD (IMM16, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'o':
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offs = GET_BROFF_SIGNED (opcode) * 4;
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(*info->print_address_func) (address + offs, info);
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break;
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case 'O':
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offs = GET_INSN_FIELD (LOOP_JMPOFFS, opcode) * 4;
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(*info->print_address_func) (address + offs, info);
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break;
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case 'l':
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i = GET_BURSTLEN (opcode);
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if (i < LSSBBO_BYTECOUNT_R0_BITS7_0)
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(*info->fprintf_func) (info->stream, "%ld", i + 1);
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else
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{
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i -= LSSBBO_BYTECOUNT_R0_BITS7_0;
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(*info->fprintf_func) (info->stream, "r0.b%ld", i);
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}
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break;
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case 'n':
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i = GET_INSN_FIELD (XFR_LENGTH, opcode);
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if (i < LSSBBO_BYTECOUNT_R0_BITS7_0)
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(*info->fprintf_func) (info->stream, "%ld", i + 1);
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else
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{
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i -= LSSBBO_BYTECOUNT_R0_BITS7_0;
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(*info->fprintf_func) (info->stream, "r0.b%ld", i);
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}
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break;
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case 'c':
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i = GET_INSN_FIELD (CB, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'w':
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i = GET_INSN_FIELD (WAKEONSTATUS, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'x':
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i = GET_INSN_FIELD (XFR_WBA, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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default:
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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}
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return 0;
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}
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/* pru_disassemble does all the work of disassembling a PRU
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instruction opcode. */
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static int
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pru_disassemble (bfd_vma address, unsigned long opcode,
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disassemble_info *info)
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{
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const struct pru_opcode *op;
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info->bytes_per_line = INSNLEN;
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info->bytes_per_chunk = INSNLEN;
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info->display_endian = info->endian;
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info->insn_info_valid = 1;
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info->branch_delay_insns = 0;
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info->data_size = 0;
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info->insn_type = dis_nonbranch;
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info->target = 0;
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info->target2 = 0;
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/* Find the major opcode and use this to disassemble
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the instruction and its arguments. */
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op = pru_find_opcode (opcode);
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if (op != NULL)
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{
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(*info->fprintf_func) (info->stream, "%s", op->name);
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const char *argstr = op->args;
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if (argstr != NULL && *argstr != '\0')
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{
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(*info->fprintf_func) (info->stream, "\t");
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while (*argstr != '\0')
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{
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pru_print_insn_arg (argstr, opcode, address, info);
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++argstr;
|
||||
}
|
||||
}
|
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}
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else
|
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{
|
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/* Handle undefined instructions. */
|
||||
info->insn_type = dis_noninsn;
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(*info->fprintf_func) (info->stream, "0x%lx", opcode);
|
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}
|
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/* Tell the caller how far to advance the program counter. */
|
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return INSNLEN;
|
||||
}
|
||||
|
||||
|
||||
/* print_insn_pru is the main disassemble function for PRU. */
|
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int
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print_insn_pru (bfd_vma address, disassemble_info *info)
|
||||
{
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||||
bfd_byte buffer[INSNLEN];
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int status;
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||||
|
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status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
|
||||
if (status == 0)
|
||||
{
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||||
unsigned long insn;
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insn = (unsigned long) bfd_getl32 (buffer);
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||||
status = pru_disassemble (address, insn, info);
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||||
}
|
||||
else
|
||||
{
|
||||
(*info->memory_error_func) (status, address, info);
|
||||
status = -1;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/* TI PRU opcode list.
|
||||
Copyright (C) 2014-2016 Free Software Foundation, Inc.
|
||||
Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
|
||||
This library is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
/* Source:
|
||||
http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit */
|
||||
|
||||
#include "sysdep.h"
|
||||
#include <stdio.h>
|
||||
#include "opcode/pru.h"
|
||||
|
||||
/* Register string table. */
|
||||
|
||||
#define DECLARE_REG(name, index) \
|
||||
{ #name ".b0", (index), RSEL_7_0 }, \
|
||||
{ #name ".b1", (index), RSEL_15_8 }, \
|
||||
{ #name ".b2", (index), RSEL_23_16 }, \
|
||||
{ #name ".b3", (index), RSEL_31_24 }, \
|
||||
{ #name ".w0", (index), RSEL_15_0 }, \
|
||||
{ #name ".w1", (index), RSEL_23_8 }, \
|
||||
{ #name ".w2", (index), RSEL_31_16 }, \
|
||||
{ #name , (index), RSEL_31_0 }
|
||||
|
||||
const struct pru_reg pru_regs[] = {
|
||||
/* Standard register names. */
|
||||
DECLARE_REG (r0, 0),
|
||||
DECLARE_REG (r1, 1),
|
||||
DECLARE_REG (sp, 2), /* Stack pointer. */
|
||||
DECLARE_REG (ra, 3), /* Return address. */
|
||||
DECLARE_REG (fp, 4), /* Frame pointer. */
|
||||
DECLARE_REG (r5, 5),
|
||||
DECLARE_REG (r6, 6),
|
||||
DECLARE_REG (r7, 7),
|
||||
DECLARE_REG (r8, 8),
|
||||
DECLARE_REG (r9, 9),
|
||||
DECLARE_REG (r10, 10),
|
||||
DECLARE_REG (r11, 11),
|
||||
DECLARE_REG (r12, 12),
|
||||
DECLARE_REG (r13, 13),
|
||||
DECLARE_REG (r14, 14),
|
||||
DECLARE_REG (r15, 15),
|
||||
DECLARE_REG (r16, 16),
|
||||
DECLARE_REG (r17, 17),
|
||||
DECLARE_REG (r18, 18),
|
||||
DECLARE_REG (r19, 19),
|
||||
DECLARE_REG (r20, 20),
|
||||
DECLARE_REG (r21, 21),
|
||||
DECLARE_REG (r22, 22),
|
||||
DECLARE_REG (r23, 23),
|
||||
DECLARE_REG (r24, 24),
|
||||
DECLARE_REG (r25, 25),
|
||||
DECLARE_REG (r26, 26),
|
||||
DECLARE_REG (r27, 27),
|
||||
DECLARE_REG (r28, 28),
|
||||
DECLARE_REG (r29, 29),
|
||||
DECLARE_REG (r30, 30),
|
||||
DECLARE_REG (r31, 31),
|
||||
|
||||
/* Alternative names for special registers. */
|
||||
DECLARE_REG (r2, 2),
|
||||
DECLARE_REG (r3, 3),
|
||||
DECLARE_REG (r4, 4)
|
||||
};
|
||||
|
||||
#define PRU_NUM_REGS \
|
||||
((sizeof pru_regs) / (sizeof (pru_regs[0])))
|
||||
const int pru_num_regs = PRU_NUM_REGS;
|
||||
|
||||
#undef PRU_NUM_REGS
|
||||
|
||||
/* This is the opcode table used by the PRU GNU as, disassembler
|
||||
and soon GDB. */
|
||||
const struct pru_opcode pru_opcodes[] =
|
||||
{
|
||||
/* { name, args,
|
||||
match, mask, pinfo, overflow_msg } */
|
||||
#define DECLARE_FORMAT1_OPCODE(str, subop) \
|
||||
{ #str, prui_ ## str, "d,s,b", \
|
||||
OP_MATCH_ ## subop, OP_MASK_FMT1_OP | OP_MASK_SUBOP, 0, \
|
||||
unsigned_immed8_overflow }
|
||||
|
||||
DECLARE_FORMAT1_OPCODE (add, ADD),
|
||||
DECLARE_FORMAT1_OPCODE (adc, ADC),
|
||||
DECLARE_FORMAT1_OPCODE (sub, SUB),
|
||||
DECLARE_FORMAT1_OPCODE (suc, SUC),
|
||||
DECLARE_FORMAT1_OPCODE (lsl, LSL),
|
||||
DECLARE_FORMAT1_OPCODE (lsr, LSR),
|
||||
DECLARE_FORMAT1_OPCODE (rsb, RSB),
|
||||
DECLARE_FORMAT1_OPCODE (rsc, RSC),
|
||||
DECLARE_FORMAT1_OPCODE (and, AND),
|
||||
DECLARE_FORMAT1_OPCODE (or, OR),
|
||||
DECLARE_FORMAT1_OPCODE (xor, XOR),
|
||||
DECLARE_FORMAT1_OPCODE (min, MIN),
|
||||
DECLARE_FORMAT1_OPCODE (max, MAX),
|
||||
DECLARE_FORMAT1_OPCODE (clr, CLR),
|
||||
DECLARE_FORMAT1_OPCODE (set, SET),
|
||||
|
||||
{ "not", prui_not, "d,s",
|
||||
OP_MATCH_NOT | OP_MASK_IO,
|
||||
OP_MASK_FMT1_OP | OP_MASK_SUBOP | OP_MASK_IO, 0, no_overflow},
|
||||
|
||||
{ "jmp", prui_jmp, "j",
|
||||
OP_MATCH_JMP, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow},
|
||||
{ "jal", prui_jal, "d,j",
|
||||
OP_MATCH_JAL, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow},
|
||||
{ "ldi", prui_ldi, "d,W",
|
||||
OP_MATCH_LDI, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow},
|
||||
{ "halt", prui_halt, "",
|
||||
OP_MATCH_HALT, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, no_overflow},
|
||||
{ "slp", prui_slp, "w",
|
||||
OP_MATCH_SLP, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, no_overflow},
|
||||
|
||||
{ "xin", prui_xin, "x,D,n",
|
||||
OP_MATCH_XIN, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow},
|
||||
{ "xout", prui_xout, "x,D,n",
|
||||
OP_MATCH_XOUT, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow},
|
||||
{ "xchg", prui_xchg, "x,D,n",
|
||||
OP_MATCH_XCHG, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow},
|
||||
{ "sxin", prui_sxin, "x,D,n",
|
||||
OP_MATCH_SXIN, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow},
|
||||
{ "sxout", prui_sxout, "x,D,n",
|
||||
OP_MATCH_SXOUT, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow},
|
||||
{ "sxchg", prui_sxchg, "x,D,n",
|
||||
OP_MATCH_SXCHG, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow},
|
||||
|
||||
{ "loop", prui_loop, "O,B",
|
||||
OP_MATCH_LOOP, OP_MASK_LOOP_OP, 0, unsigned_immed8_overflow},
|
||||
{ "iloop", prui_loop, "O,B",
|
||||
OP_MATCH_ILOOP, OP_MASK_LOOP_OP, 0, unsigned_immed8_overflow},
|
||||
|
||||
{ "qbgt", prui_qbgt, "o,s,b",
|
||||
OP_MATCH_QBGT, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow},
|
||||
{ "qbge", prui_qbge, "o,s,b",
|
||||
OP_MATCH_QBGE, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow},
|
||||
{ "qblt", prui_qblt, "o,s,b",
|
||||
OP_MATCH_QBLT, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow},
|
||||
{ "qble", prui_qble, "o,s,b",
|
||||
OP_MATCH_QBLE, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow},
|
||||
{ "qbeq", prui_qbeq, "o,s,b",
|
||||
OP_MATCH_QBEQ, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow},
|
||||
{ "qbne", prui_qbne, "o,s,b",
|
||||
OP_MATCH_QBNE, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow},
|
||||
{ "qba", prui_qba, "o",
|
||||
OP_MATCH_QBA, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow},
|
||||
|
||||
{ "qbbs", prui_qbbs, "o,s,b",
|
||||
OP_MATCH_QBBS, OP_MASK_FMT5_OP | OP_MASK_BCMP, 0, qbranch_target_overflow},
|
||||
{ "qbbc", prui_qbbc, "o,s,b",
|
||||
OP_MATCH_QBBC, OP_MASK_FMT5_OP | OP_MASK_BCMP, 0, qbranch_target_overflow},
|
||||
|
||||
{ "lbbo", prui_lbbo, "D,S,b,l",
|
||||
OP_MATCH_LBBO, OP_MASK_FMT6AB_OP | OP_MASK_LOADSTORE, 0,
|
||||
unsigned_immed8_overflow},
|
||||
{ "sbbo", prui_sbbo, "D,S,b,l",
|
||||
OP_MATCH_SBBO, OP_MASK_FMT6AB_OP | OP_MASK_LOADSTORE, 0,
|
||||
unsigned_immed8_overflow},
|
||||
{ "lbco", prui_lbco, "D,c,b,l",
|
||||
OP_MATCH_LBCO, OP_MASK_FMT6CD_OP | OP_MASK_LOADSTORE, 0,
|
||||
unsigned_immed8_overflow},
|
||||
{ "sbco", prui_sbco, "D,c,b,l",
|
||||
OP_MATCH_SBCO, OP_MASK_FMT6CD_OP | OP_MASK_LOADSTORE, 0,
|
||||
unsigned_immed8_overflow},
|
||||
|
||||
/* Fill in the default values for the real-instruction arguments.
|
||||
The assembler will not do it! */
|
||||
{ "nop", prui_or, "",
|
||||
OP_MATCH_OR
|
||||
| (RSEL_31_0 << OP_SH_RS2SEL) | (0 << OP_SH_RS2)
|
||||
| (RSEL_31_0 << OP_SH_RS1SEL) | (0 << OP_SH_RS1)
|
||||
| (RSEL_31_0 << OP_SH_RDSEL) | (0 << OP_SH_RD),
|
||||
OP_MASK_FMT1_OP | OP_MASK_SUBOP
|
||||
| OP_MASK_RS2SEL | OP_MASK_RS2 | OP_MASK_RS1SEL | OP_MASK_RS1
|
||||
| OP_MASK_RDSEL | OP_MASK_RD | OP_MASK_IO,
|
||||
PRU_INSN_MACRO, no_overflow},
|
||||
{ "mov", prui_or, "d,s",
|
||||
OP_MATCH_OR | (0 << OP_SH_IMM8) | OP_MASK_IO,
|
||||
OP_MASK_FMT1_OP | OP_MASK_SUBOP | OP_MASK_IMM8 | OP_MASK_IO,
|
||||
PRU_INSN_MACRO, no_overflow},
|
||||
{ "ret", prui_jmp, "",
|
||||
OP_MATCH_JMP
|
||||
| (RSEL_31_16 << OP_SH_RS2SEL) | (3 << OP_SH_RS2),
|
||||
OP_MASK_FMT2_OP | OP_MASK_SUBOP
|
||||
| OP_MASK_RS2SEL | OP_MASK_RS2 | OP_MASK_IO,
|
||||
PRU_INSN_MACRO, unsigned_immed16_overflow},
|
||||
{ "call", prui_jal, "j",
|
||||
OP_MATCH_JAL
|
||||
| (RSEL_31_16 << OP_SH_RDSEL) | (3 << OP_SH_RD),
|
||||
OP_MASK_FMT2_OP | OP_MASK_SUBOP
|
||||
| OP_MASK_RDSEL | OP_MASK_RD,
|
||||
PRU_INSN_MACRO, unsigned_immed16_overflow},
|
||||
|
||||
{ "wbc", prui_qbbs, "s,b",
|
||||
OP_MATCH_QBBS | (0 << OP_SH_BROFF98) | (0 << OP_SH_BROFF70),
|
||||
OP_MASK_FMT5_OP | OP_MASK_BCMP | OP_MASK_BROFF,
|
||||
PRU_INSN_MACRO, qbranch_target_overflow},
|
||||
{ "wbs", prui_qbbc, "s,b",
|
||||
OP_MATCH_QBBC | (0 << OP_SH_BROFF98) | (0 << OP_SH_BROFF70),
|
||||
OP_MASK_FMT5_OP | OP_MASK_BCMP | OP_MASK_BROFF,
|
||||
PRU_INSN_MACRO, qbranch_target_overflow},
|
||||
|
||||
{ "fill", prui_xin, "D,n",
|
||||
OP_MATCH_XIN | (254 << OP_SH_XFR_WBA),
|
||||
OP_MASK_XFR_OP | OP_MASK_XFR_WBA,
|
||||
PRU_INSN_MACRO, unsigned_immed8_overflow},
|
||||
{ "zero", prui_xin, "D,n",
|
||||
OP_MATCH_XIN | (255 << OP_SH_XFR_WBA),
|
||||
OP_MASK_XFR_OP | OP_MASK_XFR_WBA,
|
||||
PRU_INSN_MACRO, unsigned_immed8_overflow},
|
||||
|
||||
{ "ldi32", prui_ldi, "R,i",
|
||||
OP_MATCH_LDI, OP_MASK_FMT2_OP | OP_MASK_SUBOP,
|
||||
PRU_INSN_LDI32, unsigned_immed32_overflow},
|
||||
};
|
||||
|
||||
#define PRU_NUM_OPCODES \
|
||||
((sizeof pru_opcodes) / (sizeof (pru_opcodes[0])))
|
||||
const int bfd_pru_num_opcodes = PRU_NUM_OPCODES;
|
||||
|
||||
#undef PRU_NUM_OPCODES
|
||||
Loading…
Reference in New Issue