[ARC] Enhance enter/leave mnemonics.
enter/leave mnemonics are enhanced to not only accept register ranges but also single register (i.e., r13) or even no GPR register at all. gas/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/leave_enter.d: Update test. * testsuite/gas/arc/leave_enter.s: Likewise. opcodes/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. * arc-opc.c (insert_r13el): New function. (R13_EL): Define. * arc-tbl.h: Add new enter/leave variants.
This commit is contained in:
Claudiu Zissulescu
claziss
parent
be6a24d8ea
commit
126124cc0f
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@ -1,3 +1,8 @@
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
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* testsuite/gas/arc/leave_enter.d: Update test.
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* testsuite/gas/arc/leave_enter.s: Likewise.
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
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* testsuite/gas/arc/b.d: Update test.
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@ -1,21 +1,30 @@
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#objdump: -dr
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arc.*
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Disassembly of section .text:
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[0-9a-f]+ <.text>:
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0: c0c2 leave_s \[r13-r13\]
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2: c4dc leave_s \[r13-gp,pcl\]
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4: c1dc leave_s \[r13-gp,fp\]
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6: c2dc leave_s \[r13-gp,blink\]
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8: c3dc leave_s \[r13-gp,fp,blink\]
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a: c5dc leave_s \[r13-gp,fp,pcl\]
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c: c6dc leave_s \[r13-gp,blink,pcl\]
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e: c7dc leave_s \[r13-gp,fp,blink,pcl\]
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10: 1100 0000 ld r0,\[r1\]
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14: c0e2 enter_s \[r13-r13\]
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16: c1fc enter_s \[r13-gp,fp\]
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18: c2fc enter_s \[r13-gp,blink\]
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1a: c3fc enter_s \[r13-gp,fp,blink\]
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0x[0-9a-f]+\s+c0c2\s+leave_s \[r13\]
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0x[0-9a-f]+\s+c0c2\s+leave_s \[r13\]
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0x[0-9a-f]+\s+c4dc\s+leave_s \[r13-gp,pcl\]
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0x[0-9a-f]+\s+c1dc\s+leave_s \[r13-gp,fp\]
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0x[0-9a-f]+\s+c2dc\s+leave_s \[r13-gp,blink\]
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0x[0-9a-f]+\s+c3dc\s+leave_s \[r13-gp,fp,blink\]
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0x[0-9a-f]+\s+c5dc\s+leave_s \[r13-gp,fp,pcl\]
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0x[0-9a-f]+\s+c6dc\s+leave_s \[r13-gp,blink,pcl\]
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0x[0-9a-f]+\s+c7dc\s+leave_s \[r13-gp,fp,blink,pcl\]
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0x[0-9a-f]+\s+c6c2\s+leave_s \[r13,blink,pcl\]
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0x[0-9a-f]+\s+c6c0\s+leave_s \[blink,pcl\]
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0x[0-9a-f]+\s+c1c0\s+leave_s \[fp\]
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0x[0-9a-f]+\s+c2c0\s+leave_s \[blink\]
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0x[0-9a-f]+\s+c4c0\s+leave_s \[pcl\]
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0x[0-9a-f]+\s+1100 0000\s+ld r0,\[r1\]
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0x[0-9a-f]+\s+c0e2\s+enter_s \[r13\]
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0x[0-9a-f]+\s+c0e2\s+enter_s \[r13\]
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0x[0-9a-f]+\s+c1fc\s+enter_s \[r13-gp,fp\]
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0x[0-9a-f]+\s+c2fc\s+enter_s \[r13-gp,blink\]
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0x[0-9a-f]+\s+c3fc\s+enter_s \[r13-gp,fp,blink\]
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0x[0-9a-f]+\s+c2e2\s+enter_s \[r13,blink]
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0x[0-9a-f]+\s+c2e0\s+enter_s \[blink\]
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0x[0-9a-f]+\s+c3e0\s+enter_s \[fp,blink\]
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0x[0-9a-f]+\s+c1e0\s+enter_s \[fp\]
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@ -1,4 +1,5 @@
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.cpu HS
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leave_s {r13}
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leave_s {r13-r13}
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leave_s {r13-r26,pcl}
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leave_s {r13-r26,fp}
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@ -7,10 +8,20 @@
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leave_s {r13-r26,fp,pcl}
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leave_s {r13-r26,blink,pcl}
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leave_s {r13-r26,fp,blink,pcl}
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leave_s {r13,blink,pcl}
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leave_s {blink,pcl}
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leave_s {fp}
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leave_s {blink}
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leave_s {pcl}
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ld r0,[r1]
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enter_s {r13}
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enter_s {r13-r13}
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enter_s {r13-r26,fp}
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enter_s {r13-r26,blink}
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enter_s {r13-r26,fp,blink}
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enter_s {r13,blink}
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enter_s {blink}
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enter_s {fp, blink}
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enter_s {fp}
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@ -1,3 +1,10 @@
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
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* arc-opc.c (insert_r13el): New function.
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(R13_EL): Define.
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* arc-tbl.h: Add new enter/leave variants.
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2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
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@ -1208,9 +1208,22 @@ print_insn_arc (bfd_vma memaddr,
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if (operand->flags & ARC_OPERAND_TRUNCATE
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&& !(operand->flags & ARC_OPERAND_ALIGNED32)
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&& !(operand->flags & ARC_OPERAND_ALIGNED16)
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&& value > 0 && value <= 14)
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(*info->fprintf_func) (info->stream, "r13-%s",
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regnames[13 + value - 1]);
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&& value >= 0 && value <= 14)
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{
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switch (value)
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{
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case 0:
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need_comma = FALSE;
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break;
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case 1:
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(*info->fprintf_func) (info->stream, "r13");
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break;
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default:
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(*info->fprintf_func) (info->stream, "r13-%s",
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regnames[13 + value - 1]);
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break;
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}
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}
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else
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{
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const char *rname = get_auxreg (opcode, value, isa_mask);
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@ -545,6 +545,21 @@ extract_rrange (unsigned long long insn,
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return (insn >> 1) & 0x0F;
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}
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static unsigned long long
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insert_r13el (unsigned long long insn,
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long long int value,
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const char **errmsg)
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{
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if (value != 13)
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{
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*errmsg = _("Invalid register number, should be fp");
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return insn;
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}
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insn |= 0x02;
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return insn;
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}
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static unsigned long long
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insert_fpel (unsigned long long insn,
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long long value,
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@ -1876,7 +1891,10 @@ const struct arc_operand arc_operands[] =
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#define RRANGE_EL (ZA + 1)
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{ 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
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insert_rrange, extract_rrange},
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#define FP_EL (RRANGE_EL + 1)
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#define R13_EL (RRANGE_EL + 1)
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{ 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
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insert_r13el, extract_rrange },
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#define FP_EL (R13_EL + 1)
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{ 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
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insert_fpel, extract_fpel },
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#define BLINK_EL (FP_EL + 1)
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@ -6192,6 +6192,7 @@
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/* enter_s u6 110000UU111uuuu0. */
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{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
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{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
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{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { UIMM6_11_S }, { 0 }},
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/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */
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@ -8230,6 +8231,7 @@
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/* leave_s u7 11000UUU110uuuu0. */
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{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
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{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
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{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { UIMM7_11_S }, { 0 }},
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/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */
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