* m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate.
This commit is contained in:
Doug Evans
parent
b6177e139c
commit
1294c286cb
@ -20,6 +20,7 @@ Mon Apr 27 10:33:56 1998 Doug Evans <devans@seba.cygnus.com>
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(@arch@_cgen_get_insn_operands): Change result type to void.
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Delete args insn_value, length. New arg fields. All callers updated.
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(@arch@_cgen_lookup_get_insn_operands): New function.
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* m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate.
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Fri Apr 24 16:07:57 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
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@ -36,127 +36,33 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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compiled with GCC), or switch to macros, or use something else.
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*/
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static const char * insert_normal
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PARAMS ((long, unsigned int, int, int, int, char *));
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static const char * parse_insn_normal
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PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *));
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static const char * insert_insn_normal
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PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *));
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/* Default insertion routine.
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ATTRS is a mask of the boolean attributes.
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LENGTH is the length of VALUE in bits.
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TOTAL_LENGTH is the total length of the insn (currently 8,16,32).
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The result is an error message or NULL if success. */
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/* ??? This duplicates functionality with bfd's howto table and
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bfd_install_relocation. */
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/* ??? For architectures where insns can be representable as ints,
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store insn in `field' struct and add registers, etc. while parsing? */
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static const char *
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insert_normal (value, attrs, start, length, shift, total_length, buffer)
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long value;
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unsigned int attrs;
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int start;
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int length;
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int shift;
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int total_length;
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char * buffer;
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{
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bfd_vma x;
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static char buf[100];
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if (shift < 0)
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value <<= -shift;
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else
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value >>= shift;
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/* Ensure VALUE will fit. */
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if ((attrs & (1 << CGEN_OPERAND_UNSIGNED)) != 0)
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{
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unsigned long max = (1 << length) - 1;
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if ((unsigned long) value > max)
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{
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const char *err = "operand out of range (%lu not between 0 and %lu)";
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sprintf (buf, err, value, max);
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return buf;
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}
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}
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else
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{
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long min = - (1 << (length - 1));
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long max = (1 << (length - 1)) - 1;
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if (value < min || value > max)
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{
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const char *err = "operand out of range (%ld not between %ld and %ld)";
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sprintf (buf, err, value, min, max);
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return buf;
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}
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}
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#if 0 /*def CGEN_INT_INSN*/
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*buffer |= ((value & ((1 << length) - 1))
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<< (total_length - (start + length)));
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#else
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switch (total_length)
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{
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case 8:
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x = * (unsigned char *) buffer;
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break;
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case 16:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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x = bfd_getb16 (buffer);
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else
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x = bfd_getl16 (buffer);
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break;
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case 32:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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x = bfd_getb32 (buffer);
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else
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x = bfd_getl32 (buffer);
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break;
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default :
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abort ();
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}
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x |= ((value & ((1 << length) - 1))
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<< (total_length - (start + length)));
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switch (total_length)
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{
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case 8:
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* buffer = value;
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break;
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case 16:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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bfd_putb16 (x, buffer);
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else
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bfd_putl16 (x, buffer);
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break;
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case 32:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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bfd_putb32 (x, buffer);
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else
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bfd_putl32 (x, buffer);
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break;
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default :
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abort ();
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}
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#endif
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return NULL;
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}
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/* -- assembler routines inserted here */
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/* -- asm.c */
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/* Handle '#' prefixes (i.e. skip over them). */
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static const char *
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parse_hash (strp, opindex, valuep)
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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if (**strp == '#')
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++*strp;
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return NULL;
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}
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/* Handle shigh(), high(). */
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static const char *
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parse_h_hi16 (strp, opindex, valuep)
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parse_hi16 (strp, opindex, valuep)
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const char **strp;
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int opindex;
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unsigned long *valuep;
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@ -164,7 +70,6 @@ parse_h_hi16 (strp, opindex, valuep)
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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@ -203,7 +108,7 @@ parse_h_hi16 (strp, opindex, valuep)
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handles the case where low() isn't present. */
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static const char *
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parse_h_slo16 (strp, opindex, valuep)
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parse_slo16 (strp, opindex, valuep)
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const char **strp;
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int opindex;
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long *valuep;
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@ -211,7 +116,6 @@ parse_h_slo16 (strp, opindex, valuep)
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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@ -247,7 +151,7 @@ parse_h_slo16 (strp, opindex, valuep)
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handles the case where low() isn't present. */
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static const char *
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parse_h_ulo16 (strp, opindex, valuep)
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parse_ulo16 (strp, opindex, valuep)
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const char **strp;
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int opindex;
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unsigned long *valuep;
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@ -255,7 +159,6 @@ parse_h_ulo16 (strp, opindex, valuep)
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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@ -355,14 +258,17 @@ m32r_cgen_parse_operand (opindex, strp, fields)
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_acc);
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break;
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/* end-sanitize-m32rx */
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case M32R_OPERAND_HASH :
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errmsg = parse_hash (strp, M32R_OPERAND_HASH, &fields->f_nil);
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break;
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case M32R_OPERAND_HI16 :
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errmsg = parse_h_hi16 (strp, M32R_OPERAND_HI16, &fields->f_hi16);
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errmsg = parse_hi16 (strp, M32R_OPERAND_HI16, &fields->f_hi16);
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break;
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case M32R_OPERAND_SLO16 :
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errmsg = parse_h_slo16 (strp, M32R_OPERAND_SLO16, &fields->f_simm16);
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errmsg = parse_slo16 (strp, M32R_OPERAND_SLO16, &fields->f_simm16);
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break;
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case M32R_OPERAND_ULO16 :
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errmsg = parse_h_ulo16 (strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
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errmsg = parse_ulo16 (strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
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break;
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case M32R_OPERAND_UIMM24 :
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errmsg = cgen_parse_address (strp, M32R_OPERAND_UIMM24, 0, NULL, & fields->f_uimm24);
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@ -411,89 +317,92 @@ m32r_cgen_insert_operand (opindex, fields, buffer)
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DR :
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SRC1 :
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SRC2 :
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SCR :
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DCR :
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SIMM8 :
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errmsg = insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SIMM16 :
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errmsg = insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM4 :
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errmsg = insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM5 :
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errmsg = insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM16 :
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errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* start-sanitize-m32rx */
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case M32R_OPERAND_IMM1 :
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{
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long value = ((fields->f_imm1) - (1));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCD :
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errmsg = insert_normal (fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCS :
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errmsg = insert_normal (fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACC :
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errmsg = insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* end-sanitize-m32rx */
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case M32R_OPERAND_HASH :
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errmsg = insert_normal (fields->f_nil, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_HI16 :
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errmsg = insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SLO16 :
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errmsg = insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_simm16, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_ULO16 :
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errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM24 :
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errmsg = insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DISP8 :
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{
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long value = ((fields->f_disp8) >> (2));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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case M32R_OPERAND_DISP16 :
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{
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long value = ((fields->f_disp16) >> (2));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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case M32R_OPERAND_DISP24 :
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{
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long value = ((fields->f_disp24) >> (2));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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@ -524,10 +433,113 @@ m32r_cgen_init_asm (mach, endian)
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enum cgen_endian endian;
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{
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m32r_cgen_init_tables (mach);
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cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
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cgen_set_cpu (& m32r_cgen_opcode_table, mach, endian);
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cgen_asm_init ();
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}
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/* Default insertion routine.
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ATTRS is a mask of the boolean attributes.
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LENGTH is the length of VALUE in bits.
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TOTAL_LENGTH is the total length of the insn (currently 8,16,32).
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The result is an error message or NULL if success. */
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/* ??? This duplicates functionality with bfd's howto table and
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bfd_install_relocation. */
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/* ??? For architectures where insns can be representable as ints,
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store insn in `field' struct and add registers, etc. while parsing? */
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static const char *
|
||||
insert_normal (value, attrs, start, length, total_length, buffer)
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
int start;
|
||||
int length;
|
||||
int total_length;
|
||||
char * buffer;
|
||||
{
|
||||
bfd_vma x;
|
||||
static char buf[100];
|
||||
|
||||
/* Ensure VALUE will fit. */
|
||||
if ((attrs & (1 << CGEN_OPERAND_UNSIGNED)) != 0)
|
||||
{
|
||||
unsigned long max = (1 << length) - 1;
|
||||
if ((unsigned long) value > max)
|
||||
{
|
||||
const char *err = "operand out of range (%lu not between 0 and %lu)";
|
||||
|
||||
sprintf (buf, err, value, max);
|
||||
return buf;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
long min = - (1 << (length - 1));
|
||||
long max = (1 << (length - 1)) - 1;
|
||||
if (value < min || value > max)
|
||||
{
|
||||
const char *err = "operand out of range (%ld not between %ld and %ld)";
|
||||
|
||||
sprintf (buf, err, value, min, max);
|
||||
return buf;
|
||||
}
|
||||
}
|
||||
|
||||
#if 0 /*def CGEN_INT_INSN*/
|
||||
*buffer |= ((value & ((1 << length) - 1))
|
||||
<< (total_length - (start + length)));
|
||||
#else
|
||||
switch (total_length)
|
||||
{
|
||||
case 8:
|
||||
x = * (unsigned char *) buffer;
|
||||
break;
|
||||
case 16:
|
||||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||||
x = bfd_getb16 (buffer);
|
||||
else
|
||||
x = bfd_getl16 (buffer);
|
||||
break;
|
||||
case 32:
|
||||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||||
x = bfd_getb32 (buffer);
|
||||
else
|
||||
x = bfd_getl32 (buffer);
|
||||
break;
|
||||
default :
|
||||
abort ();
|
||||
}
|
||||
|
||||
x |= ((value & ((1 << length) - 1))
|
||||
<< (total_length - (start + length)));
|
||||
|
||||
switch (total_length)
|
||||
{
|
||||
case 8:
|
||||
* buffer = value;
|
||||
break;
|
||||
case 16:
|
||||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||||
bfd_putb16 (x, buffer);
|
||||
else
|
||||
bfd_putl16 (x, buffer);
|
||||
break;
|
||||
case 32:
|
||||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||||
bfd_putb32 (x, buffer);
|
||||
else
|
||||
bfd_putl32 (x, buffer);
|
||||
break;
|
||||
default :
|
||||
abort ();
|
||||
}
|
||||
#endif
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Default insn parser.
|
||||
|
||||
@ -707,9 +719,14 @@ insert_insn_normal (insn, fields, buffer)
|
||||
This routine is called for each instruction to be assembled.
|
||||
STR points to the insn to be assembled.
|
||||
We assume all necessary tables have been initialized.
|
||||
The assembled instruction, less any fixups, is stored in buf.
|
||||
[??? What byte order?]
|
||||
The result is a pointer to the insn's entry in the opcode table,
|
||||
or NULL if an error occured (an error message will have already been
|
||||
printed). */
|
||||
printed).
|
||||
|
||||
Note that when processing (non-alias) macro-insns,
|
||||
this function recurses. */
|
||||
|
||||
const CGEN_INSN *
|
||||
m32r_cgen_assemble_insn (str, fields, buf, errmsg)
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
This file is used to generate m32r-dis.c.
|
||||
|
||||
Copyright (C) 1996, 1997 Free Software Foundation, Inc.
|
||||
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Binutils and GDB, the GNU debugger.
|
||||
|
||||
@ -46,57 +46,32 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
static int print_insn PARAMS ((bfd_vma, disassemble_info *, char *, int));
|
||||
|
||||
static int extract_normal
|
||||
PARAMS ((PTR, cgen_insn_t, unsigned int, int, int, int, long *));
|
||||
static void print_normal
|
||||
PARAMS ((PTR, long, unsigned int, unsigned long, int));
|
||||
static void print_keyword
|
||||
PARAMS ((PTR, CGEN_KEYWORD *, long, unsigned int));
|
||||
static int extract_insn_normal
|
||||
PARAMS ((const CGEN_INSN *, void *, cgen_insn_t, CGEN_FIELDS *));
|
||||
static void print_insn_normal
|
||||
PARAMS ((void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int));
|
||||
|
||||
/* Default extraction routine.
|
||||
/* -- disassembler routines inserted here */
|
||||
/* -- dis.c */
|
||||
|
||||
ATTRS is a mask of the boolean attributes. We only need `unsigned',
|
||||
but for generality we take a bitmask of all of them. */
|
||||
/* Immediate values are prefixed with '#'. */
|
||||
|
||||
static int
|
||||
extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep)
|
||||
PTR buf_ctrl;
|
||||
cgen_insn_t insn_value;
|
||||
unsigned int attrs;
|
||||
int start, length, shift, total_length;
|
||||
long *valuep;
|
||||
{
|
||||
long value;
|
||||
#define CGEN_PRINT_NORMAL(info, value, attrs, pc, length) \
|
||||
do { \
|
||||
if ((attrs) & (1 << CGEN_OPERAND_HASH_PREFIX)) \
|
||||
(*info->fprintf_func) (info->stream, "#"); \
|
||||
} while (0)
|
||||
|
||||
#ifdef CGEN_INT_INSN
|
||||
#if 0
|
||||
value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length)))
|
||||
& ((1 << length) - 1));
|
||||
#else
|
||||
value = ((insn_value >> (total_length - (start + length)))
|
||||
& ((1 << length) - 1));
|
||||
#endif
|
||||
if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
|
||||
&& (value & (1 << (length - 1))))
|
||||
value -= 1 << length;
|
||||
#else
|
||||
/* FIXME: unfinished */
|
||||
#endif
|
||||
|
||||
/* This is backwards as we undo the effects of insert_normal. */
|
||||
if (shift < 0)
|
||||
value >>= -shift;
|
||||
else
|
||||
value <<= shift;
|
||||
|
||||
*valuep = value;
|
||||
|
||||
/* FIXME: for now */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Default print handler. */
|
||||
/* Handle '#' prefixes as operands. */
|
||||
|
||||
static void
|
||||
print_normal (dis_info, value, attrs, pc, length)
|
||||
print_hash (dis_info, value, attrs, pc, length)
|
||||
PTR dis_info;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
@ -104,44 +79,9 @@ print_normal (dis_info, value, attrs, pc, length)
|
||||
int length;
|
||||
{
|
||||
disassemble_info *info = dis_info;
|
||||
|
||||
/* Print the operand as directed by the attributes. */
|
||||
if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE))
|
||||
; /* nothing to do (??? at least not yet) */
|
||||
else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_PCREL_ADDR))
|
||||
(*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info);
|
||||
/* ??? Not all cases of this are currently caught. */
|
||||
else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_ABS_ADDR))
|
||||
/* FIXME: Why & 0xffffffff? */
|
||||
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
||||
else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
|
||||
(*info->fprintf_func) (info->stream, "0x%lx", value);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%ld", value);
|
||||
(*info->fprintf_func) (info->stream, "#");
|
||||
}
|
||||
|
||||
/* Keyword print handler. */
|
||||
|
||||
static void
|
||||
print_keyword (dis_info, keyword_table, value, attrs)
|
||||
PTR dis_info;
|
||||
CGEN_KEYWORD *keyword_table;
|
||||
long value;
|
||||
CGEN_ATTR *attrs;
|
||||
{
|
||||
disassemble_info *info = dis_info;
|
||||
const CGEN_KEYWORD_ENTRY *ke;
|
||||
|
||||
ke = cgen_keyword_lookup_value (keyword_table, value);
|
||||
if (ke != NULL)
|
||||
(*info->fprintf_func) (info->stream, "%s", ke->name);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "???");
|
||||
}
|
||||
|
||||
/* -- disassembler routines inserted here */
|
||||
/* -- dis.c */
|
||||
|
||||
#undef CGEN_PRINT_INSN
|
||||
#define CGEN_PRINT_INSN my_print_insn
|
||||
|
||||
@ -209,92 +149,95 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
|
||||
switch (opindex)
|
||||
{
|
||||
case M32R_OPERAND_SR :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
|
||||
break;
|
||||
case M32R_OPERAND_DR :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
|
||||
break;
|
||||
case M32R_OPERAND_SRC1 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
|
||||
break;
|
||||
case M32R_OPERAND_SRC2 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
|
||||
break;
|
||||
case M32R_OPERAND_SCR :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
|
||||
break;
|
||||
case M32R_OPERAND_DCR :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
|
||||
break;
|
||||
case M32R_OPERAND_SIMM8 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm8);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 8, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm8);
|
||||
break;
|
||||
case M32R_OPERAND_SIMM16 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM4 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm4);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm4);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM5 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm5);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm5);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM16 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
|
||||
break;
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_IMM1 :
|
||||
{
|
||||
long value;
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
fields->f_imm1 = ((value) + (1));
|
||||
}
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCD :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_accd);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_accd);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACCS :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_accs);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_accs);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_ACC :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_acc);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, CGEN_FIELDS_BITSIZE (fields), & fields->f_acc);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
case M32R_OPERAND_HASH :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil);
|
||||
break;
|
||||
case M32R_OPERAND_HI16 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_hi16);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_hi16);
|
||||
break;
|
||||
case M32R_OPERAND_SLO16 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
|
||||
break;
|
||||
case M32R_OPERAND_ULO16 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM24 :
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm24);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm24);
|
||||
break;
|
||||
case M32R_OPERAND_DISP8 :
|
||||
{
|
||||
long value;
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
fields->f_disp8 = ((value) << (2));
|
||||
}
|
||||
break;
|
||||
case M32R_OPERAND_DISP16 :
|
||||
{
|
||||
long value;
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
fields->f_disp16 = ((value) << (2));
|
||||
}
|
||||
break;
|
||||
case M32R_OPERAND_DISP24 :
|
||||
{
|
||||
long value;
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, CGEN_FIELDS_BITSIZE (fields), & value);
|
||||
fields->f_disp24 = ((value) << (2));
|
||||
}
|
||||
break;
|
||||
@ -352,23 +295,23 @@ m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
|
||||
print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
|
||||
break;
|
||||
case M32R_OPERAND_SIMM8 :
|
||||
print_normal (info, fields->f_simm8, 0, pc, length);
|
||||
print_normal (info, fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
|
||||
break;
|
||||
case M32R_OPERAND_SIMM16 :
|
||||
print_normal (info, fields->f_simm16, 0, pc, length);
|
||||
print_normal (info, fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM4 :
|
||||
print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM5 :
|
||||
print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM16 :
|
||||
print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
/* start-sanitize-m32rx */
|
||||
case M32R_OPERAND_IMM1 :
|
||||
print_normal (info, fields->f_imm1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
print_normal (info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
@ -386,6 +329,9 @@ m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
|
||||
print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
|
||||
break;
|
||||
/* end-sanitize-m32rx */
|
||||
case M32R_OPERAND_HASH :
|
||||
print_hash (info, fields->f_nil, 0, pc, length);
|
||||
break;
|
||||
case M32R_OPERAND_HI16 :
|
||||
print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
@ -396,7 +342,7 @@ m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
|
||||
print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
case M32R_OPERAND_UIMM24 :
|
||||
print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
|
||||
break;
|
||||
case M32R_OPERAND_DISP8 :
|
||||
print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
|
||||
@ -434,10 +380,96 @@ m32r_cgen_init_dis (mach, endian)
|
||||
enum cgen_endian endian;
|
||||
{
|
||||
m32r_cgen_init_tables (mach);
|
||||
cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
|
||||
cgen_set_cpu (& m32r_cgen_opcode_table, mach, endian);
|
||||
cgen_dis_init ();
|
||||
}
|
||||
|
||||
|
||||
/* Default extraction routine.
|
||||
|
||||
ATTRS is a mask of the boolean attributes. We only need `unsigned',
|
||||
but for generality we take a bitmask of all of them. */
|
||||
|
||||
static int
|
||||
extract_normal (buf_ctrl, insn_value, attrs, start, length, total_length, valuep)
|
||||
PTR buf_ctrl;
|
||||
cgen_insn_t insn_value;
|
||||
unsigned int attrs;
|
||||
int start, length, total_length;
|
||||
long *valuep;
|
||||
{
|
||||
long value;
|
||||
|
||||
#ifdef CGEN_INT_INSN
|
||||
#if 0
|
||||
value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length)))
|
||||
& ((1 << length) - 1));
|
||||
#else
|
||||
value = ((insn_value >> (total_length - (start + length)))
|
||||
& ((1 << length) - 1));
|
||||
#endif
|
||||
if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
|
||||
&& (value & (1 << (length - 1))))
|
||||
value -= 1 << length;
|
||||
#else
|
||||
/* FIXME: unfinished */
|
||||
#endif
|
||||
|
||||
*valuep = value;
|
||||
|
||||
/* FIXME: for now */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Default print handler. */
|
||||
|
||||
static void
|
||||
print_normal (dis_info, value, attrs, pc, length)
|
||||
PTR dis_info;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
unsigned long pc; /* FIXME: should be bfd_vma */
|
||||
int length;
|
||||
{
|
||||
disassemble_info *info = dis_info;
|
||||
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
CGEN_PRINT_NORMAL (info, value, attrs, pc, length);
|
||||
#endif
|
||||
|
||||
/* Print the operand as directed by the attributes. */
|
||||
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_FAKE))
|
||||
; /* nothing to do (??? at least not yet) */
|
||||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
|
||||
(*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info);
|
||||
/* ??? Not all cases of this are currently caught. */
|
||||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
|
||||
/* FIXME: Why & 0xffffffff? */
|
||||
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
||||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
|
||||
(*info->fprintf_func) (info->stream, "0x%lx", value);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%ld", value);
|
||||
}
|
||||
|
||||
/* Keyword print handler. */
|
||||
|
||||
static void
|
||||
print_keyword (dis_info, keyword_table, value, attrs)
|
||||
PTR dis_info;
|
||||
CGEN_KEYWORD *keyword_table;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
{
|
||||
disassemble_info *info = dis_info;
|
||||
const CGEN_KEYWORD_ENTRY *ke;
|
||||
|
||||
ke = cgen_keyword_lookup_value (keyword_table, value);
|
||||
if (ke != NULL)
|
||||
(*info->fprintf_func) (info->stream, "%s", ke->name);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "???");
|
||||
}
|
||||
|
||||
/* Default insn extractor.
|
||||
|
||||
|
||||
1533
opcodes/m32r-opc.c
1533
opcodes/m32r-opc.c
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user