* opcodes/ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt, efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid, efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz, efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
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e05389b893
commit
12c64a4e4d
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@ -1,3 +1,11 @@
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2004-10-06 Aldy Hernandez <aldyh@redhat.com>
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* ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
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efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
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efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
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efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
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efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
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2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
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* pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
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@ -1958,6 +1958,41 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
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{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
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/* Double-precision opcodes. */
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/* Some of these conflict with AltiVec, so move them before, since
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PPCVEC includes the PPC_OPCODE_PPC set. */
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{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RA } },
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{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
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{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
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{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
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{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
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{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
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{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
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{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
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{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
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{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
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{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
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{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
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/* End of double-precision opcodes. */
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{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
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