i386: Check vector length for EVEX vextractfXX and vinsertfXX
Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
This commit is contained in:
H.J. Lu
parent
62d8e3b731
commit
12efd68d15
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@ -1,3 +1,12 @@
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2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/24633
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* testsuite/gas/i386/disassem.s: Add tests for invalid vector
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lengths for EVEX vextractfXX and vinsertfXX.
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* testsuite/gas/i386/x86-64-disassem.s: Likewise.
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* testsuite/gas/i386/disassem.d: Updated.
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* testsuite/gas/i386/x86-64-disassem.d: Likewise.
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2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/24626
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@ -345,5 +345,8 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*41[ ]*inc[ ]*%ecx
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[ ]*[a-f0-9]+:[ ]*37[ ]*aaa[ ]*
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[ ]*[a-f0-9]+:[ ]*62 f2 ad 08 1c[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*01[ ]*.byte[ ]*0x1
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[ ]*[a-f0-9]+:[ ]*01 01[ ]*add[ ]*%eax,\(%ecx\)
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[ ]*[a-f0-9]+:[ ]*62 f3 7d 28 1b[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*c8[ ]*.byte[ ]*0xc8
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[ ]*[a-f0-9]+:[ ]*25[ ]*.byte[ ]*0x25
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#pass
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@ -169,3 +169,5 @@
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
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.byte 0xc4, 0xe2, 0x1, 0x1c, 0x41, 0x37
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.byte 0x62, 0xf2, 0xad, 0x08, 0x1c, 0x01
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.byte 0x1
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.byte 0x62, 0xf3, 0x7d, 0x28, 0x1b, 0xc8, 0x25
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@ -344,5 +344,8 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*c4 62 01 1c[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*41 37[ ]*rex.B \(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*62 72 ad 08 1c[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*01[ ]*.byte[ ]*0x1
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[ ]*[a-f0-9]+:[ ]*01 01[ ]*add[ ]*%eax,\(%rcx\)
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[ ]*[a-f0-9]+:[ ]*62 f3 7d 28 1b[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*c8[ ]*.byte[ ]*0xc8
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[ ]*[a-f0-9]+:[ ]*25[ ]*.byte[ ]*0x25
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#pass
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@ -169,3 +169,5 @@
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
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.byte 0xc4, 0x62, 0x1, 0x1c, 0x41, 0x37
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.byte 0x62, 0x72, 0xad, 0x08, 0x1c, 0x01
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.byte 0x1
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.byte 0x62, 0xf3, 0x7d, 0x28, 0x1b, 0xc8, 0x25
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@ -1,3 +1,22 @@
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2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/24633
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* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
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EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
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(evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
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EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
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EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
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EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
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EVEX_LEN_0F3A1B_P_2_W_1.
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* i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
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(EVEX_LEN_0F3A18_P_2_W_1): Likewise.
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(EVEX_LEN_0F3A19_P_2_W_0): Likewise.
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(EVEX_LEN_0F3A19_P_2_W_1): Likewise.
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(EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
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(EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
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(EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
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(EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
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2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/24626
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@ -3912,23 +3912,23 @@ static const struct dis386 evex_table[][256] = {
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},
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/* EVEX_W_0F3A18_P_2 */
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{
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{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, 0 },
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{ "vinsertf64x2", { XM, Vex, EXxmm, Ib }, 0 },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A18_P_2_W_0) },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A18_P_2_W_1) },
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},
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/* EVEX_W_0F3A19_P_2 */
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{
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{ "vextractf32x4", { EXxmm, XM, Ib }, 0 },
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{ "vextractf64x2", { EXxmm, XM, Ib }, 0 },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A19_P_2_W_0) },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A19_P_2_W_1) },
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},
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/* EVEX_W_0F3A1A_P_2 */
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{
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{ "vinsertf32x8", { XM, Vex, EXxmmq, Ib }, 0 },
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{ "vinsertf64x4", { XM, Vex, EXxmmq, Ib }, 0 },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1A_P_2_W_0) },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1A_P_2_W_1) },
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},
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/* EVEX_W_0F3A1B_P_2 */
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{
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{ "vextractf32x8", { EXxmmq, XM, Ib }, 0 },
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{ "vextractf64x4", { EXxmmq, XM, Ib }, 0 },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1B_P_2_W_0) },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1B_P_2_W_1) },
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},
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/* EVEX_W_0F3A1D_P_2 */
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{
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@ -4129,4 +4129,60 @@ static const struct dis386 evex_table[][256] = {
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{ VEX_W_TABLE (EVEX_W_0FD6_P_2) },
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},
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/* EVEX_LEN_0F3A18_P_2_W_0 */
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{
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{ Bad_Opcode },
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{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, 0 },
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{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, 0 },
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},
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/* EVEX_LEN_0F3A18_P_2_W_1 */
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{
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{ Bad_Opcode },
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{ "vinsertf64x2", { XM, Vex, EXxmm, Ib }, 0 },
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{ "vinsertf64x2", { XM, Vex, EXxmm, Ib }, 0 },
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},
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/* EVEX_LEN_0F3A19_P_2_W_0 */
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{
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{ Bad_Opcode },
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{ "vextractf32x4", { EXxmm, XM, Ib }, 0 },
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{ "vextractf32x4", { EXxmm, XM, Ib }, 0 },
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},
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/* EVEX_LEN_0F3A19_P_2_W_1 */
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{
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{ Bad_Opcode },
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{ "vextractf64x2", { EXxmm, XM, Ib }, 0 },
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{ "vextractf64x2", { EXxmm, XM, Ib }, 0 },
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},
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/* EVEX_LEN_0F3A1A_P_2_W_0 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vinsertf32x8", { XM, Vex, EXxmmq, Ib }, 0 },
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},
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/* EVEX_LEN_0F3A1A_P_2_W_1 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vinsertf64x4", { XM, Vex, EXxmmq, Ib }, 0 },
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},
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/* EVEX_LEN_0F3A1B_P_2_W_0 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vextractf32x8", { EXxmmq, XM, Ib }, 0 },
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},
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/* EVEX_LEN_0F3A1B_P_2_W_1 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vextractf64x4", { EXxmmq, XM, Ib }, 0 },
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},
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#endif /* NEED_EVEX_LEN_TABLE */
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@ -1937,7 +1937,15 @@ enum
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EVEX_LEN_0F6E_P_2 = 0,
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EVEX_LEN_0F7E_P_1,
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EVEX_LEN_0F7E_P_2,
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EVEX_LEN_0FD6_P_2
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EVEX_LEN_0FD6_P_2,
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EVEX_LEN_0F3A18_P_2_W_0,
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EVEX_LEN_0F3A18_P_2_W_1,
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EVEX_LEN_0F3A19_P_2_W_0,
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EVEX_LEN_0F3A19_P_2_W_1,
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EVEX_LEN_0F3A1A_P_2_W_0,
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EVEX_LEN_0F3A1A_P_2_W_1,
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EVEX_LEN_0F3A1B_P_2_W_0,
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EVEX_LEN_0F3A1B_P_2_W_1
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};
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enum
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