Check v850eq popm[hl] instructions.

Check v850 NMI/RETI.

sim/testsuite/v850eq-elf/Makefile.in

@@ -36,6 +36,7 @@ target_cpu = @target_cpu@
 SHELL = /bin/sh
 SUBDIRS = @subdirs@
 RPATH_ENVVAR = @RPATH_ENVVAR@
+INTFLAGS_FOR_TARGET=--watch-cycles-nmi=+100
 
 EXPECT = `if [ -f $${rootme}/../../expect/expect ] ; then \
           echo $${rootme}/../../expect/expect ; \
@@ -82,6 +83,7 @@ RUN_FOR_TARGET = `\
 TESTS= \
 	hello.hi \
 	exit47.ko \
+	tick.ti \
 	\
 	t-bsh.ok \
 	t-bsw.ok \
@@ -93,6 +95,8 @@ TESTS= \
 	t-jmp.ok \
 	t-jr.ok \
 	t-ldsr.ok \
+	t-popml.ok \
+	t-popmh.ok \
 	t-sld.ok \
 	t-sxb.ok \
 	t-sxh.ok \
@@ -105,9 +109,14 @@ sanity:
 	@eval echo LD_FOR_TARGET=$(LD_FOR_TARGET)
 	@eval echo RUN_FOR_TARGET=$(RUN_FOR_TARGET)
 
+clean:
+	rm -f $(TESTS)
+	rm -f *.run *.o
+	rm -f core *.core
+
 # Rules for running the tests
 
-.SUFFIXES: .ok .run .hi .ko
+.SUFFIXES: .ok .run .hi .ko .ti
 .run.ok:
 	rm -f tmp-$* $*.hi
 	ulimit -t 5 ; \
@@ -130,7 +139,14 @@ sanity:
 	  exit 1 ; \
 	fi
 	mv tmp-$* $*.ko
-
+.run.ti:
+	rm -f tmp-$* $*.ti
+	set +e ; \
+	ulimit -t 5 ; \
+	$(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $(INTFLAGS_FOR_TARGET) $*.run > tmp-$*
+	test `cat tmp-$* | wc -l` -eq 10 < /dev/null
+	test `grep Tick tmp-$* | wc -l` -eq 10 < /dev/null
+	mv tmp-$* $*.ti
 
 # Rules for building the test
 # Preference is for obtaining the executable (.run) from a prebuilt image
@@ -148,3 +164,10 @@ sanity:
 .S.o:
 	$(AS_FOR_TARGET) $(ASFLAGS_FOR_TARGET) -I$(srcdir) $(srcdir)/$*.S -o $*.o
 # NNN
+
+Makefile: Makefile.in config.status
+	$(SHELL) ./config.status
+
+config.status: configure
+	$(SHELL) ./config.status --recheck
+

sim/testsuite/v850eq-elf/t-macros.i

@@ -62,3 +62,7 @@ _start:
 	PSW_S = 0x2
 	PSW_Z = 0x1
 
+
+# definitions of various interrupt addresses
+	INT_RESET = 0x0
+	INT_NMI = 0x10

sim/testsuite/v850eq-elf/t-popmh.s

@@ -0,0 +1,104 @@
+.include "t-macros.i"
+
+	start
+
+	load sp stackEI
+	ldsr r0, psw    # ENSURE NP=EP=0
+test_popmh_EI:
+	popmh {eipc, eipsw}
+	# check EIPSW
+	stsr eipsw, r3
+	check1 r3 0xe0
+	ldsr r0, eipsw
+	# check EIPC
+	stsr eipc, r3
+	check1 r3 0xec
+	ldsr r0, eipc
+
+
+	
+	mov PSW_NP, r1
+	ldsr r1, psw   # ENSURE NP=1, EP=0
+	load sp stackFE
+test_popmh_FE:
+	popmh {fepc, fepsw}
+	# check FEPSW
+	stsr fepsw, r3
+	check1 r3 0xf0
+	ldsr r0, fepsw
+	# check FEPC
+	stsr fepc, r3
+	check1 r3 0xfc
+	ldsr r0, fepc
+	
+
+	load sp stackR
+test_popmh_R:
+	popmh {r16,r17,r18,r19,r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30,r31}
+	check1 r16 16
+	mov 0, r16
+	check1 r17 17
+	mov 0, r17
+	check1 r18 18
+	mov 0, r18
+	check1 r19 19
+	mov 0, r19
+	check1 r20 20
+	mov 0, r20
+	check1 r21 21
+	mov 0, r21
+	check1 r22 22
+	mov 0, r22
+	check1 r23 23
+	mov 0, r23
+	check1 r24 24
+	mov 0, r24
+	check1 r25 25
+	mov 0, r25
+	check1 r26 26
+	mov 0, r26
+	check1 r27 27
+	mov 0, r27
+	check1 r28 28
+	mov 0, r28
+	check1 r29 29
+	mov 0, r29
+	check1 r30 30
+	mov 0, r30
+	check1 r31 31
+	mov 0, r31
+
+	exit0
+
+	.align 2
+stackEI:
+	.long 0xe0 #EIPSW
+	.long 0xec #EIPC
+
+
+stackFE:
+	.long 0xf0 #FEPSW
+	.long 0xfc #FEPC
+
+
+stackR:
+	.long 31
+	.long 30
+	.long 29
+	.long 28
+	.long 27
+	.long 26
+	.long 25
+	.long 24
+	.long 23
+	.long 22
+	.long 21
+	.long 20
+	.long 19
+	.long 18
+	.long 17
+	.long 16
+
+
+stackPSW:
+	.long 0xee

sim/testsuite/v850eq-elf/t-popml.s

@@ -0,0 +1,109 @@
+.include "t-macros.i"
+
+	start
+
+	load sp stackEI
+	ldsr r0, psw    # ENSURE NP=EP=0
+test_popml_EI:
+	popml {eipc, eipsw}
+	# check EIPSW
+	stsr eipsw, r3
+	check1 r3 0xe0
+	ldsr r0, eipsw
+	# check EIPC
+	stsr eipc, r3
+	check1 r3 0xec
+	ldsr r0, eipc
+
+
+	
+	mov PSW_NP, r1
+	ldsr r1, psw   # ENSURE NP=1, EP=0
+	load sp stackFE
+test_popml_FE:
+	popml {fepc, fepsw}
+	# check FEPSW
+	stsr fepsw, r3
+	check1 r3 0xf0
+	ldsr r0, fepsw
+	# check FEPC
+	stsr fepc, r3
+	check1 r3 0xfc
+	ldsr r0, fepc
+	
+
+	load sp stackR
+test_popml_R:
+	popml {r1,r2,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15}
+	mov r1, r3
+	check1 r3 1
+	mov 0, r3
+	check1 r2 2
+	mov 0, r2
+	#check1 r3 3
+	check1 r4 4
+	mov 0, r4
+	check1 r5 5
+	mov 0, r5
+	check1 r6 6
+	mov 0, r6
+	check1 r7 7
+	mov 0, r7
+	check1 r8 8
+	mov 0, r8
+	check1 r9 9
+	mov 0, r9
+	check1 r10 10
+	mov 0, r10
+	check1 r11 11
+	mov 0, r11
+	check1 r12 12
+	mov 0, r12
+	check1 r13 13
+	mov 0, r13
+	check1 r14 14
+	mov 0, r14
+	check1 r15 15
+	mov 0, r15
+
+
+	load sp, stackPSW
+test_popml_PSW:
+	popml {psw}
+	stsr psw, r2
+	check1 r2, 0xee
+
+
+	exit0
+
+	.align 2
+stackEI:
+	.long 0xe0 #EIPSW
+	.long 0xec #EIPC
+
+
+stackFE:
+	.long 0xf0 #FEPSW
+	.long 0xfc #FEPC
+
+
+stackR:
+	.long 15
+	.long 14
+	.long 13
+	.long 12
+	.long 11
+	.long 10
+	.long  9
+	.long  8
+	.long  7
+	.long  6
+	.long  5
+	.long  4
+	#.long  3 - sp
+	.long  2
+	.long  1
+
+
+stackPSW:
+	.long 0xee

sim/testsuite/v850eq-elf/tick.s

@@ -0,0 +1,42 @@
+.include "t-macros.i"
+
+	start
+
+	# Establish `interrupt..einterrupt' at the NMI interrupt address
+	load r1 interrupt
+	load r2 einterrupt
+	load r3 INT_NMI
+copy:	ld.b 0[r1], r4
+	st.b r4, 0[r3]
+	add 1, r1
+	add 1, r3
+	cmp r1, r2
+	bge copy
+
+	# Keep looping until r1 becomes non zero - a tick
+	mov 0, r1
+	mov 0, r2
+loop:	cmp 0, r1
+	be loop
+
+	# Print the message indicating that a tick was encountered
+	mov 4, r6
+	mov 1, r7                 # FID
+	load r8 tick              # string
+	load r9 etick-tick        # size
+	trap 31
+	mov 0, r1
+	add 1, r2
+	cmp 10, r2
+	blt loop
+
+	exit0
+
+interrupt:
+	mov 1, r1
+	reti
+einterrupt:	
+
+	.data
+tick:	.ascii "Tick\n"
+etick: