* opcode/hppa.h: Fix templates for all the sfu and copr
instructions.
This commit is contained in:
Jeff Law
parent
623d738026
commit
13a343993f
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@ -1,3 +1,30 @@
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Mon Jan 17 00:12:19 1994 Jeffrey A. Law (law@snake.cs.utah.edu)
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* opcode/hppa.h: Fix templates for all the sfu and copr
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instructions.
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Thu Jan 6 14:15:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
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* bfdlink.h (struct bfd_link_callbacks): Add bitsize argument to
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add_to_set field. Add new callback named constructor.
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Thu Dec 30 10:44:06 1993 Ian Lance Taylor (ian@rtl.cygnus.com)
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* bfdlink.h: New file for new BFD linker backend routines.
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Mon Nov 29 10:43:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
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* dis-asm.h (enum dis_insn_tyupe): Remove non-ANSI trailing comma.
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Sat Oct 2 20:42:26 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
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* dis-asm.h: Move comment to right place.
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Mon Aug 9 19:03:35 1993 David J. Mackenzie (djm@thepub.cygnus.com)
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* obstack.h (obstack_chunkfun, obstack_freefun): Add defns from
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previous version. Are these Cygnus local changes?
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Fri Aug 6 17:05:47 1993 David J. Mackenzie (djm@thepub.cygnus.com)
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* getopt.h, obstack.h: Update to latest FSF version.
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@ -31,7 +31,11 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* There are two kinds of delay slot nullification: normal which is
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* controled by the nullification bit, and conditional, which depends
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* on the direction of the branch and its success or failure.
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*
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* NONE is unfortunately #defined in the hiux system include files.
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* #undef it away.
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*/
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#undef NONE
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enum delay_type {NONE, NORMAL, CONDITIONAL};
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struct pa_opcode
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{
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@ -66,7 +70,7 @@ struct pa_opcode
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In the args field, the following characters are unused:
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' "#$% *+- ./ 3 :; = @'
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' B L N [\] _'
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' B L [\] _'
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' e gh lm qr { } '
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Here are all the characters:
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@ -98,6 +102,7 @@ Kinds of operands:
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j 14 bit immediate value at 31
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k 21 bit immediate value at 31
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n nullification for branch instructions
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N nullification for spop and copr instructions
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w 12 bit branch displacement
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W 17 bit branch displacement (PC relative)
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z 17 bit branch displacement (just a number, not an address)
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@ -137,7 +142,7 @@ Also these:
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r 5 bit immediate value at 31 (for the break instruction)
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(very similar to V above, except the value is unsigned instead of
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low_sign_ext)
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R 5 bit immediate value at 15 (for the ssm, rsm instruction)
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R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
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(same as r above, except the value is in a different location)
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Q 5 bit immediate value at 10 (a bit position specified in
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the bb instruction. It's the same as r above, except the
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@ -328,12 +333,12 @@ static const struct pa_opcode pa_opcodes[] =
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{ "sync", 0x00000400, 0xffffffff, ""},
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{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t"},
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{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t"},
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{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),5,t"},
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{ "proberi", 0x04003180, 0xfc003fe0, "(b),5,t"},
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{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t"},
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{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t"},
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{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t"},
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{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t"},
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{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),5,t"},
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{ "probewi", 0x040031c0, 0xfc003fe0, "(b),5,t"},
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{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t"},
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{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t"},
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{ "lpa", 0x04001340, 0xfc003fc0, "Zx(s,b),t"},
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{ "lpa", 0x04001340, 0xfc003fc0, "Zx(b),t"},
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{ "lha", 0x04001300, 0xfc003fc0, "Zx(s,b),t"},
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@ -365,6 +370,9 @@ static const struct pa_opcode pa_opcodes[] =
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{ "fice", 0x040002c0, 0xfc003fdf, "Zx(s,b)"},
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{ "fice", 0x040002c0, 0xfc003fdf, "Zx(b)"},
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{ "diag", 0x14000000, 0xfc000000, "D"},
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/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
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the Timex FPU or the Mustang ERS (not sure which) manual. */
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{ "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)"},
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{ "gfw", 0x04001680, 0xfc003fdf, "Zx(b)"},
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{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(s,b)"},
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@ -380,6 +388,8 @@ static const struct pa_opcode pa_opcodes[] =
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{ "fstwx", 0x24000200, 0xfc001fc0, "cv,x(b)"},
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{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(s,b)"},
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{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(b)"},
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{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(s,b)"},
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{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(b)"},
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{ "fldws", 0x24001000, 0xfc001f80, "C5(s,b),v"},
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{ "fldws", 0x24001000, 0xfc001f80, "C5(b),v"},
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{ "fldds", 0x2c001000, 0xfc001fc0, "C5(s,b),y"},
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@ -388,6 +398,8 @@ static const struct pa_opcode pa_opcodes[] =
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{ "fstws", 0x24001200, 0xfc001f80, "Cy,5(b)"},
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{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(s,b)"},
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{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(b)"},
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{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(s,b)"},
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{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(b)"},
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{ "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v"},
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{ "fadd", 0x38000600, 0xfc00e720, "IJ,K,v"},
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{ "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v"},
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@ -424,27 +436,27 @@ static const struct pa_opcode pa_opcodes[] =
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/* Assist Instructions */
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{ "spop0", 0x10000000, 0xfc000600, ",f,On", NORMAL},
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{ "spop1", 0x10000200, 0xfc000600, ",f,ont", NORMAL},
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{ "spop2", 0x10000400, 0xfc000600, ",f,1nb", NORMAL},
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{ "spop3", 0x10000600, 0xfc000600, ",f,0nx,b", NORMAL},
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{ "copr", 0x30000000, 0xfc000000, ",u,2n", NORMAL},
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{ "cldwx", 0x24000000, 0xfc001e00, ",u,Zx(s,b),t"},
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{ "cldwx", 0x24000000, 0xfc001e00, ",u,Zx(b),t"},
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{ "clddx", 0x2c000000, 0xfc001e00, ",u,Zx(s,b),t"},
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{ "clddx", 0x2c000000, 0xfc001e00, ",u,Zx(b),t"},
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{ "cstwx", 0x24000200, 0xfc001e00, ",u,Zt,x(s,b)"},
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{ "cstwx", 0x24000200, 0xfc001e00, ",u,Zt,x(b)"},
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{ "cstdx", 0x2c000200, 0xfc001e00, ",u,Zt,x(s,b)"},
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{ "cstdx", 0x2c000200, 0xfc001e00, ",u,Zt,x(b)"},
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{ "cldws", 0x24001000, 0xfc001e00, ",u,Z5(s,b),t"},
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{ "cldws", 0x24001000, 0xfc001e00, ",u,Z5(b),t"},
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{ "cldds", 0x2c001000, 0xfc001e00, ",u,Z5(s,b),t"},
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{ "cldds", 0x2c001000, 0xfc001e00, ",u,Z5(b),t"},
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{ "cstws", 0x24001200, 0xfc001e00, ",u,Zt,5(s,b)"},
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{ "cstws", 0x24001200, 0xfc001e00, ",u,Zt,5(b)"},
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{ "cstds", 0x2c001200, 0xfc001e00, ",u,Zt,5(s,b)"},
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{ "cstds", 0x2c001200, 0xfc001e00, ",u,Zt,5(b)"},
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{ "spop0", 0x10000000, 0xfc000600, ",f,ON", NORMAL},
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{ "spop1", 0x10000200, 0xfc000600, ",f,oNt", NORMAL},
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{ "spop2", 0x10000400, 0xfc000600, ",f,1Nb", NORMAL},
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{ "spop3", 0x10000600, 0xfc000600, ",f,0Nx,b", NORMAL},
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{ "copr", 0x30000000, 0xfc000000, ",u,2N", NORMAL},
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{ "cldwx", 0x24000000, 0xfc001e00, ",ucx(s,b),t"},
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{ "cldwx", 0x24000000, 0xfc001e00, ",ucx(b),t"},
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{ "clddx", 0x2c000000, 0xfc001e00, ",ucx(s,b),t"},
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{ "clddx", 0x2c000000, 0xfc001e00, ",ucx(b),t"},
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{ "cstwx", 0x24000200, 0xfc001e00, ",uct,x(s,b)"},
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{ "cstwx", 0x24000200, 0xfc001e00, ",uct,x(b)"},
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{ "cstdx", 0x2c000200, 0xfc001e00, ",uct,x(s,b)"},
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{ "cstdx", 0x2c000200, 0xfc001e00, ",uct,x(b)"},
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{ "cldws", 0x24001000, 0xfc001e00, ",uC5(s,b),t"},
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{ "cldws", 0x24001000, 0xfc001e00, ",uC5(b),t"},
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{ "cldds", 0x2c001000, 0xfc001e00, ",uC5(s,b),t"},
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{ "cldds", 0x2c001000, 0xfc001e00, ",uC5(b),t"},
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{ "cstws", 0x24001200, 0xfc001e00, ",uCt,5(s,b)"},
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{ "cstws", 0x24001200, 0xfc001e00, ",uCt,5(b)"},
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{ "cstds", 0x2c001200, 0xfc001e00, ",uCt,5(s,b)"},
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{ "cstds", 0x2c001200, 0xfc001e00, ",uCt,5(b)"},
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};
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#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
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