bfd signed overflow fixes
Aimed at quietening ubsan. include/ * opcode/mmix.h (PUSHGO_INSN_BYTE): Make unsigned. (GO_INSN_BYTE, SETL_INSN_BYTE, INCML_INSN_BYTE, INCMH_INSN_BYTE), (INCH_INSN_BYTE, SWYM_INSN_BYTE, JMP_INSN_BYTE): Likewise. bfd/ * elf32-rx.c (elf32_rx_relax_section): Avoid signed overflow. * libaout.h (N_SET_INFO, N_SET_FLAGS): Likewise. * netbsd.h (write_object_contents): Likewise. * elf32-arm.c (bfd_elf32_arm_vfp11_erratum_scan): Likewise. * libhppa.h (HPPA_R_CONSTANT): Don't signed extend with shifts. (stm32l4xx_create_replacing_stub_vldm): Don't truncate high bits with shifts. * elf32-nds32.h (R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG): Define using 1u shifted left. Ditto for other macros. * mmo.c (LOP): Make unsigned.
This commit is contained in:
Alan Modra
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09c7848734
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13c9c48599
@ -1,3 +1,16 @@
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2019-12-11 Alan Modra <amodra@gmail.com>
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* elf32-rx.c (elf32_rx_relax_section): Avoid signed overflow.
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* libaout.h (N_SET_INFO, N_SET_FLAGS): Likewise.
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* netbsd.h (write_object_contents): Likewise.
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* elf32-arm.c (bfd_elf32_arm_vfp11_erratum_scan): Likewise.
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* libhppa.h (HPPA_R_CONSTANT): Don't signed extend with shifts.
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(stm32l4xx_create_replacing_stub_vldm): Don't truncate high bits
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with shifts.
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* elf32-nds32.h (R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG): Define
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using 1u shifted left. Ditto for other macros.
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* mmo.c (LOP): Make unsigned.
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2019-12-11 Alan Modra <amodra@gmail.com>
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* libbfd.c (bfd_get_8): Return a bfd_vma.
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@ -8506,14 +8506,14 @@ bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
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{
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unsigned int next_i = i + 4;
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unsigned int insn = bfd_big_endian (abfd)
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? (contents[i] << 24)
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| (contents[i + 1] << 16)
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| (contents[i + 2] << 8)
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| contents[i + 3]
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: (contents[i + 3] << 24)
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| (contents[i + 2] << 16)
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| (contents[i + 1] << 8)
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| contents[i];
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? (((unsigned) contents[i] << 24)
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| (contents[i + 1] << 16)
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| (contents[i + 2] << 8)
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| contents[i + 3])
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: (((unsigned) contents[i + 3] << 24)
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| (contents[i + 2] << 16)
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| (contents[i + 1] << 8)
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| contents[i]);
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unsigned int writemask = 0;
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enum bfd_arm_vfp11_pipe vpipe;
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@ -19356,7 +19356,7 @@ stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
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const bfd_byte *const initial_insn_addr,
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bfd_byte *const base_stub_contents)
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{
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int num_words = ((unsigned int) initial_insn << 24) >> 24;
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int num_words = initial_insn & 0xff;
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bfd_byte *current_stub_contents = base_stub_contents;
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BFD_ASSERT (is_thumb2_vldm (initial_insn));
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@ -31,45 +31,45 @@ extern "C" {
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/* Relocation flags for R_NDS32_ERLAX_ENTRY. */
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/* Set if relax on this section is done or disabled. */
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#define R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG (1 << 31)
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#define R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG (1u << 31)
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/* Optimize for performance. */
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#define R_NDS32_RELAX_ENTRY_OPTIMIZE_FLAG (1 << 30)
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#define R_NDS32_RELAX_ENTRY_OPTIMIZE_FLAG (1u << 30)
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/* Optimize for size. Branch destination 4-byte adjustment
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may be disabled. */
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#define R_NDS32_RELAX_ENTRY_OPTIMIZE_FOR_SPACE_FLAG (1 << 29)
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#define R_NDS32_RELAX_ENTRY_OPTIMIZE_FOR_SPACE_FLAG (1u << 29)
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/* To distinguish the assembly code generated by compiler
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or written manually. */
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#define R_NDS32_RELAX_ENTRY_VERBATIM_FLAG (1 << 28)
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#define R_NDS32_RELAX_ENTRY_VERBATIM_FLAG (1u << 28)
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/* Two bits for ICT to comply with files without directive. */
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/* ICT small model. */
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#define R_NDS32_RELAX_ENTRY_ICT_SMALL (0x2 << 4)
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#define R_NDS32_RELAX_ENTRY_ICT_SMALL (0x2u << 4)
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/* ICT large model. */
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#define R_NDS32_RELAX_ENTRY_ICT_LARGE (0x3 << 4)
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#define R_NDS32_RELAX_ENTRY_ICT_LARGE (0x3u << 4)
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/* Mask for get ict bits. */
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#define R_NDS32_RELAX_ENTRY_ICT_MASK (0x3 << 4)
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#define R_NDS32_RELAX_ENTRY_ICT_MASK (0x3u << 4)
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/* Relocation flags for R_NDS32_INSN16. */
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/* Tag the nop16 can be removed. */
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#define R_NDS32_INSN16_CONVERT_FLAG (1 << 0)
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#define R_NDS32_INSN16_CONVERT_FLAG (1u << 0)
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/* Convert a gp-relative access (e.g., lwi.gp)
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to fp-as-gp access (lwi37.fp).
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This value is used by linker internally only.
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It's fine to change the vlaue. */
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#define R_NDS32_INSN16_FP7U2_FLAG (1 << 1)
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#define R_NDS32_INSN16_FP7U2_FLAG (1u << 1)
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/* Relocation flags for R_NDS32_RELAX_REGION_OMIT_FP_START/END. */
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/* OMIT_FP_FLAG marks the region for applying fp-as-gp
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optimization. */
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#define R_NDS32_RELAX_REGION_OMIT_FP_FLAG (1 << 0)
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#define R_NDS32_RELAX_REGION_OMIT_FP_FLAG (1u << 0)
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/* NOT_OMIT_FP_FLAG is set if this region is not worth
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for fp-as-gp. */
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#define R_NDS32_RELAX_REGION_NOT_OMIT_FP_FLAG (1 << 1)
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#define R_NDS32_RELAX_REGION_NOT_OMIT_FP_FLAG (1u << 1)
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/* A Innermost loop region. Some optimizations is suppressed
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in this region due to performance drop. */
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#define R_NDS32_RELAX_REGION_INNERMOST_LOOP_FLAG (1 << 4)
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#define R_NDS32_RELAX_REGION_INNERMOST_LOOP_FLAG (1u << 4)
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/* Tag range for LOADSTORE relocation. */
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enum
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@ -2932,9 +2932,9 @@ elf32_rx_relax_section (bfd * abfd,
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break;
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case 0:
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#if RX_OPCODE_BIG_ENDIAN
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imm_val = (ip[0] << 24) | (ip[1] << 16) | (ip[2] << 8) | ip[3];
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imm_val = ((unsigned) ip[0] << 24) | (ip[1] << 16) | (ip[2] << 8) | ip[3];
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#else
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imm_val = (ip[3] << 24) | (ip[2] << 16) | (ip[1] << 8) | ip[0];
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imm_val = ((unsigned) ip[3] << 24) | (ip[2] << 16) | (ip[1] << 8) | ip[0];
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#endif
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break;
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}
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@ -309,7 +309,7 @@ enum machine_type
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# define N_SET_INFO(execp, magic, type, flags) \
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((execp)->a_info = ((magic) & 0xffff) \
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| (((int)(type) & 0xff) << 16) \
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| (((flags) & 0xff) << 24))
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| (((flags) & 0xffu) << 24))
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#endif
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#ifndef N_SET_DYNAMIC
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@ -332,7 +332,7 @@ enum machine_type
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#ifndef N_SET_FLAGS
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# define N_SET_FLAGS(execp, flags) \
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((execp)->a_info = \
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((execp)->a_info & 0x00ffffff) | (((flags) & 0xff) << 24))
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((execp)->a_info & 0x00ffffff) | (((flags) & 0xffu) << 24))
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#endif
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typedef struct aout_symbol
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@ -148,7 +148,7 @@ enum hppa_reloc_expr_type_alt
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#define HPPA_R_ARG_RELOC(a) \
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(((a) >> 22) & 0x3ff)
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#define HPPA_R_CONSTANT(a) \
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((((bfd_signed_vma)(a)) << (BFD_ARCH_SIZE-22)) >> (BFD_ARCH_SIZE-22))
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((((bfd_signed_vma) (a) & 0x3fffff) ^ 0x200000) - 0x200000)
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#define HPPA_R_ADDEND(r, c) \
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(((r) << 22) + ((c) & 0x3fffff))
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@ -207,7 +207,7 @@ EXAMPLE
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#include "elf/mmix.h"
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#include "opcode/mmix.h"
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#define LOP 0x98
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#define LOP 0x98u
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#define LOP_QUOTE 0
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#define LOP_LOC 1
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#define LOP_SKIP 2
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@ -104,7 +104,7 @@ MY (write_object_contents) (bfd *abfd)
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/* XXX aren't there any macro to change byteorder of a word independent of
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the host's or target's endiannesses? */
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execp->a_info
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= (execp->a_info & 0xff) << 24 | (execp->a_info & 0xff00) << 8
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= (execp->a_info & 0xffu) << 24 | (execp->a_info & 0xff00) << 8
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| (execp->a_info & 0xff0000) >> 8 | (execp->a_info & 0xff000000) >> 24;
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#endif
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@ -1,3 +1,9 @@
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2019-12-11 Alan Modra <amodra@gmail.com>
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* opcode/mmix.h (PUSHGO_INSN_BYTE): Make unsigned.
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(GO_INSN_BYTE, SETL_INSN_BYTE, INCML_INSN_BYTE, INCMH_INSN_BYTE),
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(INCH_INSN_BYTE, SWYM_INSN_BYTE, JMP_INSN_BYTE): Likewise.
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2019-12-11 Alan Modra <amodra@gmail.com>
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* dis-asm.h (INSN_HAS_RELOC, DISASSEMBLE_DATA),
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@ -173,14 +173,14 @@ extern const struct mmix_spec_reg mmix_spec_regs[];
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#define COND_INV_BIT 0x8
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#define PRED_INV_BIT 0x10
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#define PUSHGO_INSN_BYTE 0xbe
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#define GO_INSN_BYTE 0x9e
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#define SETL_INSN_BYTE 0xe3
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#define INCML_INSN_BYTE 0xe6
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#define INCMH_INSN_BYTE 0xe5
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#define INCH_INSN_BYTE 0xe4
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#define SWYM_INSN_BYTE 0xfd
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#define JMP_INSN_BYTE 0xf0
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#define PUSHGO_INSN_BYTE 0xbeu
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#define GO_INSN_BYTE 0x9eu
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#define SETL_INSN_BYTE 0xe3u
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#define INCML_INSN_BYTE 0xe6u
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#define INCMH_INSN_BYTE 0xe5u
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#define INCH_INSN_BYTE 0xe4u
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#define SWYM_INSN_BYTE 0xfdu
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#define JMP_INSN_BYTE 0xf0u
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/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable)
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global registers. */
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