[PATCH]: aarch64: Refactor representation of system registers

Prior to this patch, the information describing the AArch64 system
registers was separate from the information describing which system
registers are available depending on the CPU feature set. Indeed, the
latter was implemented as a separate function from the main table with
the system register information.

This patch remedies this situation and puts the feature information into
the system register table itself.

This has several advantages:

 * Having all the information described in one place is easier to
   maintain.
 * The logic to check whether a system register is supported now becomes
   trivial (and much more efficient).

Since this patch ended up touching every line of the system register
table, I took the opportunity to make the formatting more consistent and
remove some redundant comments.

Note that there is still more refactoring that could be done along the
same lines here (e.g. with the TLB instructions) but this seemed like a
reasonable first pass.

Testing:

 * Regression tested an x64 -> aarch64-none-elf cross binutils.
 * Built aarch64-none-elf cross toolchain, checked newlib startup
   code still works.
 * Bootstrapped binutils on aarch64-linux-gnu, regression tested.
 * Built aarch64 kernel using new binutils with allyesconfig.

OK for master? If so, I'll need a maintainer to commit on my behalf
since I don't have write access.

Thanks,
Alex

---

include/ChangeLog:

2020-06-11  Alex Coplan  <alex.coplan@arm.com>

	* opcode/aarch64.h (aarch64_sys_reg): Add required features to struct
	describing system registers.

opcodes/ChangeLog:

2020-06-11  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-opc.c (SYSREG): New macro for describing system registers.
	(SR_CORE): Likewise.
	(SR_FEAT): Likewise.
	(SR_RNG): Likewise.
	(SR_V8_1): Likewise.
	(SR_V8_2): Likewise.
	(SR_V8_3): Likewise.
	(SR_V8_4): Likewise.
	(SR_PAN): Likewise.
	(SR_RAS): Likewise.
	(SR_SSBS): Likewise.
	(SR_SVE): Likewise.
	(SR_ID_PFR2): Likewise.
	(SR_PROFILE): Likewise.
	(SR_MEMTAG): Likewise.
	(SR_SCXTNUM): Likewise.
	(aarch64_sys_regs): Refactor to store feature information in the table.
	(aarch64_sys_reg_supported_p): Collapse logic for system registers
	that now describe their own features.
	(aarch64_pstatefield_supported_p): Likewise.

include/ChangeLog

@@ -1,3 +1,8 @@
+2020-06-11  Alex Coplan  <alex.coplan@arm.com>
+
+	* opcode/aarch64.h (aarch64_sys_reg): Add required features to struct
+	describing system registers.
+
 2020-06-11  Alan Modra  <amodra@gmail.com>
 
 	* elf/mips.h (Elf32_RegInfo): Use fixed width integer types.

include/opcode/aarch64.h

@@ -965,6 +965,10 @@ typedef struct
   const char *  name;
   aarch64_insn	value;
   uint32_t	flags;
+
+  /* A set of features, all of which are required for this system register to be
+     available.  */
+  aarch64_feature_set features;
 } aarch64_sys_reg;
 
 extern const aarch64_sys_reg aarch64_sys_regs [];

opcodes/ChangeLog

@@ -1,3 +1,26 @@
+2020-06-11  Alex Coplan  <alex.coplan@arm.com>
+
+	* aarch64-opc.c (SYSREG): New macro for describing system registers.
+	(SR_CORE): Likewise.
+	(SR_FEAT): Likewise.
+	(SR_RNG): Likewise.
+	(SR_V8_1): Likewise.
+	(SR_V8_2): Likewise.
+	(SR_V8_3): Likewise.
+	(SR_V8_4): Likewise.
+	(SR_PAN): Likewise.
+	(SR_RAS): Likewise.
+	(SR_SSBS): Likewise.
+	(SR_SVE): Likewise.
+	(SR_ID_PFR2): Likewise.
+	(SR_PROFILE): Likewise.
+	(SR_MEMTAG): Likewise.
+	(SR_SCXTNUM): Likewise.
+	(aarch64_sys_regs): Refactor to store feature information in the table.
+	(aarch64_sys_reg_supported_p): Collapse logic for system registers
+	that now describe their own features.
+	(aarch64_pstatefield_supported_p): Likewise.
+
 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (prefix_table): Fix a typo in comments.