* eCos->devo merge; tx3904 sanitize tags removed
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. (load_word): Call SIM_CORE_SIGNAL hook on error. (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before starting. For exception dispatching, pass PC instead of NULL_CIA. (decode_coproc): Use COP0_BADVADDR to store faulting address. * sim-main.h (COP0_BADVADDR): Define. (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * mips.igen (*): Replace memory-related SignalException* calls with references to SIM_CORE_SIGNAL hook. * dv-tx3904irc.c (tx3904irc_port_event): printf format warning fix. * sim-main.c (*): Minor warning cleanups.
This commit is contained in:
Frank Ch. Eigler
parent
a714374d5e
commit
14bbac6609
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@ -1,3 +1,21 @@
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1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
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* interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
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(load_word): Call SIM_CORE_SIGNAL hook on error.
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(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
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starting. For exception dispatching, pass PC instead of NULL_CIA.
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(decode_coproc): Use COP0_BADVADDR to store faulting address.
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* sim-main.h (COP0_BADVADDR): Define.
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(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
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(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
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(_sim_cpu): Add exc_* fields to store register value snapshots.
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* mips.igen (*): Replace memory-related SignalException* calls
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with references to SIM_CORE_SIGNAL hook.
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* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
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fix.
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* sim-main.c (*): Minor warning cleanups.
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1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
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* m16.igen (DADDIU5): Correct type-o.
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@ -88,13 +106,11 @@ end-sanitize-vr4xxx
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* mips/interp.c (DEBUG): Cleanups.
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start-sanitize-tx3904
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1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
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* dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
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(tx3904sio_tickle): fflush after a stdout character output.
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end-sanitize-tx3904
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1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
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* interp.c (sim_close): Uninstall modules.
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@ -219,14 +235,12 @@ Thu Nov 5 19:40:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
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(r59fp_store): Clarify "bad value" abort messages.
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end-sanitize-r5900
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start-sanitize-tx3904
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Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
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* dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
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interrupt level number to match changed SignalExceptionInterrupt
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macro.
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end-sanitize-tx3904
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start-sanitize-sky
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Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com>
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@ -293,7 +307,6 @@ Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
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macros to store output result during computation.
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end-sanitize-r5900
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start-sanitize-tx3904
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Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
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* dv-tx3904sio.c: Include sim-assert.h.
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@ -313,7 +326,6 @@ Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
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* dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
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frequent hw-trace messages.
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end-sanitize-tx3904
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start-sanitize-sky
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Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com>
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@ -445,22 +457,18 @@ start-sanitize-sky
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end-sanitize-sky
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* sim-main.h (interrupt_event): Add prototype.
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start-sanitize-tx3904
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* dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
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register_ptr, register_value.
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(deliver_tx3904tmr_tick): Fix types passed to printf fmt.
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end-sanitize-tx3904
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* sim-main.h (tracefh): Make extern.
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start-sanitize-tx3904
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Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
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* dv-tx3904tmr.c: Deschedule timer event after dispatching.
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Reduce unnecessarily high timer event frequency.
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* dv-tx3904cpu.c: Ditto for interrupt event.
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end-sanitize-tx3904
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start-sanitize-sky
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Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
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@ -475,12 +483,10 @@ Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
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* interp.c (decode_coproc): For TX39, add stub COP0 register #7,
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to allay warnings.
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(interrupt_event): Made non-static.
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start-sanitize-tx3904
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* dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
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interchange of configuration values for external vs. internal
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clock dividers.
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end-sanitize-tx3904
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Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
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@ -492,7 +498,6 @@ Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
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than halting sim.
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* sim-main.h: Moved magic constants to here.
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start-sanitize-tx3904
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Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
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* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
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@ -507,7 +512,6 @@ Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
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* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
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serial I/O and timer module at base address 0xFFFF0000.
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end-sanitize-tx3904
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Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
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* mips.igen (SWC1) : Correct the handling of ReverseEndian
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@ -519,7 +523,6 @@ Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
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parts.
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* configure: Update.
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start-sanitize-tx3904
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Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
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* dv-tx3904tmr.c: New file - implements tx3904 timer.
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@ -529,7 +532,6 @@ Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
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* interp.c (sim_open): Instantiate three timer instances.
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Fix address typo of tx3904irc instance.
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end-sanitize-tx3904
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start-sanitize-r5900
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Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
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@ -563,7 +565,6 @@ Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
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start-sanitize-tx3904
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Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
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@ -572,7 +573,6 @@ Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
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sim-main.h. Declare a struct hw_descriptor instead of struct
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hw_device_descriptor.
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end-sanitize-tx3904
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Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen (do_store_left, do_load_left): Compute nr of left and
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@ -580,7 +580,6 @@ Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
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lanes. Fix incorrect computation in do_store_left when loading
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bytes from second word.
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start-sanitize-tx3904
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Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
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@ -590,7 +589,6 @@ Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
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* interp.c (signal_exception): Ditto.
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end-sanitize-tx3904
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Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
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* gencode.c: Mark BEGEZALL as LIKELY.
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@ -626,13 +624,11 @@ Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
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exit.
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(decode_coproc): Implement RFE instruction for TX39.
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(mips.igen): Decode RFE instruction as such.
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start-sanitize-tx3904
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* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
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* interp.c: Define "jmr3904" and "jmr3904debug" board types and
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bbegin to implement memory map.
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* dv-tx3904cpu.c: New file.
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* dv-tx3904irc.c: New file.
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end-sanitize-tx3904
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Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
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@ -3968,9 +3968,18 @@ case "${target}" in
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;;
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# end-sanitize-cygnus
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# start-sanitize-vr4xxx
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mips64vr4xxx*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mipsIV,vr4100,vr4121 -G gen-multi-sim=mipsIV"
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;;
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mips64vr4xxx*-*-*) sim_gen=HACK
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sim_igen_filter="32,64,f"
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;;
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# mips64vr4xxx*-*-*) sim_gen=IGEN
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# sim_igen_machine="-M mipsIV,vr4100,vr4121 -G gen-multi-sim=mipsIV"
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# ;;
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# mips64vr4xxx*-*-*) sim_gen=M16
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# sim_igen_machine="-M mipsIV,vr4100 -G gen-multi-sim=mipsV"
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# sim_m16_machine="-M vr4100"
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# sim_igen_filter="32,64,f"
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# sim_m16_filter="16"
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# ;;
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# end-sanitize-vr4xxx
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mips64vr41*) sim_gen=M16
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sim_igen_machine="-M vr4100"
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@ -4007,14 +4016,12 @@ sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
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#
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hw_enabled=no
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case "${target}" in
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# start-sanitize-tx3904
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mips*tx39*)
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hw_enabled=yes
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hw_extra_devices="tx3904cpu tx3904irc tx3904tmr tx3904sio"
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mips_extra_objs="dv-sockser.o"
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SIM_SUBTARGET="$SIM_SUBTARGET -DTARGET_TX3904=1"
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;;
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# end-sanitize-tx3904
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# start-sanitize-sky
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mips64r59*-sky-*)
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mips_extra_objs='$(SIM_SKY_OBJS)'
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@ -4110,7 +4117,7 @@ esac
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# Uses ac_ vars as temps to allow command line to override cache and checks.
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# --without-x overrides everything else, but does not touch the cache.
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echo $ac_n "checking for X""... $ac_c" 1>&6
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echo "configure:4114: checking for X" >&5
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echo "configure:4123: checking for X" >&5
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# Check whether --with-x or --without-x was given.
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if test "${with_x+set}" = set; then
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@ -4172,12 +4179,12 @@ if test "$ac_x_includes" = NO; then
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# First, try using that file with no special directory specified.
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cat > conftest.$ac_ext <<EOF
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#line 4176 "configure"
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#line 4185 "configure"
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#include "confdefs.h"
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#include <$x_direct_test_include>
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:4181: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:4190: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
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if test -z "$ac_err"; then
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rm -rf conftest*
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@ -4246,14 +4253,14 @@ if test "$ac_x_libraries" = NO; then
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ac_save_LIBS="$LIBS"
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LIBS="-l$x_direct_test_library $LIBS"
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cat > conftest.$ac_ext <<EOF
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#line 4250 "configure"
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#line 4259 "configure"
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#include "confdefs.h"
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int main() {
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${x_direct_test_function}()
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; return 0; }
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EOF
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if { (eval echo configure:4257: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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if { (eval echo configure:4266: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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rm -rf conftest*
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LIBS="$ac_save_LIBS"
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# We can link X programs with no special library path.
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@ -4367,7 +4374,7 @@ then
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# Uses ac_ vars as temps to allow command line to override cache and checks.
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# --without-x overrides everything else, but does not touch the cache.
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echo $ac_n "checking for X""... $ac_c" 1>&6
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echo "configure:4371: checking for X" >&5
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echo "configure:4380: checking for X" >&5
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# Check whether --with-x or --without-x was given.
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if test "${with_x+set}" = set; then
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@ -4429,12 +4436,12 @@ if test "$ac_x_includes" = NO; then
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# First, try using that file with no special directory specified.
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cat > conftest.$ac_ext <<EOF
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#line 4433 "configure"
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#line 4442 "configure"
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#include "confdefs.h"
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#include <$x_direct_test_include>
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:4438: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:4447: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
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if test -z "$ac_err"; then
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rm -rf conftest*
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@ -4503,14 +4510,14 @@ if test "$ac_x_libraries" = NO; then
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ac_save_LIBS="$LIBS"
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LIBS="-l$x_direct_test_library $LIBS"
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cat > conftest.$ac_ext <<EOF
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#line 4507 "configure"
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#line 4516 "configure"
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#include "confdefs.h"
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int main() {
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${x_direct_test_function}()
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; return 0; }
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EOF
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if { (eval echo configure:4514: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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if { (eval echo configure:4523: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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rm -rf conftest*
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LIBS="$ac_save_LIBS"
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# We can link X programs with no special library path.
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@ -4600,12 +4607,12 @@ fi
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if test "$no_x" = ""; then
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if test "$x_includes" = ""; then
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cat > conftest.$ac_ext <<EOF
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#line 4604 "configure"
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#line 4613 "configure"
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#include "confdefs.h"
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#include <X11/XIntrinsic.h>
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:4609: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:4618: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
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if test -z "$ac_err"; then
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:
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|
@ -4625,15 +4632,15 @@ rm -f conftest*
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fi
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if test "$no_x" = "yes" -o "$not_really_there" = "yes"; then
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echo $ac_n "checking for X11 header files""... $ac_c" 1>&6
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echo "configure:4629: checking for X11 header files" >&5
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echo "configure:4638: checking for X11 header files" >&5
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XINCLUDES="# no special path needed"
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cat > conftest.$ac_ext <<EOF
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#line 4632 "configure"
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#line 4641 "configure"
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||||
#include "confdefs.h"
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||||
#include <X11/Intrinsic.h>
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||||
EOF
|
||||
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
|
||||
{ (eval echo configure:4637: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
||||
{ (eval echo configure:4646: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
||||
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
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||||
if test -z "$ac_err"; then
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:
|
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|
|
@ -4669,7 +4676,7 @@ rm -f conftest*
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|||
|
||||
if test "$no_x" = yes; then
|
||||
echo $ac_n "checking for X11 libraries""... $ac_c" 1>&6
|
||||
echo "configure:4673: checking for X11 libraries" >&5
|
||||
echo "configure:4682: checking for X11 libraries" >&5
|
||||
XLIBSW=nope
|
||||
dirs="/usr/unsupported/lib /usr/local/lib /usr/X386/lib /usr/X11R6/lib /usr/X11R5/lib /usr/lib/X11R5 /usr/lib/X11R4 /usr/lib/X11 /usr/openwin/lib /usr/X11/lib /usr/sww/X11/lib"
|
||||
for i in $dirs ; do
|
||||
|
|
@ -4689,7 +4696,7 @@ echo "configure:4673: checking for X11 libraries" >&5
|
|||
fi
|
||||
if test "$XLIBSW" = nope ; then
|
||||
echo $ac_n "checking for XCreateWindow in -lXwindow""... $ac_c" 1>&6
|
||||
echo "configure:4693: checking for XCreateWindow in -lXwindow" >&5
|
||||
echo "configure:4702: checking for XCreateWindow in -lXwindow" >&5
|
||||
ac_lib_var=`echo Xwindow'_'XCreateWindow | sed 'y%./+-%__p_%'`
|
||||
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
|
|
@ -4697,7 +4704,7 @@ else
|
|||
ac_save_LIBS="$LIBS"
|
||||
LIBS="-lXwindow $LIBS"
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 4701 "configure"
|
||||
#line 4710 "configure"
|
||||
#include "confdefs.h"
|
||||
/* Override any gcc2 internal prototype to avoid an error. */
|
||||
/* We use char because int might match the return type of a gcc2
|
||||
|
|
@ -4708,7 +4715,7 @@ int main() {
|
|||
XCreateWindow()
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:4712: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:4721: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_lib_$ac_lib_var=yes"
|
||||
else
|
||||
|
|
@ -4824,7 +4831,7 @@ fi
|
|||
#--------------------------------------------------------------------
|
||||
|
||||
echo $ac_n "checking for main in -lXbsd""... $ac_c" 1>&6
|
||||
echo "configure:4828: checking for main in -lXbsd" >&5
|
||||
echo "configure:4837: checking for main in -lXbsd" >&5
|
||||
ac_lib_var=`echo Xbsd'_'main | sed 'y%./+-%__p_%'`
|
||||
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
|
|
@ -4832,14 +4839,14 @@ else
|
|||
ac_save_LIBS="$LIBS"
|
||||
LIBS="-lXbsd $LIBS"
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 4836 "configure"
|
||||
#line 4845 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
int main() {
|
||||
main()
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:4843: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:4852: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_lib_$ac_lib_var=yes"
|
||||
else
|
||||
|
|
@ -4863,7 +4870,7 @@ fi
|
|||
# CYGNUS LOCAL: Store any socket library(ies) in the cache, and don't
|
||||
# mess up the cache values of the functions we check for.
|
||||
echo $ac_n "checking for socket libraries""... $ac_c" 1>&6
|
||||
echo "configure:4867: checking for socket libraries" >&5
|
||||
echo "configure:4876: checking for socket libraries" >&5
|
||||
if eval "test \"`echo '$''{'sim_cv_lib_sockets'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
else
|
||||
|
|
@ -4871,12 +4878,12 @@ else
|
|||
sim_checkBoth=0
|
||||
unset ac_cv_func_connect
|
||||
echo $ac_n "checking for connect""... $ac_c" 1>&6
|
||||
echo "configure:4875: checking for connect" >&5
|
||||
echo "configure:4884: checking for connect" >&5
|
||||
if eval "test \"`echo '$''{'ac_cv_func_connect'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
else
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 4880 "configure"
|
||||
#line 4889 "configure"
|
||||
#include "confdefs.h"
|
||||
/* System header to define __stub macros and hopefully few prototypes,
|
||||
which can conflict with char connect(); below. */
|
||||
|
|
@ -4899,7 +4906,7 @@ connect();
|
|||
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:4903: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:4912: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_func_connect=yes"
|
||||
else
|
||||
|
|
@ -4922,7 +4929,7 @@ fi
|
|||
if test "$sim_checkSocket" = 1; then
|
||||
unset ac_cv_func_connect
|
||||
echo $ac_n "checking for main in -lsocket""... $ac_c" 1>&6
|
||||
echo "configure:4926: checking for main in -lsocket" >&5
|
||||
echo "configure:4935: checking for main in -lsocket" >&5
|
||||
ac_lib_var=`echo socket'_'main | sed 'y%./+-%__p_%'`
|
||||
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
|
|
@ -4930,14 +4937,14 @@ else
|
|||
ac_save_LIBS="$LIBS"
|
||||
LIBS="-lsocket $LIBS"
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 4934 "configure"
|
||||
#line 4943 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
int main() {
|
||||
main()
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:4941: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:4950: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_lib_$ac_lib_var=yes"
|
||||
else
|
||||
|
|
@ -4964,12 +4971,12 @@ fi
|
|||
SOCKLIBSW="$SOCKLIBSW -lsocket -lnsl"
|
||||
unset ac_cv_func_accept
|
||||
echo $ac_n "checking for accept""... $ac_c" 1>&6
|
||||
echo "configure:4968: checking for accept" >&5
|
||||
echo "configure:4977: checking for accept" >&5
|
||||
if eval "test \"`echo '$''{'ac_cv_func_accept'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
else
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 4973 "configure"
|
||||
#line 4982 "configure"
|
||||
#include "confdefs.h"
|
||||
/* System header to define __stub macros and hopefully few prototypes,
|
||||
which can conflict with char accept(); below. */
|
||||
|
|
@ -4992,7 +4999,7 @@ accept();
|
|||
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:4996: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:5005: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_func_accept=yes"
|
||||
else
|
||||
|
|
@ -5019,12 +5026,12 @@ fi
|
|||
sim_oldLibs=$SOCKLIBSW
|
||||
SOCKLIBSW="$SOCKLIBSW $sim_cv_lib_sockets"
|
||||
echo $ac_n "checking for gethostbyname""... $ac_c" 1>&6
|
||||
echo "configure:5023: checking for gethostbyname" >&5
|
||||
echo "configure:5032: checking for gethostbyname" >&5
|
||||
if eval "test \"`echo '$''{'ac_cv_func_gethostbyname'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
else
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 5028 "configure"
|
||||
#line 5037 "configure"
|
||||
#include "confdefs.h"
|
||||
/* System header to define __stub macros and hopefully few prototypes,
|
||||
which can conflict with char gethostbyname(); below. */
|
||||
|
|
@ -5047,7 +5054,7 @@ gethostbyname();
|
|||
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:5051: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:5060: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_func_gethostbyname=yes"
|
||||
else
|
||||
|
|
@ -5065,7 +5072,7 @@ if eval "test \"`echo '$ac_cv_func_'gethostbyname`\" = yes"; then
|
|||
else
|
||||
echo "$ac_t""no" 1>&6
|
||||
echo $ac_n "checking for main in -lnsl""... $ac_c" 1>&6
|
||||
echo "configure:5069: checking for main in -lnsl" >&5
|
||||
echo "configure:5078: checking for main in -lnsl" >&5
|
||||
ac_lib_var=`echo nsl'_'main | sed 'y%./+-%__p_%'`
|
||||
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
|
|
@ -5073,14 +5080,14 @@ else
|
|||
ac_save_LIBS="$LIBS"
|
||||
LIBS="-lnsl $LIBS"
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 5077 "configure"
|
||||
#line 5086 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
int main() {
|
||||
main()
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:5084: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:5093: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_lib_$ac_lib_var=yes"
|
||||
else
|
||||
|
|
@ -5140,17 +5147,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h
|
|||
do
|
||||
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
|
||||
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
|
||||
echo "configure:5144: checking for $ac_hdr" >&5
|
||||
echo "configure:5153: checking for $ac_hdr" >&5
|
||||
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
else
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 5149 "configure"
|
||||
#line 5158 "configure"
|
||||
#include "confdefs.h"
|
||||
#include <$ac_hdr>
|
||||
EOF
|
||||
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
|
||||
{ (eval echo configure:5154: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
||||
{ (eval echo configure:5163: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
||||
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
|
||||
if test -z "$ac_err"; then
|
||||
rm -rf conftest*
|
||||
|
|
@ -5177,7 +5184,7 @@ fi
|
|||
done
|
||||
|
||||
echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
|
||||
echo "configure:5181: checking for fabs in -lm" >&5
|
||||
echo "configure:5190: checking for fabs in -lm" >&5
|
||||
ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
|
||||
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
|
|
@ -5185,7 +5192,7 @@ else
|
|||
ac_save_LIBS="$LIBS"
|
||||
LIBS="-lm $LIBS"
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 5189 "configure"
|
||||
#line 5198 "configure"
|
||||
#include "confdefs.h"
|
||||
/* Override any gcc2 internal prototype to avoid an error. */
|
||||
/* We use char because int might match the return type of a gcc2
|
||||
|
|
@ -5196,7 +5203,7 @@ int main() {
|
|||
fabs()
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:5200: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:5209: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_lib_$ac_lib_var=yes"
|
||||
else
|
||||
|
|
@ -5226,12 +5233,12 @@ fi
|
|||
for ac_func in aint anint sqrt
|
||||
do
|
||||
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
|
||||
echo "configure:5230: checking for $ac_func" >&5
|
||||
echo "configure:5239: checking for $ac_func" >&5
|
||||
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
|
||||
echo $ac_n "(cached) $ac_c" 1>&6
|
||||
else
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 5235 "configure"
|
||||
#line 5244 "configure"
|
||||
#include "confdefs.h"
|
||||
/* System header to define __stub macros and hopefully few prototypes,
|
||||
which can conflict with char $ac_func(); below. */
|
||||
|
|
@ -5254,7 +5261,7 @@ $ac_func();
|
|||
|
||||
; return 0; }
|
||||
EOF
|
||||
if { (eval echo configure:5258: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
if { (eval echo configure:5267: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
|
||||
rm -rf conftest*
|
||||
eval "ac_cv_func_$ac_func=yes"
|
||||
else
|
||||
|
|
|
|||
|
|
@ -217,14 +217,12 @@ AC_SUBST(sim_gen)
|
|||
#
|
||||
hw_enabled=no
|
||||
case "${target}" in
|
||||
# start-sanitize-tx3904
|
||||
mips*tx39*)
|
||||
hw_enabled=yes
|
||||
hw_extra_devices="tx3904cpu tx3904irc tx3904tmr tx3904sio"
|
||||
mips_extra_objs="dv-sockser.o"
|
||||
SIM_SUBTARGET="$SIM_SUBTARGET -DTARGET_TX3904=1"
|
||||
;;
|
||||
# end-sanitize-tx3904
|
||||
# start-sanitize-sky
|
||||
mips64r59*-sky-*)
|
||||
mips_extra_objs='$(SIM_SKY_OBJS)'
|
||||
|
|
|
|||
|
|
@ -39,9 +39,7 @@ code on the hardware.
|
|||
#include "sim-assert.h"
|
||||
#include "sim-hw.h"
|
||||
|
||||
#if WITH_IGEN
|
||||
#include "itable.h"
|
||||
#endif
|
||||
|
||||
/* start-sanitize-sky */
|
||||
#ifdef TARGET_SKY
|
||||
|
|
@ -89,13 +87,6 @@ char* pr_addr PARAMS ((SIM_ADDR addr));
|
|||
char* pr_uword64 PARAMS ((uword64 addr));
|
||||
|
||||
|
||||
/* Get the simulator engine description, without including the code: */
|
||||
#if !(WITH_IGEN)
|
||||
#define SIM_MANIFESTS
|
||||
#include "oengine.c"
|
||||
#undef SIM_MANIFESTS
|
||||
#endif
|
||||
|
||||
/* Within interp.c we refer to the sim_state and sim_cpu directly. */
|
||||
#define CPU cpu
|
||||
#define SD sd
|
||||
|
|
@ -174,9 +165,7 @@ FILE *tracefh = NULL;
|
|||
static void open_trace PARAMS((SIM_DESC sd));
|
||||
#endif /* TRACE */
|
||||
|
||||
#if WITH_IGEN
|
||||
static const char * get_insn_name (sim_cpu *, int);
|
||||
#endif
|
||||
|
||||
/* simulation target board. NULL=canonical */
|
||||
static char* board = NULL;
|
||||
|
|
@ -314,14 +303,12 @@ static const OPTION mips_options[] =
|
|||
{ {"board", required_argument, NULL, OPTION_BOARD},
|
||||
'\0', "none" /* rely on compile-time string concatenation for other options */
|
||||
|
||||
/* start-sanitize-tx3904 */
|
||||
#define BOARD_JMR3904 "jmr3904"
|
||||
"|" BOARD_JMR3904
|
||||
#define BOARD_JMR3904_PAL "jmr3904pal"
|
||||
"|" BOARD_JMR3904_PAL
|
||||
#define BOARD_JMR3904_DEBUG "jmr3904debug"
|
||||
"|" BOARD_JMR3904_DEBUG
|
||||
/* end-sanitize-tx3904 */
|
||||
|
||||
, "Customize simulation for a particular board.", mips_option_handler },
|
||||
|
||||
|
|
@ -377,11 +364,9 @@ sim_open (kind, cb, abfd, argv)
|
|||
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
|
||||
STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
|
||||
|
||||
#if WITH_IGEN
|
||||
/* Initialize the mechanism for doing insn profiling. */
|
||||
CPU_INSN_NAME (cpu) = get_insn_name;
|
||||
CPU_MAX_INSNS (cpu) = nr_itable_entries;
|
||||
#endif
|
||||
|
||||
STATE = 0;
|
||||
|
||||
|
|
@ -438,7 +423,6 @@ sim_open (kind, cb, abfd, argv)
|
|||
device_init(sd);
|
||||
}
|
||||
|
||||
/* start-sanitize-tx3904 */
|
||||
#if (WITH_HW)
|
||||
if (board != NULL
|
||||
&& (strcmp(board, BOARD_JMR3904) == 0 ||
|
||||
|
|
@ -446,6 +430,7 @@ sim_open (kind, cb, abfd, argv)
|
|||
strcmp(board, BOARD_JMR3904_DEBUG) == 0))
|
||||
{
|
||||
/* match VIRTUAL memory layout of JMR-TX3904 board */
|
||||
int i;
|
||||
|
||||
/* --- environment --- */
|
||||
|
||||
|
|
@ -466,10 +451,14 @@ sim_open (kind, cb, abfd, argv)
|
|||
0xA0000000);
|
||||
|
||||
/* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
|
||||
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
|
||||
0x88000000,
|
||||
32 * 1024 * 1024, /* 32 MB */
|
||||
0xA8000000);
|
||||
for (i=0; i<8; i++) /* 32 MB total */
|
||||
{
|
||||
unsigned size = 4 * 1024 * 1024; /* 4 MB */
|
||||
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
|
||||
0x88000000 + (i * size),
|
||||
size,
|
||||
0xA8000000 + (i * size));
|
||||
}
|
||||
|
||||
/* Dummy memory regions for unsimulated devices */
|
||||
|
||||
|
|
@ -544,7 +533,6 @@ sim_open (kind, cb, abfd, argv)
|
|||
device_init(sd);
|
||||
}
|
||||
#endif
|
||||
/* end-sanitize-tx3904 */
|
||||
|
||||
|
||||
/* check for/establish the a reference program image */
|
||||
|
|
@ -756,14 +744,12 @@ open_trace(sd)
|
|||
}
|
||||
#endif /* TRACE */
|
||||
|
||||
#if WITH_IGEN
|
||||
/* Return name of an insn, used by insn profiling. */
|
||||
static const char *
|
||||
get_insn_name (sim_cpu *cpu, int i)
|
||||
{
|
||||
return itable[i].name;
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
sim_close (sd, quitting)
|
||||
|
|
@ -780,9 +766,11 @@ sim_close (sd, quitting)
|
|||
#endif
|
||||
/* end-sanitize-sky */
|
||||
|
||||
|
||||
/* "quitting" is non-zero if we cannot hang on errors */
|
||||
|
||||
/* shut down modules */
|
||||
sim_module_uninstall (sd);
|
||||
|
||||
/* Ensure that any resources allocated through the callback
|
||||
mechanism are released: */
|
||||
sim_io_shutdown (sd);
|
||||
|
|
@ -1113,7 +1101,9 @@ sim_fetch_register (sd,rn,memory,length)
|
|||
/* NOTE: gdb (the client) stores registers in target byte order
|
||||
while the simulator uses host byte order */
|
||||
#ifdef DEBUG
|
||||
#if 0 /* FIXME: doesn't compile */
|
||||
sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
|
||||
#endif
|
||||
#endif /* DEBUG */
|
||||
|
||||
if (cpu->register_widths[rn] == 0)
|
||||
|
|
@ -1352,8 +1342,10 @@ sim_create_inferior (sd, abfd, argv,env)
|
|||
{
|
||||
|
||||
#ifdef DEBUG
|
||||
#if 0 /* FIXME: doesn't compile */
|
||||
printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
|
||||
pr_addr(PC));
|
||||
#endif
|
||||
#endif /* DEBUG */
|
||||
|
||||
ColdReset(sd);
|
||||
|
|
@ -1416,7 +1408,7 @@ fetch_str (SIM_DESC sd,
|
|||
}
|
||||
|
||||
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
|
||||
static void
|
||||
void
|
||||
sim_monitor (SIM_DESC sd,
|
||||
sim_cpu *cpu,
|
||||
address_word cia,
|
||||
|
|
@ -1692,7 +1684,9 @@ load_word (SIM_DESC sd,
|
|||
uword64 vaddr)
|
||||
{
|
||||
if ((vaddr & 3) != 0)
|
||||
SignalExceptionAddressLoad ();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
address_word paddr;
|
||||
|
|
@ -2199,6 +2193,11 @@ signal_exception (SIM_DESC sd,
|
|||
/* Ensure that any active atomic read/modify/write operation will fail: */
|
||||
LLBIT = 0;
|
||||
|
||||
/* Save registers before interrupt dispatching */
|
||||
#ifdef SIM_CPU_EXCEPTION_TRIGGER
|
||||
SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
|
||||
#endif
|
||||
|
||||
switch (exception) {
|
||||
|
||||
case DebugBreakPoint :
|
||||
|
|
@ -2343,23 +2342,25 @@ signal_exception (SIM_DESC sd,
|
|||
case InstructionFetch:
|
||||
case DataReference:
|
||||
/* The following is so that the simulator will continue from the
|
||||
exception address on breakpoint operations. */
|
||||
PC = EPC;
|
||||
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
|
||||
exception handler address. */
|
||||
sim_engine_halt (SD, CPU, NULL, PC,
|
||||
sim_stopped, SIM_SIGBUS);
|
||||
|
||||
case ReservedInstruction:
|
||||
case CoProcessorUnusable:
|
||||
PC = EPC;
|
||||
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
|
||||
sim_engine_halt (SD, CPU, NULL, PC,
|
||||
sim_stopped, SIM_SIGILL);
|
||||
|
||||
case IntegerOverflow:
|
||||
case FPE:
|
||||
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
|
||||
sim_engine_halt (SD, CPU, NULL, PC,
|
||||
sim_stopped, SIM_SIGFPE);
|
||||
|
||||
|
||||
case BreakPoint:
|
||||
sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
|
||||
break;
|
||||
|
||||
case SystemCall:
|
||||
case Trap:
|
||||
sim_engine_restart (SD, CPU, NULL, PC);
|
||||
|
|
@ -2367,12 +2368,12 @@ signal_exception (SIM_DESC sd,
|
|||
|
||||
case Watch:
|
||||
PC = EPC;
|
||||
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
|
||||
sim_engine_halt (SD, CPU, NULL, PC,
|
||||
sim_stopped, SIM_SIGTRAP);
|
||||
|
||||
default : /* Unknown internal exception */
|
||||
PC = EPC;
|
||||
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
|
||||
sim_engine_halt (SD, CPU, NULL, PC,
|
||||
sim_stopped, SIM_SIGABRT);
|
||||
|
||||
}
|
||||
|
|
@ -2473,10 +2474,8 @@ undefined_result(sd,cia)
|
|||
#define FPINF_SINGLE (0x7F800000)
|
||||
#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
|
||||
|
||||
#if 1 /* def DEBUG */
|
||||
#define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
|
||||
#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
|
||||
#endif /* DEBUG */
|
||||
#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : (((v) == fmt_uninterpreted_32) ? "<uninterpreted_32>" : (((v) == fmt_uninterpreted_64) ? "<uninterpreted_64>" : "<format error>"))))))))
|
||||
|
||||
uword64
|
||||
value_fpr (SIM_DESC sd,
|
||||
|
|
@ -2561,6 +2560,11 @@ value_fpr (SIM_DESC sd,
|
|||
case fmt_double:
|
||||
case fmt_long:
|
||||
if ((fpr & 1) == 0) { /* even registers only */
|
||||
#ifdef DEBUG
|
||||
printf("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
|
||||
fpr+1, pr_uword64( (uword64) FGR[fpr+1] ),
|
||||
fpr, pr_uword64( (uword64) FGR[fpr] ));
|
||||
#endif
|
||||
value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
|
||||
} else {
|
||||
SignalException(ReservedInstruction,0);
|
||||
|
|
@ -2577,7 +2581,7 @@ value_fpr (SIM_DESC sd,
|
|||
SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
|
||||
printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(value);
|
||||
|
|
@ -2594,7 +2598,7 @@ store_fpr (SIM_DESC sd,
|
|||
int err = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
|
||||
printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d,\n",fpr,DOFMT(fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
|
||||
#endif /* DEBUG */
|
||||
|
||||
if (SizeFGR() == 64) {
|
||||
|
|
@ -2663,7 +2667,7 @@ store_fpr (SIM_DESC sd,
|
|||
SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
|
||||
printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_uword64(FGR[fpr]),DOFMT(fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return;
|
||||
|
|
@ -3391,7 +3395,9 @@ convert (SIM_DESC sd,
|
|||
unsigned64 result64;
|
||||
|
||||
#ifdef DEBUG
|
||||
#if 0 /* FIXME: doesn't compile */
|
||||
printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
|
||||
#endif
|
||||
#endif /* DEBUG */
|
||||
|
||||
switch (rm)
|
||||
|
|
@ -3530,6 +3536,11 @@ cop_ld (SIM_DESC sd,
|
|||
int coproc_reg,
|
||||
uword64 memword)
|
||||
{
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
|
||||
#endif
|
||||
|
||||
switch (coproc_num) {
|
||||
case 1:
|
||||
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
|
||||
|
|
@ -3743,14 +3754,22 @@ decode_coproc (SIM_DESC sd,
|
|||
/* 12 = SR R4000 VR4100 VR4300 */
|
||||
#ifdef SUBTARGET_R3900
|
||||
case 3:
|
||||
/* ignore */
|
||||
break;
|
||||
/* 3 = Config R3900 */
|
||||
|
||||
case 7:
|
||||
/* 7 = Cache R3900 */
|
||||
case 15:
|
||||
/* 15 = PRID R3900 */
|
||||
|
||||
/* ignore */
|
||||
break;
|
||||
/* 3 = Cache R3900 */
|
||||
|
||||
case 8:
|
||||
/* 8 = BadVAddr R4000 VR4100 VR4300 */
|
||||
if (code == 0x00)
|
||||
GPR[rt] = COP0_BADVADDR;
|
||||
else
|
||||
COP0_BADVADDR = GPR[rt];
|
||||
break;
|
||||
|
||||
#endif /* SUBTARGET_R3900 */
|
||||
case 12:
|
||||
|
|
@ -3819,9 +3838,9 @@ decode_coproc (SIM_DESC sd,
|
|||
COP0_GPR[rd] = GPR[rt];
|
||||
#if 0
|
||||
if (code == 0x00)
|
||||
sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
|
||||
sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
|
||||
else
|
||||
sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
|
||||
sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -4084,215 +4103,6 @@ decode_coproc (SIM_DESC sd,
|
|||
}
|
||||
|
||||
|
||||
/*-- instruction simulation -------------------------------------------------*/
|
||||
|
||||
/* When the IGEN simulator is being built, the function below is be
|
||||
replaced by a generated version. However, WITH_IGEN == 2 indicates
|
||||
that the fubction below should be compiled but under a different
|
||||
name (to allow backward compatibility) */
|
||||
|
||||
#if (WITH_IGEN != 1)
|
||||
#if (WITH_IGEN > 1)
|
||||
void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
|
||||
void
|
||||
old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
|
||||
#else
|
||||
void
|
||||
sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
|
||||
#endif
|
||||
SIM_DESC sd;
|
||||
int next_cpu_nr; /* ignore */
|
||||
int nr_cpus; /* ignore */
|
||||
int siggnal; /* ignore */
|
||||
{
|
||||
sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
|
||||
#if !defined(FASTSIM)
|
||||
unsigned int pipeline_count = 1;
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
if (STATE_MEMORY (sd) == NULL) {
|
||||
printf("DBG: simulate() entered with no memory\n");
|
||||
exit(1);
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
#if 0 /* Disabled to check that everything works OK */
|
||||
/* The VR4300 seems to sign-extend the PC on its first
|
||||
access. However, this may just be because it is currently
|
||||
configured in 32bit mode. However... */
|
||||
PC = SIGNEXTEND(PC,32);
|
||||
#endif
|
||||
|
||||
/* main controlling loop */
|
||||
while (1) {
|
||||
/* vaddr is slowly being replaced with cia - current instruction
|
||||
address */
|
||||
address_word cia = (uword64)PC;
|
||||
address_word vaddr = cia;
|
||||
address_word paddr;
|
||||
int cca;
|
||||
unsigned int instruction; /* uword64? what's this used for? FIXME! */
|
||||
|
||||
#ifdef DEBUG
|
||||
{
|
||||
printf("DBG: state = 0x%08X :",state);
|
||||
if (state & simHALTEX) printf(" simHALTEX");
|
||||
if (state & simHALTIN) printf(" simHALTIN");
|
||||
printf("\n");
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
DSSTATE = (STATE & simDELAYSLOT);
|
||||
#ifdef DEBUG
|
||||
if (dsstate)
|
||||
sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* Fetch the next instruction from the simulator memory: */
|
||||
if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
|
||||
if ((vaddr & 1) == 0) {
|
||||
/* Copy the action of the LW instruction */
|
||||
unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
|
||||
unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
|
||||
uword64 value;
|
||||
unsigned int byte;
|
||||
paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
|
||||
LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
|
||||
byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
|
||||
instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
|
||||
} else {
|
||||
/* Copy the action of the LH instruction */
|
||||
unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
|
||||
unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
|
||||
uword64 value;
|
||||
unsigned int byte;
|
||||
paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
|
||||
| (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
|
||||
LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
|
||||
paddr & ~ (uword64) 1,
|
||||
vaddr, isINSTRUCTION, isREAL);
|
||||
byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
|
||||
instruction = ((value >> (8 * byte)) & 0xFFFF);
|
||||
}
|
||||
} else {
|
||||
fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
|
||||
exit(1);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* This is required by exception processing, to ensure that we can
|
||||
cope with exceptions in the delay slots of branches that may
|
||||
already have changed the PC. */
|
||||
if ((vaddr & 1) == 0)
|
||||
PC += 4; /* increment ready for the next fetch */
|
||||
else
|
||||
PC += 2;
|
||||
/* NOTE: If we perform a delay slot change to the PC, this
|
||||
increment is not requuired. However, it would make the
|
||||
simulator more complicated to try and avoid this small hit. */
|
||||
|
||||
/* Currently this code provides a simple model. For more
|
||||
complicated models we could perform exception status checks at
|
||||
this point, and set the simSTOP state as required. This could
|
||||
also include processing any hardware interrupts raised by any
|
||||
I/O model attached to the simulator context.
|
||||
|
||||
Support for "asynchronous" I/O events within the simulated world
|
||||
could be providing by managing a counter, and calling a I/O
|
||||
specific handler when a particular threshold is reached. On most
|
||||
architectures a decrement and check for zero operation is
|
||||
usually quicker than an increment and compare. However, the
|
||||
process of managing a known value decrement to zero, is higher
|
||||
than the cost of using an explicit value UINT_MAX into the
|
||||
future. Which system is used will depend on how complicated the
|
||||
I/O model is, and how much it is likely to affect the simulator
|
||||
bandwidth.
|
||||
|
||||
If events need to be scheduled further in the future than
|
||||
UINT_MAX event ticks, then the I/O model should just provide its
|
||||
own counter, triggered from the event system. */
|
||||
|
||||
/* MIPS pipeline ticks. To allow for future support where the
|
||||
pipeline hit of individual instructions is known, this control
|
||||
loop manages a "pipeline_count" variable. It is initialised to
|
||||
1 (one), and will only be changed by the simulator engine when
|
||||
executing an instruction. If the engine does not have access to
|
||||
pipeline cycle count information then all instructions will be
|
||||
treated as using a single cycle. NOTE: A standard system is not
|
||||
provided by the default simulator because different MIPS
|
||||
architectures have different cycle counts for the same
|
||||
instructions.
|
||||
|
||||
[NOTE: pipeline_count has been replaced the event queue] */
|
||||
|
||||
/* shuffle the floating point status pipeline state */
|
||||
ENGINE_ISSUE_PREFIX_HOOK();
|
||||
|
||||
/* NOTE: For multi-context simulation environments the "instruction"
|
||||
variable should be local to this routine. */
|
||||
|
||||
/* Shorthand accesses for engine. Note: If we wanted to use global
|
||||
variables (and a single-threaded simulator engine), then we can
|
||||
create the actual variables with these names. */
|
||||
|
||||
if (!(STATE & simSKIPNEXT)) {
|
||||
/* Include the simulator engine */
|
||||
#include "oengine.c"
|
||||
#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
|
||||
#error "Mismatch between run-time simulator code and simulation engine"
|
||||
#endif
|
||||
#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
|
||||
#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
|
||||
#endif
|
||||
#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
|
||||
#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
|
||||
#endif
|
||||
|
||||
/* For certain MIPS architectures, GPR[0] is hardwired to zero. We
|
||||
should check for it being changed. It is better doing it here,
|
||||
than within the simulator, since it will help keep the simulator
|
||||
small. */
|
||||
if (ZERO != 0) {
|
||||
#if defined(WARN_ZERO)
|
||||
sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
|
||||
#endif /* WARN_ZERO */
|
||||
ZERO = 0; /* reset back to zero before next instruction */
|
||||
}
|
||||
} else /* simSKIPNEXT check */
|
||||
STATE &= ~simSKIPNEXT;
|
||||
|
||||
/* If the delay slot was active before the instruction is
|
||||
executed, then update the PC to its new value: */
|
||||
if (DSSTATE) {
|
||||
#ifdef DEBUG
|
||||
printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
|
||||
#endif /* DEBUG */
|
||||
PC = DSPC;
|
||||
CANCELDELAYSLOT();
|
||||
}
|
||||
|
||||
#if !defined(FASTSIM)
|
||||
if (sim_events_tickn (sd, pipeline_count))
|
||||
{
|
||||
/* cpu->cia = cia; */
|
||||
sim_events_process (sd);
|
||||
}
|
||||
#else
|
||||
if (sim_events_tick (sd))
|
||||
{
|
||||
/* cpu->cia = cia; */
|
||||
sim_events_process (sd);
|
||||
}
|
||||
#endif /* FASTSIM */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* This code copied from gdb's utils.c. Would like to share this code,
|
||||
but don't know of a common place where both could get to it. */
|
||||
|
||||
|
|
@ -4347,6 +4157,101 @@ pr_uword64(addr)
|
|||
}
|
||||
|
||||
|
||||
void
|
||||
mips_core_signal (SIM_DESC sd,
|
||||
sim_cpu *cpu,
|
||||
sim_cia cia,
|
||||
unsigned map,
|
||||
int nr_bytes,
|
||||
address_word addr,
|
||||
transfer_type transfer,
|
||||
sim_core_signals sig)
|
||||
{
|
||||
const char *copy = (transfer == read_transfer ? "read" : "write");
|
||||
address_word ip = CIA_ADDR (cia);
|
||||
|
||||
switch (sig)
|
||||
{
|
||||
case sim_core_unmapped_signal:
|
||||
sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
|
||||
nr_bytes, copy,
|
||||
(unsigned long) addr, (unsigned long) ip);
|
||||
COP0_BADVADDR = addr;
|
||||
SignalExceptionDataReference();
|
||||
break;
|
||||
|
||||
case sim_core_unaligned_signal:
|
||||
sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
|
||||
nr_bytes, copy,
|
||||
(unsigned long) addr, (unsigned long) ip);
|
||||
COP0_BADVADDR = addr;
|
||||
if(transfer == read_transfer)
|
||||
SignalExceptionAddressLoad();
|
||||
else
|
||||
SignalExceptionAddressStore();
|
||||
break;
|
||||
|
||||
default:
|
||||
sim_engine_abort (sd, cpu, cia,
|
||||
"mips_core_signal - internal error - bad switch");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
|
||||
{
|
||||
ASSERT(cpu != NULL);
|
||||
|
||||
if(cpu->exc_suspended > 0)
|
||||
sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
|
||||
|
||||
PC = cia;
|
||||
memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
|
||||
cpu->exc_suspended = 0;
|
||||
}
|
||||
|
||||
void
|
||||
mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
|
||||
{
|
||||
ASSERT(cpu != NULL);
|
||||
|
||||
if(cpu->exc_suspended > 0)
|
||||
sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
|
||||
cpu->exc_suspended, exception);
|
||||
|
||||
memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
|
||||
memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
|
||||
cpu->exc_suspended = exception;
|
||||
}
|
||||
|
||||
void
|
||||
mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
|
||||
{
|
||||
ASSERT(cpu != NULL);
|
||||
|
||||
if(exception == 0 && cpu->exc_suspended > 0)
|
||||
{
|
||||
/* warn not for breakpoints */
|
||||
if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
|
||||
sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
|
||||
cpu->exc_suspended);
|
||||
}
|
||||
else if(exception != 0 && cpu->exc_suspended > 0)
|
||||
{
|
||||
if(exception != cpu->exc_suspended)
|
||||
sim_io_eprintf(sd, "Warning, resuming with unmatching exception signal (%d vs %d)\n",
|
||||
cpu->exc_suspended, exception);
|
||||
|
||||
memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
|
||||
}
|
||||
else if(exception != 0 && cpu->exc_suspended == 0)
|
||||
{
|
||||
sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
|
||||
}
|
||||
cpu->exc_suspended = 0;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/*> EOF interp.c <*/
|
||||
|
|
|
|||
|
|
@ -1288,7 +1288,7 @@
|
|||
|
||||
|
||||
|
||||
:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
|
||||
:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
|
||||
{
|
||||
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
||||
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
|
||||
|
|
@ -1356,28 +1356,32 @@
|
|||
|
||||
|
||||
|
||||
:function:64::void:do_ddiv:int rs, int rt
|
||||
:function:::void:do_ddiv:int rs, int rt
|
||||
{
|
||||
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
||||
{
|
||||
signed64 n = GPR[rs];
|
||||
signed64 d = GPR[rt];
|
||||
signed64 hi;
|
||||
signed64 lo;
|
||||
if (d == 0)
|
||||
{
|
||||
LO = SIGNED64 (0x8000000000000000);
|
||||
HI = 0;
|
||||
lo = SIGNED64 (0x8000000000000000);
|
||||
hi = 0;
|
||||
}
|
||||
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
|
||||
{
|
||||
LO = SIGNED64 (0x8000000000000000);
|
||||
HI = 0;
|
||||
lo = SIGNED64 (0x8000000000000000);
|
||||
hi = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LO = (n / d);
|
||||
HI = (n % d);
|
||||
lo = (n / d);
|
||||
hi = (n % d);
|
||||
}
|
||||
HI = hi;
|
||||
LO = lo;
|
||||
}
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
|
|
@ -1409,23 +1413,27 @@
|
|||
|
||||
|
||||
|
||||
:function:64::void:do_ddivu:int rs, int rt
|
||||
:function:::void:do_ddivu:int rs, int rt
|
||||
{
|
||||
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
||||
{
|
||||
unsigned64 n = GPR[rs];
|
||||
unsigned64 d = GPR[rt];
|
||||
unsigned64 hi;
|
||||
unsigned64 lo;
|
||||
if (d == 0)
|
||||
{
|
||||
LO = SIGNED64 (0x8000000000000000);
|
||||
HI = 0;
|
||||
lo = SIGNED64 (0x8000000000000000);
|
||||
hi = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LO = (n / d);
|
||||
HI = (n % d);
|
||||
lo = (n / d);
|
||||
hi = (n % d);
|
||||
}
|
||||
HI = hi;
|
||||
LO = lo;
|
||||
}
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
|
|
@ -1683,6 +1691,16 @@
|
|||
do_dmultu (SD_, RS, RT, RD);
|
||||
}
|
||||
|
||||
:function:::void:do_dsll:int rt, int rd, int shift
|
||||
{
|
||||
GPR[rd] = GPR[rt] << shift;
|
||||
}
|
||||
|
||||
:function:::void:do_dsllv:int rs, int rt, int rd
|
||||
{
|
||||
int s = MASKED64 (GPR[rs], 5, 0);
|
||||
GPR[rd] = GPR[rt] << s;
|
||||
}
|
||||
|
||||
|
||||
00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
|
||||
|
|
@ -1707,8 +1725,7 @@
|
|||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = GPR[RT] << s;
|
||||
do_dsll (SD_, RT, RD, SHIFT);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1738,8 +1755,6 @@
|
|||
GPR[RD] = GPR[RT] << s;
|
||||
}
|
||||
|
||||
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
|
||||
"dsllv r<RD>, r<RT>, r<RS>"
|
||||
*mipsIII:
|
||||
|
|
@ -1762,10 +1777,13 @@
|
|||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
int s = MASKED64 (GPR[RS], 5, 0);
|
||||
GPR[RD] = GPR[RT] << s;
|
||||
do_dsllv (SD_, RS, RT, RD);
|
||||
}
|
||||
|
||||
:function:::void:do_dsra:int rt, int rd, int shift
|
||||
{
|
||||
GPR[rd] = ((signed64) GPR[rt]) >> shift;
|
||||
}
|
||||
|
||||
|
||||
00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
|
||||
|
|
@ -1790,8 +1808,7 @@
|
|||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = ((signed64) GPR[RT]) >> s;
|
||||
do_dsra (SD_, RT, RD, SHIFT);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1855,6 +1872,11 @@
|
|||
do_dsrav (SD_, RS, RT, RD);
|
||||
}
|
||||
|
||||
:function:::void:do_dsrl:int rt, int rd, int shift
|
||||
{
|
||||
GPR[rd] = (unsigned64) GPR[rt] >> shift;
|
||||
}
|
||||
|
||||
|
||||
00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
|
||||
"dsrl r<RD>, r<RT>, <SHIFT>"
|
||||
|
|
@ -1878,8 +1900,7 @@
|
|||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = (unsigned64) GPR[RT] >> s;
|
||||
do_dsrl (SD_, RT, RD, SHIFT);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1910,6 +1931,14 @@
|
|||
}
|
||||
|
||||
|
||||
:function:::void:do_dsrlv:int rs, int rt, int rd
|
||||
{
|
||||
int s = MASKED64 (GPR[rs], 5, 0);
|
||||
GPR[rd] = (unsigned64) GPR[rt] >> s;
|
||||
}
|
||||
|
||||
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
|
||||
"dsrl32 r<RD>, r<RT>, r<RS>"
|
||||
*mipsIII:
|
||||
|
|
@ -1932,8 +1961,7 @@
|
|||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
int s = MASKED64 (GPR[RS], 5, 0);
|
||||
GPR[RD] = (unsigned64) GPR[RT] >> s;
|
||||
do_dsrlv (SD_, RS, RT, RD);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -2060,7 +2088,6 @@
|
|||
DELAY_SLOT (region | (INSTR_INDEX << 2));
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
|
||||
"jalr r<RS>":RD == 31
|
||||
"jalr r<RD>, r<RS>"
|
||||
|
|
@ -2129,7 +2156,9 @@
|
|||
|
||||
vaddr = base + offset;
|
||||
if ((vaddr & access) != 0)
|
||||
SignalExceptionAddressLoad ();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
|
||||
|
|
@ -2379,7 +2408,9 @@
|
|||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 3) != 0)
|
||||
SignalExceptionAddressLoad();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
||||
|
|
@ -2433,7 +2464,9 @@
|
|||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 7) != 0)
|
||||
SignalExceptionAddressLoad();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
||||
|
|
@ -3098,7 +3131,9 @@
|
|||
|
||||
vaddr = base + offset;
|
||||
if ((vaddr & access) != 0)
|
||||
SignalExceptionAddressStore ();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
byte = ((vaddr & mask) ^ bigendiancpu);
|
||||
|
|
@ -3165,7 +3200,9 @@
|
|||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 3) != 0)
|
||||
SignalExceptionAddressStore();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
||||
|
|
@ -3219,7 +3256,9 @@
|
|||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 7) != 0)
|
||||
SignalExceptionAddressStore();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
||||
|
|
@ -4544,13 +4583,6 @@
|
|||
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
|
||||
"bc1%s<TF>%s<ND> <OFFSET>"
|
||||
*mipsI,mipsII,mipsIII:
|
||||
*vr4100:
|
||||
// start-sanitize-vr4xxx
|
||||
*vr4121:
|
||||
// end-sanitize-vr4xxx
|
||||
// start-sanitize-vr4320
|
||||
*vr4320:
|
||||
// end-sanitize-vr4320
|
||||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
|
|
@ -4575,11 +4607,23 @@
|
|||
}
|
||||
}
|
||||
|
||||
// start-sanitize-vr4xxx
|
||||
// FIXME: vr4100,vr4320, and 4121 all should be in the
|
||||
// previous insn, but the renameing thing wasn't working
|
||||
// so I cheated -gavin
|
||||
// end-sanitize-vr4xxx
|
||||
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
|
||||
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
|
||||
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
|
||||
*mipsIV:
|
||||
*vr5000:
|
||||
#*vr4100:
|
||||
// start-sanitize-vr4320
|
||||
//*vr4320:
|
||||
// end-sanitize-vr4320
|
||||
// start-sanitize-vr4xxx
|
||||
*vr4121:
|
||||
// end-sanitize-vr4xxx
|
||||
// start-sanitize-cygnus
|
||||
*vr5400:
|
||||
// end-sanitize-cygnus
|
||||
|
|
@ -4751,7 +4795,7 @@
|
|||
|
||||
// CFC1
|
||||
// CTC1
|
||||
010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
|
||||
010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
|
||||
"c%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsI:
|
||||
*mipsII:
|
||||
|
|
@ -4775,7 +4819,7 @@
|
|||
/* else NOP */
|
||||
}
|
||||
}
|
||||
010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
|
||||
010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
|
||||
"c%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsIV:
|
||||
*vr4100:
|
||||
|
|
@ -5003,7 +5047,7 @@
|
|||
|
||||
// DMFC1
|
||||
// DMTC1
|
||||
010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
|
||||
010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
|
||||
"dm%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsIII:
|
||||
{
|
||||
|
|
@ -5027,7 +5071,7 @@
|
|||
PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
|
||||
}
|
||||
}
|
||||
010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
|
||||
010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
|
||||
"dm%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsIV:
|
||||
*vr4100:
|
||||
|
|
@ -5273,7 +5317,7 @@
|
|||
|
||||
// MFC1
|
||||
// MTC1
|
||||
010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
|
||||
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
|
||||
"m%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsI:
|
||||
*mipsII:
|
||||
|
|
@ -5289,7 +5333,7 @@
|
|||
else /*MFC1*/
|
||||
PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
|
||||
}
|
||||
010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
|
||||
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
|
||||
"m%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsIV:
|
||||
*vr4100:
|
||||
|
|
@ -5942,7 +5986,9 @@
|
|||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 3) != 0)
|
||||
SignalExceptionAddressStore();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
||||
|
|
@ -5983,7 +6029,9 @@
|
|||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 3) != 0)
|
||||
SignalExceptionAddressStore();
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
||||
|
|
|
|||
|
|
@ -32,6 +32,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
#define WITH_WATCHPOINTS 1
|
||||
#define WITH_MODULO_MEMORY 1
|
||||
|
||||
|
||||
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
|
||||
mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
|
||||
|
||||
#include "sim-basics.h"
|
||||
|
||||
typedef address_word sim_cia;
|
||||
|
|
@ -124,11 +128,13 @@ convert (SD, CPU, cia, rm, op, from, to)
|
|||
instruction: */
|
||||
#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
|
||||
|
||||
#if 1
|
||||
#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
|
||||
#ifdef TARGET_ENABLE_FR
|
||||
/* FIXME: this should be enabled for all targets, but needs testing first. */
|
||||
#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
|
||||
? ((SR & status_FR) ? 64 : 32) \
|
||||
: (WITH_TARGET_FLOATING_POINT_BITSIZE))
|
||||
#else
|
||||
/* They depend on the CPU being simulated */
|
||||
#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
|
||||
#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
|
||||
#endif
|
||||
|
||||
/* Standard FCRS bits: */
|
||||
|
|
@ -608,6 +614,7 @@ enum float_operation
|
|||
manifests to access the correct slot. */
|
||||
|
||||
unsigned_word registers[LAST_EMBED_REGNUM + 1];
|
||||
|
||||
int register_widths[NUM_REGS];
|
||||
#define REGISTERS ((CPU)->registers)
|
||||
|
||||
|
|
@ -640,6 +647,16 @@ enum float_operation
|
|||
#define EPC (REGISTERS[88])
|
||||
#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
|
||||
|
||||
/* All internal state modified by signal_exception() that may need to be
|
||||
rolled back for passing moment-of-exception image back to gdb. */
|
||||
unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
|
||||
unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
|
||||
int exc_suspended;
|
||||
|
||||
#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
|
||||
#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
|
||||
#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
|
||||
|
||||
unsigned_word c0_config_reg;
|
||||
#define C0_CONFIG ((CPU)->c0_config_reg)
|
||||
|
||||
|
|
@ -679,7 +696,9 @@ enum float_operation
|
|||
#define COP0_CONTEXT ((unsigned32)(COP0_GPR[4]))
|
||||
#define COP0_PAGEMASK ((unsigned32)(COP0_GPR[5]))
|
||||
#define COP0_WIRED ((unsigned32)(COP0_GPR[6]))
|
||||
/* end-sanitize-r5900 */
|
||||
#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
|
||||
/* start-sanitize-r5900 */
|
||||
#define COP0_COUNT ((unsigned32)(COP0_GPR[9]))
|
||||
#define COP0_ENTRYHI ((unsigned32)(COP0_GPR[10]))
|
||||
#define COP0_COMPARE ((unsigned32)(COP0_GPR[11]))
|
||||
|
|
@ -995,6 +1014,7 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio
|
|||
#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
|
||||
#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
|
||||
#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
|
||||
#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
|
||||
#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
|
||||
#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
|
||||
#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
|
||||
|
|
@ -1116,6 +1136,7 @@ void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_AD
|
|||
extern FILE *tracefh;
|
||||
|
||||
INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
|
||||
extern SIM_CORE_SIGNAL_FN mips_core_signal;
|
||||
|
||||
char* pr_addr PARAMS ((SIM_ADDR addr));
|
||||
char* pr_uword64 PARAMS ((uword64 addr));
|
||||
|
|
@ -1176,6 +1197,11 @@ enum txvu_cpu_context
|
|||
#endif /* TARGET_SKY */
|
||||
/* end-sanitize-sky */
|
||||
|
||||
void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
|
||||
void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
|
||||
void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
|
||||
|
||||
|
||||
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
|
||||
#include "sim-main.c"
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue