Add AVX512VBMI instructions
gas/ * config/tc-i386.c (cpu_arch): Add .avx512vbmi. * doc/c-i386.texi: Document it. opcodes/ * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb, vpmultishiftqb. * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2. * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS. (cpu_flags): Add CpuAVX512VBMI. * i386-opc.h (enum): Add CpuAVX512VBMI. (i386_cpu_flags): Add cpuavx512vbmi. * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b, vpermt2b. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/avx512vbmi-intel.d: New file. * gas/i386/avx512vbmi.d: Likewise. * gas/i386/avx512vbmi.s: Likewise. * gas/i386/avx512vbmi_vl-intel.d: Likewise. * gas/i386/avx512vbmi_vl.d: Likewise. * gas/i386/avx512vbmi_vl.s: Likewise. * gas/i386/x86-64-avx512vbmi-intel.d: Likewise. * gas/i386/x86-64-avx512vbmi.d: Likewise. * gas/i386/x86-64-avx512vbmi.s: Likewise. * gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise. * gas/i386/x86-64-avx512vbmi_vl.d: Likewise. * gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
This commit is contained in:
Ilya Tocar
H.J. Lu
parent
2cc1b5aad8
commit
14f195c9a0
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@ -1,3 +1,8 @@
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* config/tc-i386.c (cpu_arch): Add .avx512vbmi.
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* doc/c-i386.texi: Document it.
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* config/tc-i386.c (cpu_arch): Add .avx512ifma.
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@ -935,6 +935,8 @@ static const arch_entry cpu_arch[] =
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CPU_PCOMMIT_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
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CPU_AVX512IFMA_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
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CPU_AVX512VBMI_FLAGS, 0, 0 },
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};
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#ifdef I386COFF
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@ -164,6 +164,7 @@ accept various extension mnemonics. For example,
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@code{avx512bw},
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@code{avx512dq},
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@code{avx512ifma},
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@code{avx512vbmi},
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@code{noavx},
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@code{vmx},
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@code{vmfunc},
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@ -1106,7 +1107,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
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@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
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@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
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@item @samp{.clwb} @tab @samp{.pcommit}
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@item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
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@ -1,3 +1,19 @@
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* gas/i386/i386.exp: Run new tests.
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* gas/i386/avx512vbmi-intel.d: New file.
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* gas/i386/avx512vbmi.d: Likewise.
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* gas/i386/avx512vbmi.s: Likewise.
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* gas/i386/avx512vbmi_vl-intel.d: Likewise.
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* gas/i386/avx512vbmi_vl.d: Likewise.
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* gas/i386/avx512vbmi_vl.s: Likewise.
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* gas/i386/x86-64-avx512vbmi-intel.d: Likewise.
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* gas/i386/x86-64-avx512vbmi.d: Likewise.
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* gas/i386/x86-64-avx512vbmi.s: Likewise.
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* gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise.
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* gas/i386/x86-64-avx512vbmi_vl.d: Likewise.
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* gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* gas/i386/i386.exp: Run new tests.
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@ -0,0 +1,94 @@
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#as:
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#objdump: -dw -Mintel
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#name: i386 AVX512VBMI insns (Intel disassembly)
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#source: avx512vbmi.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d f4[ ]*vpermb zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8d f4[ ]*vpermb zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 8d f4[ ]*vpermb zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 31[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b4 f4 c0 1d fe ff[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 7f[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 00 20 00 00[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 80[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 c0 df ff ff[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 f4[ ]*vpermi2b zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 75 f4[ ]*vpermi2b zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 75 f4[ ]*vpermi2b zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 31[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b4 f4 c0 1d fe ff[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 7f[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 00 20 00 00[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 80[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 c0 df ff ff[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d f4[ ]*vpermt2b zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 7d f4[ ]*vpermt2b zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 7d f4[ ]*vpermt2b zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 31[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b4 f4 c0 1d fe ff[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 7f[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 00 20 00 00[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 80[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 c0 df ff ff[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 f4[ ]*vpmultishiftqb zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 83 f4[ ]*vpmultishiftqb zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 83 f4[ ]*vpmultishiftqb zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 31[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 30[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[eax\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 7f[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 00 20 00 00[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 80[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 c0 df ff ff[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 7f[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 00 04 00 00[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 80[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 f8 fb ff ff[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d f4[ ]*vpermb zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8d f4[ ]*vpermb zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 8d f4[ ]*vpermb zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 31[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b4 f4 c0 1d fe ff[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 7f[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 00 20 00 00[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 80[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 c0 df ff ff[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 f4[ ]*vpermi2b zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 75 f4[ ]*vpermi2b zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 75 f4[ ]*vpermi2b zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 31[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b4 f4 c0 1d fe ff[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 7f[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 00 20 00 00[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 80[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 c0 df ff ff[ ]*vpermi2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d f4[ ]*vpermt2b zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 7d f4[ ]*vpermt2b zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 7d f4[ ]*vpermt2b zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 31[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b4 f4 c0 1d fe ff[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 7f[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 00 20 00 00[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 80[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 c0 df ff ff[ ]*vpermt2b zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 f4[ ]*vpmultishiftqb zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 83 f4[ ]*vpmultishiftqb zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 83 f4[ ]*vpmultishiftqb zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 31[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 30[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[eax\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 7f[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 00 20 00 00[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 80[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 c0 df ff ff[ ]*vpmultishiftqb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 7f[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 00 04 00 00[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 80[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 f8 fb ff ff[ ]*vpmultishiftqb zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
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#pass
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@ -0,0 +1,94 @@
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#as:
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#objdump: -dw
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#name: i386 AVX512VBMI insns
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#source: avx512vbmi.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6\{%k7\}
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[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 31[ ]*vpermb \(%ecx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 7f[ ]*vpermb 0x1fc0\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 00 20 00 00[ ]*vpermb 0x2000\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 80[ ]*vpermb -0x2000\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 c0 df ff ff[ ]*vpermb -0x2040\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 f4[ ]*vpermi2b %zmm4,%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 75 f4[ ]*vpermi2b %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 75 f4[ ]*vpermi2b %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 31[ ]*vpermi2b \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b4 f4 c0 1d fe ff[ ]*vpermi2b -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 7f[ ]*vpermi2b 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 00 20 00 00[ ]*vpermi2b 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 80[ ]*vpermi2b -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 c0 df ff ff[ ]*vpermi2b -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d f4[ ]*vpermt2b %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 7d f4[ ]*vpermt2b %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 7d f4[ ]*vpermt2b %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 31[ ]*vpermt2b \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b4 f4 c0 1d fe ff[ ]*vpermt2b -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 7f[ ]*vpermt2b 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 00 20 00 00[ ]*vpermt2b 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 80[ ]*vpermt2b -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 c0 df ff ff[ ]*vpermt2b -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 f4[ ]*vpmultishiftqb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 83 f4[ ]*vpmultishiftqb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 83 f4[ ]*vpmultishiftqb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 31[ ]*vpmultishiftqb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 30[ ]*vpmultishiftqb \(%eax\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 7f[ ]*vpmultishiftqb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 00 20 00 00[ ]*vpmultishiftqb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 80[ ]*vpmultishiftqb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 c0 df ff ff[ ]*vpmultishiftqb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 80[ ]*vpmultishiftqb -0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 31[ ]*vpermb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 7f[ ]*vpermb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 00 20 00 00[ ]*vpermb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 80[ ]*vpermb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 c0 df ff ff[ ]*vpermb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 f4[ ]*vpermi2b %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 75 f4[ ]*vpermi2b %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 75 f4[ ]*vpermi2b %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 31[ ]*vpermi2b \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b4 f4 c0 1d fe ff[ ]*vpermi2b -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 7f[ ]*vpermi2b 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 00 20 00 00[ ]*vpermi2b 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 72 80[ ]*vpermi2b -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 b2 c0 df ff ff[ ]*vpermi2b -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d f4[ ]*vpermt2b %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 7d f4[ ]*vpermt2b %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf 7d f4[ ]*vpermt2b %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 31[ ]*vpermt2b \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b4 f4 c0 1d fe ff[ ]*vpermt2b -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 7f[ ]*vpermt2b 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 00 20 00 00[ ]*vpermt2b 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d 72 80[ ]*vpermt2b -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 7d b2 c0 df ff ff[ ]*vpermt2b -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 f4[ ]*vpmultishiftqb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 83 f4[ ]*vpmultishiftqb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 83 f4[ ]*vpmultishiftqb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 31[ ]*vpmultishiftqb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 30[ ]*vpmultishiftqb \(%eax\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 7f[ ]*vpmultishiftqb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 00 20 00 00[ ]*vpmultishiftqb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 72 80[ ]*vpmultishiftqb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 83 b2 c0 df ff ff[ ]*vpmultishiftqb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 72 80[ ]*vpmultishiftqb -0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
#pass
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
# Check 32bit AVX512VBMI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpermb %zmm4, %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI
|
||||
vpermb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512VBMI
|
||||
vpermb (%ecx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermb 8128(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpermb 8192(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermb -8192(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpermb -8256(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermi2b %zmm4, %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermi2b %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI
|
||||
vpermi2b %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512VBMI
|
||||
vpermi2b (%ecx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermi2b -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermi2b 8128(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpermi2b 8192(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermi2b -8192(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpermi2b -8256(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermt2b %zmm4, %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermt2b %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI
|
||||
vpermt2b %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512VBMI
|
||||
vpermt2b (%ecx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermt2b -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermt2b 8128(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpermt2b 8192(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpermt2b -8192(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpermt2b -8256(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb %zmm4, %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI
|
||||
vpmultishiftqb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512VBMI
|
||||
vpmultishiftqb (%ecx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb (%eax){1to8}, %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb 8128(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpmultishiftqb 8192(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb -8192(%edx), %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpmultishiftqb -8256(%edx), %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpmultishiftqb 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI
|
||||
vpmultishiftqb -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI Disp8
|
||||
vpmultishiftqb -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpermb zmm6, zmm5, zmm4 # AVX512VBMI
|
||||
vpermb zmm6{k7}, zmm5, zmm4 # AVX512VBMI
|
||||
vpermb zmm6{k7}{z}, zmm5, zmm4 # AVX512VBMI
|
||||
vpermb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512VBMI
|
||||
vpermb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512VBMI
|
||||
vpermb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512VBMI Disp8
|
||||
vpermb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512VBMI
|
||||
vpermb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512VBMI Disp8
|
||||
vpermb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512VBMI
|
||||
vpermi2b zmm6, zmm5, zmm4 # AVX512VBMI
|
||||
vpermi2b zmm6{k7}, zmm5, zmm4 # AVX512VBMI
|
||||
vpermi2b zmm6{k7}{z}, zmm5, zmm4 # AVX512VBMI
|
||||
vpermi2b zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512VBMI
|
||||
vpermi2b zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512VBMI
|
||||
vpermi2b zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512VBMI Disp8
|
||||
vpermi2b zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512VBMI
|
||||
vpermi2b zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512VBMI Disp8
|
||||
vpermi2b zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512VBMI
|
||||
vpermt2b zmm6, zmm5, zmm4 # AVX512VBMI
|
||||
vpermt2b zmm6{k7}, zmm5, zmm4 # AVX512VBMI
|
||||
vpermt2b zmm6{k7}{z}, zmm5, zmm4 # AVX512VBMI
|
||||
vpermt2b zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512VBMI
|
||||
vpermt2b zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512VBMI
|
||||
vpermt2b zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512VBMI Disp8
|
||||
vpermt2b zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512VBMI
|
||||
vpermt2b zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512VBMI Disp8
|
||||
vpermt2b zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, zmm4 # AVX512VBMI
|
||||
vpmultishiftqb zmm6{k7}, zmm5, zmm4 # AVX512VBMI
|
||||
vpmultishiftqb zmm6{k7}{z}, zmm5, zmm4 # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, [eax]{1to8} # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, [edx+1016]{1to8} # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm6, zmm5, [edx+1024]{1to8} # AVX512VBMI
|
||||
vpmultishiftqb zmm6, zmm5, [edx-1024]{1to8} # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm6, zmm5, [edx-1032]{1to8} # AVX512VBMI
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 AVX512VBMI/VL insns (Intel disassembly)
|
||||
#source: avx512vbmi_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d f4[ ]*vpermb xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 8d f4[ ]*vpermb xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 31[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b4 f4 c0 1d fe ff[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 7f[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 00 08 00 00[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 80[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 f0 f7 ff ff[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d f4[ ]*vpermb ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 8d f4[ ]*vpermb ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 31[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b4 f4 c0 1d fe ff[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 7f[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 00 10 00 00[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 80[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 e0 ef ff ff[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 f4[ ]*vpermi2b xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 75 f4[ ]*vpermi2b xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 31[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 7f[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 00 08 00 00[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 80[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 f0 f7 ff ff[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 f4[ ]*vpermi2b ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 75 f4[ ]*vpermi2b ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 31[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 7f[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 00 10 00 00[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 80[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 e0 ef ff ff[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d f4[ ]*vpermt2b xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 7d f4[ ]*vpermt2b xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 31[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 7f[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 00 08 00 00[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 80[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 f0 f7 ff ff[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d f4[ ]*vpermt2b ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 7d f4[ ]*vpermt2b ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 31[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 7f[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 00 10 00 00[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 80[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 e0 ef ff ff[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 f4[ ]*vpmultishiftqb xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f 83 f4[ ]*vpmultishiftqb xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 31[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 30[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 7f[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 00 08 00 00[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 80[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 7f[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 00 04 00 00[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 80[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 f4[ ]*vpmultishiftqb ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af 83 f4[ ]*vpmultishiftqb ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 31[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 30[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 7f[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 00 10 00 00[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 80[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 e0 ef ff ff[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 7f[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 00 04 00 00[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 80[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d f4[ ]*vpermb xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 8d f4[ ]*vpermb xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 31[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b4 f4 c0 1d fe ff[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 7f[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 00 08 00 00[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 80[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 f0 f7 ff ff[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d f4[ ]*vpermb ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 8d f4[ ]*vpermb ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 31[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b4 f4 c0 1d fe ff[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 7f[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 00 10 00 00[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 80[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 e0 ef ff ff[ ]*vpermb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 f4[ ]*vpermi2b xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 75 f4[ ]*vpermi2b xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 31[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 7f[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 00 08 00 00[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 80[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 f0 f7 ff ff[ ]*vpermi2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 f4[ ]*vpermi2b ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 75 f4[ ]*vpermi2b ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 31[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 7f[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 00 10 00 00[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 80[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 e0 ef ff ff[ ]*vpermi2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d f4[ ]*vpermt2b xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 7d f4[ ]*vpermt2b xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 31[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 7f[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 00 08 00 00[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 80[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 f0 f7 ff ff[ ]*vpermt2b xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d f4[ ]*vpermt2b ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 7d f4[ ]*vpermt2b ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 31[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 7f[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 00 10 00 00[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 80[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 e0 ef ff ff[ ]*vpermt2b ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 f4[ ]*vpmultishiftqb xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f 83 f4[ ]*vpmultishiftqb xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 31[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 30[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 7f[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 00 08 00 00[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 80[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 7f[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 00 04 00 00[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 80[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 f4[ ]*vpmultishiftqb ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af 83 f4[ ]*vpmultishiftqb ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 31[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 30[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 7f[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 00 10 00 00[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 80[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 e0 ef ff ff[ ]*vpmultishiftqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 7f[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 00 04 00 00[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 80[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512VBMI/VL insns
|
||||
#source: avx512vbmi_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d f4[ ]*vpermb %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 8d f4[ ]*vpermb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 31[ ]*vpermb \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 7f[ ]*vpermb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 00 08 00 00[ ]*vpermb 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 80[ ]*vpermb -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 f0 f7 ff ff[ ]*vpermb -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d f4[ ]*vpermb %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 8d f4[ ]*vpermb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 31[ ]*vpermb \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 7f[ ]*vpermb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 00 10 00 00[ ]*vpermb 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 80[ ]*vpermb -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 e0 ef ff ff[ ]*vpermb -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 f4[ ]*vpermi2b %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 75 f4[ ]*vpermi2b %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 31[ ]*vpermi2b \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 7f[ ]*vpermi2b 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 00 08 00 00[ ]*vpermi2b 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 80[ ]*vpermi2b -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 f0 f7 ff ff[ ]*vpermi2b -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 f4[ ]*vpermi2b %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 75 f4[ ]*vpermi2b %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 31[ ]*vpermi2b \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 7f[ ]*vpermi2b 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 00 10 00 00[ ]*vpermi2b 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 80[ ]*vpermi2b -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 e0 ef ff ff[ ]*vpermi2b -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d f4[ ]*vpermt2b %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 7d f4[ ]*vpermt2b %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 31[ ]*vpermt2b \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 7f[ ]*vpermt2b 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 00 08 00 00[ ]*vpermt2b 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 80[ ]*vpermt2b -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 f0 f7 ff ff[ ]*vpermt2b -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d f4[ ]*vpermt2b %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 7d f4[ ]*vpermt2b %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 31[ ]*vpermt2b \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 7f[ ]*vpermt2b 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 00 10 00 00[ ]*vpermt2b 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 80[ ]*vpermt2b -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 e0 ef ff ff[ ]*vpermt2b -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 f4[ ]*vpmultishiftqb %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f 83 f4[ ]*vpmultishiftqb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 31[ ]*vpmultishiftqb \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 30[ ]*vpmultishiftqb \(%eax\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 7f[ ]*vpmultishiftqb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 00 08 00 00[ ]*vpmultishiftqb 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 80[ ]*vpmultishiftqb -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 80[ ]*vpmultishiftqb -0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 f4[ ]*vpmultishiftqb %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af 83 f4[ ]*vpmultishiftqb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 31[ ]*vpmultishiftqb \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 30[ ]*vpmultishiftqb \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 7f[ ]*vpmultishiftqb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 00 10 00 00[ ]*vpmultishiftqb 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 80[ ]*vpmultishiftqb -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 e0 ef ff ff[ ]*vpmultishiftqb -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 80[ ]*vpmultishiftqb -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d f4[ ]*vpermb %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 8d f4[ ]*vpermb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 31[ ]*vpermb \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 7f[ ]*vpermb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 00 08 00 00[ ]*vpermb 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 80[ ]*vpermb -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 f0 f7 ff ff[ ]*vpermb -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d f4[ ]*vpermb %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 8d f4[ ]*vpermb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 31[ ]*vpermb \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 7f[ ]*vpermb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 00 10 00 00[ ]*vpermb 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d 72 80[ ]*vpermb -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d b2 e0 ef ff ff[ ]*vpermb -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 f4[ ]*vpermi2b %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 75 f4[ ]*vpermi2b %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 31[ ]*vpermi2b \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 7f[ ]*vpermi2b 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 00 08 00 00[ ]*vpermi2b 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 72 80[ ]*vpermi2b -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 75 b2 f0 f7 ff ff[ ]*vpermi2b -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 f4[ ]*vpermi2b %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 75 f4[ ]*vpermi2b %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 31[ ]*vpermi2b \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b4 f4 c0 1d fe ff[ ]*vpermi2b -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 7f[ ]*vpermi2b 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 00 10 00 00[ ]*vpermi2b 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 72 80[ ]*vpermi2b -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 75 b2 e0 ef ff ff[ ]*vpermi2b -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d f4[ ]*vpermt2b %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f 7d f4[ ]*vpermt2b %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 31[ ]*vpermt2b \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 7f[ ]*vpermt2b 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 00 08 00 00[ ]*vpermt2b 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d 72 80[ ]*vpermt2b -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 7d b2 f0 f7 ff ff[ ]*vpermt2b -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d f4[ ]*vpermt2b %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af 7d f4[ ]*vpermt2b %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 31[ ]*vpermt2b \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b4 f4 c0 1d fe ff[ ]*vpermt2b -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 7f[ ]*vpermt2b 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 00 10 00 00[ ]*vpermt2b 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d 72 80[ ]*vpermt2b -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 7d b2 e0 ef ff ff[ ]*vpermt2b -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 f4[ ]*vpmultishiftqb %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f 83 f4[ ]*vpmultishiftqb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 31[ ]*vpmultishiftqb \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 30[ ]*vpmultishiftqb \(%eax\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 7f[ ]*vpmultishiftqb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 00 08 00 00[ ]*vpmultishiftqb 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 72 80[ ]*vpmultishiftqb -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 72 80[ ]*vpmultishiftqb -0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 f4[ ]*vpmultishiftqb %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af 83 f4[ ]*vpmultishiftqb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 31[ ]*vpmultishiftqb \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b4 f4 c0 1d fe ff[ ]*vpmultishiftqb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 30[ ]*vpmultishiftqb \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 7f[ ]*vpmultishiftqb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 00 10 00 00[ ]*vpmultishiftqb 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 72 80[ ]*vpmultishiftqb -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f 83 b2 e0 ef ff ff[ ]*vpmultishiftqb -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 72 80[ ]*vpmultishiftqb -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
# Check 32bit AVX512{VBMI,VL} instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpermb %xmm4, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermb (%ecx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermb 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermb -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb %ymm4, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermb (%ecx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermb 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermb -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermb -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b %xmm4, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermi2b (%ecx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b %ymm4, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermi2b (%ecx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b %xmm4, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermt2b (%ecx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b %ymm4, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermt2b (%ecx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %xmm4, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%ecx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %ymm4, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%ecx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpermb xmm6{k7}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpermb xmm6{k7}{z}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpermb xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpermb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpermb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpermb xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{VBMI,VL}
|
||||
vpermb xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpermb xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{VBMI,VL}
|
||||
vpermb ymm6{k7}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpermb ymm6{k7}{z}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpermb ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpermb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpermb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpermb ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{VBMI,VL}
|
||||
vpermb ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpermb ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm6{k7}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpermi2b xmm6{k7}{z}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpermi2b xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm6{k7}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpermi2b ymm6{k7}{z}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpermi2b ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm6{k7}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpermt2b xmm6{k7}{z}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpermt2b xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm6{k7}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpermt2b ymm6{k7}{z}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpermt2b ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}{z}, xmm5, xmm4 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, [eax]{1to2} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}{z}, ymm5, ymm4 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, [eax]{1to4} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, [edx+1016]{1to4} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm6{k7}, ymm5, [edx+1024]{1to4} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm6{k7}, ymm5, [edx-1024]{1to4} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm6{k7}, ymm5, [edx-1032]{1to4} # AVX512{VBMI,VL}
|
||||
|
|
@ -338,6 +338,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "avx512ifma-intel"
|
||||
run_dump_test "avx512ifma_vl"
|
||||
run_dump_test "avx512ifma_vl-intel"
|
||||
run_dump_test "avx512vbmi"
|
||||
run_dump_test "avx512vbmi-intel"
|
||||
run_dump_test "avx512vbmi_vl"
|
||||
run_dump_test "avx512vbmi_vl-intel"
|
||||
run_dump_test "disassem"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
|
|
@ -697,6 +701,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-avx512ifma-intel"
|
||||
run_dump_test "x86-64-avx512ifma_vl"
|
||||
run_dump_test "x86-64-avx512ifma_vl-intel"
|
||||
run_dump_test "x86-64-avx512vbmi"
|
||||
run_dump_test "x86-64-avx512vbmi-intel"
|
||||
run_dump_test "x86-64-avx512vbmi_vl"
|
||||
run_dump_test "x86-64-avx512vbmi_vl-intel"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,94 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX512VBMI insns (Intel disassembly)
|
||||
#source: x86-64-avx512vbmi.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 8d f4[ ]*vpermb zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 8d f4[ ]*vpermb zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 8d f4[ ]*vpermb zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 31[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 8d b4 f0 23 01 00 00[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 7f[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 00 20 00 00[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 80[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 c0 df ff ff[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 75 f4[ ]*vpermi2b zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 75 f4[ ]*vpermi2b zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 75 f4[ ]*vpermi2b zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 31[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 75 b4 f0 23 01 00 00[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 7f[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 00 20 00 00[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 80[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 c0 df ff ff[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 7d f4[ ]*vpermt2b zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 7d f4[ ]*vpermt2b zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 7d f4[ ]*vpermt2b zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 31[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 7d b4 f0 23 01 00 00[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 7f[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 00 20 00 00[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 80[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 c0 df ff ff[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 83 f4[ ]*vpmultishiftqb zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 83 f4[ ]*vpmultishiftqb zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 83 f4[ ]*vpmultishiftqb zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 31[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 83 b4 f0 23 01 00 00[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 31[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 7f[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 00 20 00 00[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 80[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 c0 df ff ff[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 7f[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 00 04 00 00[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 80[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 f8 fb ff ff[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 8d f4[ ]*vpermb zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 8d f4[ ]*vpermb zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 8d f4[ ]*vpermb zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 31[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 8d b4 f0 34 12 00 00[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 7f[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 00 20 00 00[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 80[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 c0 df ff ff[ ]*vpermb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 75 f4[ ]*vpermi2b zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 75 f4[ ]*vpermi2b zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 75 f4[ ]*vpermi2b zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 31[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 75 b4 f0 34 12 00 00[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 7f[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 00 20 00 00[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 80[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 c0 df ff ff[ ]*vpermi2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 7d f4[ ]*vpermt2b zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 7d f4[ ]*vpermt2b zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 7d f4[ ]*vpermt2b zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 31[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 7d b4 f0 34 12 00 00[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 7f[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 00 20 00 00[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 80[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 c0 df ff ff[ ]*vpermt2b zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 83 f4[ ]*vpmultishiftqb zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 83 f4[ ]*vpmultishiftqb zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 83 f4[ ]*vpmultishiftqb zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 31[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 83 b4 f0 34 12 00 00[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 31[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 7f[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 00 20 00 00[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 80[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 c0 df ff ff[ ]*vpmultishiftqb zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 7f[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 00 04 00 00[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 80[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 f8 fb ff ff[ ]*vpmultishiftqb zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512VBMI insns
|
||||
#source: x86-64-avx512vbmi.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 8d f4[ ]*vpermb %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 8d f4[ ]*vpermb %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 8d f4[ ]*vpermb %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 31[ ]*vpermb \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 8d b4 f0 23 01 00 00[ ]*vpermb 0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 7f[ ]*vpermb 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 00 20 00 00[ ]*vpermb 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 80[ ]*vpermb -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 c0 df ff ff[ ]*vpermb -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 75 f4[ ]*vpermi2b %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 75 f4[ ]*vpermi2b %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 75 f4[ ]*vpermi2b %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 31[ ]*vpermi2b \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 75 b4 f0 23 01 00 00[ ]*vpermi2b 0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 7f[ ]*vpermi2b 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 00 20 00 00[ ]*vpermi2b 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 80[ ]*vpermi2b -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 c0 df ff ff[ ]*vpermi2b -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 7d f4[ ]*vpermt2b %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 7d f4[ ]*vpermt2b %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 7d f4[ ]*vpermt2b %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 31[ ]*vpermt2b \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 7d b4 f0 23 01 00 00[ ]*vpermt2b 0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 7f[ ]*vpermt2b 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 00 20 00 00[ ]*vpermt2b 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 80[ ]*vpermt2b -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 c0 df ff ff[ ]*vpermt2b -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 83 f4[ ]*vpmultishiftqb %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 83 f4[ ]*vpmultishiftqb %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 83 f4[ ]*vpmultishiftqb %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 31[ ]*vpmultishiftqb \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 83 b4 f0 23 01 00 00[ ]*vpmultishiftqb 0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 7f[ ]*vpmultishiftqb 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 00 20 00 00[ ]*vpmultishiftqb 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 80[ ]*vpmultishiftqb -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 c0 df ff ff[ ]*vpmultishiftqb -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 8d f4[ ]*vpermb %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 8d f4[ ]*vpermb %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 8d f4[ ]*vpermb %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 31[ ]*vpermb \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 8d b4 f0 34 12 00 00[ ]*vpermb 0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 7f[ ]*vpermb 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 00 20 00 00[ ]*vpermb 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d 72 80[ ]*vpermb -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 8d b2 c0 df ff ff[ ]*vpermb -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 75 f4[ ]*vpermi2b %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 75 f4[ ]*vpermi2b %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 75 f4[ ]*vpermi2b %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 31[ ]*vpermi2b \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 75 b4 f0 34 12 00 00[ ]*vpermi2b 0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 7f[ ]*vpermi2b 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 00 20 00 00[ ]*vpermi2b 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 72 80[ ]*vpermi2b -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 75 b2 c0 df ff ff[ ]*vpermi2b -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 7d f4[ ]*vpermt2b %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 7d f4[ ]*vpermt2b %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 7d f4[ ]*vpermt2b %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 31[ ]*vpermt2b \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 7d b4 f0 34 12 00 00[ ]*vpermt2b 0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 7f[ ]*vpermt2b 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 00 20 00 00[ ]*vpermt2b 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d 72 80[ ]*vpermt2b -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 7d b2 c0 df ff ff[ ]*vpermt2b -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 83 f4[ ]*vpmultishiftqb %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 83 f4[ ]*vpmultishiftqb %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 83 f4[ ]*vpmultishiftqb %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 31[ ]*vpmultishiftqb \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 83 b4 f0 34 12 00 00[ ]*vpmultishiftqb 0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 7f[ ]*vpmultishiftqb 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 00 20 00 00[ ]*vpmultishiftqb 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 72 80[ ]*vpmultishiftqb -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 83 b2 c0 df ff ff[ ]*vpmultishiftqb -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
#pass
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
# Check 64bit AVX512VBMI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpermb %zmm28, %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermb %zmm28, %zmm29, %zmm30{%k7} # AVX512VBMI
|
||||
vpermb %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512VBMI
|
||||
vpermb (%rcx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermb 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermb 8128(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpermb 8192(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermb -8192(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpermb -8256(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermi2b %zmm28, %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermi2b %zmm28, %zmm29, %zmm30{%k7} # AVX512VBMI
|
||||
vpermi2b %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512VBMI
|
||||
vpermi2b (%rcx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermi2b 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermi2b 8128(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpermi2b 8192(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermi2b -8192(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpermi2b -8256(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermt2b %zmm28, %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermt2b %zmm28, %zmm29, %zmm30{%k7} # AVX512VBMI
|
||||
vpermt2b %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512VBMI
|
||||
vpermt2b (%rcx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermt2b 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermt2b 8128(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpermt2b 8192(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpermt2b -8192(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpermt2b -8256(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb %zmm28, %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb %zmm28, %zmm29, %zmm30{%k7} # AVX512VBMI
|
||||
vpmultishiftqb %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512VBMI
|
||||
vpmultishiftqb (%rcx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb 8128(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpmultishiftqb 8192(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb -8192(%rdx), %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpmultishiftqb -8256(%rdx), %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpmultishiftqb 1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512VBMI
|
||||
vpmultishiftqb -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512VBMI Disp8
|
||||
vpmultishiftqb -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512VBMI
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpermb zmm30, zmm29, zmm28 # AVX512VBMI
|
||||
vpermb zmm30{k7}, zmm29, zmm28 # AVX512VBMI
|
||||
vpermb zmm30{k7}{z}, zmm29, zmm28 # AVX512VBMI
|
||||
vpermb zmm30, zmm29, ZMMWORD PTR [rcx] # AVX512VBMI
|
||||
vpermb zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512VBMI
|
||||
vpermb zmm30, zmm29, ZMMWORD PTR [rdx+8128] # AVX512VBMI Disp8
|
||||
vpermb zmm30, zmm29, ZMMWORD PTR [rdx+8192] # AVX512VBMI
|
||||
vpermb zmm30, zmm29, ZMMWORD PTR [rdx-8192] # AVX512VBMI Disp8
|
||||
vpermb zmm30, zmm29, ZMMWORD PTR [rdx-8256] # AVX512VBMI
|
||||
vpermi2b zmm30, zmm29, zmm28 # AVX512VBMI
|
||||
vpermi2b zmm30{k7}, zmm29, zmm28 # AVX512VBMI
|
||||
vpermi2b zmm30{k7}{z}, zmm29, zmm28 # AVX512VBMI
|
||||
vpermi2b zmm30, zmm29, ZMMWORD PTR [rcx] # AVX512VBMI
|
||||
vpermi2b zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512VBMI
|
||||
vpermi2b zmm30, zmm29, ZMMWORD PTR [rdx+8128] # AVX512VBMI Disp8
|
||||
vpermi2b zmm30, zmm29, ZMMWORD PTR [rdx+8192] # AVX512VBMI
|
||||
vpermi2b zmm30, zmm29, ZMMWORD PTR [rdx-8192] # AVX512VBMI Disp8
|
||||
vpermi2b zmm30, zmm29, ZMMWORD PTR [rdx-8256] # AVX512VBMI
|
||||
vpermt2b zmm30, zmm29, zmm28 # AVX512VBMI
|
||||
vpermt2b zmm30{k7}, zmm29, zmm28 # AVX512VBMI
|
||||
vpermt2b zmm30{k7}{z}, zmm29, zmm28 # AVX512VBMI
|
||||
vpermt2b zmm30, zmm29, ZMMWORD PTR [rcx] # AVX512VBMI
|
||||
vpermt2b zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512VBMI
|
||||
vpermt2b zmm30, zmm29, ZMMWORD PTR [rdx+8128] # AVX512VBMI Disp8
|
||||
vpermt2b zmm30, zmm29, ZMMWORD PTR [rdx+8192] # AVX512VBMI
|
||||
vpermt2b zmm30, zmm29, ZMMWORD PTR [rdx-8192] # AVX512VBMI Disp8
|
||||
vpermt2b zmm30, zmm29, ZMMWORD PTR [rdx-8256] # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, zmm28 # AVX512VBMI
|
||||
vpmultishiftqb zmm30{k7}, zmm29, zmm28 # AVX512VBMI
|
||||
vpmultishiftqb zmm30{k7}{z}, zmm29, zmm28 # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, ZMMWORD PTR [rcx] # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, [rcx]{1to8} # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, ZMMWORD PTR [rdx+8128] # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm30, zmm29, ZMMWORD PTR [rdx+8192] # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, ZMMWORD PTR [rdx-8192] # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm30, zmm29, ZMMWORD PTR [rdx-8256] # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, [rdx+1016]{1to8} # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm30, zmm29, [rdx+1024]{1to8} # AVX512VBMI
|
||||
vpmultishiftqb zmm30, zmm29, [rdx-1024]{1to8} # AVX512VBMI Disp8
|
||||
vpmultishiftqb zmm30, zmm29, [rdx-1032]{1to8} # AVX512VBMI
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX512VBMI/VL insns (Intel disassembly)
|
||||
#source: x86-64-avx512vbmi_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 8d f4[ ]*vpermb xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 8d f4[ ]*vpermb xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 8d f4[ ]*vpermb xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 31[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 8d b4 f0 23 01 00 00[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 7f[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 00 08 00 00[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 80[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 f0 f7 ff ff[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 8d f4[ ]*vpermb ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 8d f4[ ]*vpermb ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 8d f4[ ]*vpermb ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 31[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 8d b4 f0 23 01 00 00[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 7f[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 00 10 00 00[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 80[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 e0 ef ff ff[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 75 f4[ ]*vpermi2b xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 75 f4[ ]*vpermi2b xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 75 f4[ ]*vpermi2b xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 31[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 75 b4 f0 23 01 00 00[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 7f[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 00 08 00 00[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 80[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 f0 f7 ff ff[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 75 f4[ ]*vpermi2b ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 75 f4[ ]*vpermi2b ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 75 f4[ ]*vpermi2b ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 31[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 75 b4 f0 23 01 00 00[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 7f[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 00 10 00 00[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 80[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 e0 ef ff ff[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 7d f4[ ]*vpermt2b xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 7d f4[ ]*vpermt2b xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 7d f4[ ]*vpermt2b xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 31[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 7d b4 f0 23 01 00 00[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 7f[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 00 08 00 00[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 80[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 f0 f7 ff ff[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 7d f4[ ]*vpermt2b ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 7d f4[ ]*vpermt2b ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 7d f4[ ]*vpermt2b ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 31[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 7d b4 f0 23 01 00 00[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 7f[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 00 10 00 00[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 80[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 e0 ef ff ff[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 83 f4[ ]*vpmultishiftqb xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 83 f4[ ]*vpmultishiftqb xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 83 f4[ ]*vpmultishiftqb xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 31[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 83 b4 f0 23 01 00 00[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 31[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rcx\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 7f[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 00 08 00 00[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 80[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 7f[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 00 04 00 00[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 80[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 f8 fb ff ff[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 83 f4[ ]*vpmultishiftqb ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 83 f4[ ]*vpmultishiftqb ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 83 f4[ ]*vpmultishiftqb ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 31[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 83 b4 f0 23 01 00 00[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 7f[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 00 10 00 00[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 80[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 e0 ef ff ff[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 8d f4[ ]*vpermb xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 8d f4[ ]*vpermb xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 8d f4[ ]*vpermb xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 31[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 8d b4 f0 34 12 00 00[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 7f[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 00 08 00 00[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 80[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 f0 f7 ff ff[ ]*vpermb xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 8d f4[ ]*vpermb ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 8d f4[ ]*vpermb ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 8d f4[ ]*vpermb ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 31[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 8d b4 f0 34 12 00 00[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 7f[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 00 10 00 00[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 80[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 e0 ef ff ff[ ]*vpermb ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 75 f4[ ]*vpermi2b xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 75 f4[ ]*vpermi2b xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 75 f4[ ]*vpermi2b xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 31[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 75 b4 f0 34 12 00 00[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 7f[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 00 08 00 00[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 80[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 f0 f7 ff ff[ ]*vpermi2b xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 75 f4[ ]*vpermi2b ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 75 f4[ ]*vpermi2b ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 75 f4[ ]*vpermi2b ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 31[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 75 b4 f0 34 12 00 00[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 7f[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 00 10 00 00[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 80[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 e0 ef ff ff[ ]*vpermi2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 7d f4[ ]*vpermt2b xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 7d f4[ ]*vpermt2b xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 7d f4[ ]*vpermt2b xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 31[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 7d b4 f0 34 12 00 00[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 7f[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 00 08 00 00[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 80[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 f0 f7 ff ff[ ]*vpermt2b xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 7d f4[ ]*vpermt2b ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 7d f4[ ]*vpermt2b ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 7d f4[ ]*vpermt2b ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 31[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 7d b4 f0 34 12 00 00[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 7f[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 00 10 00 00[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 80[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 e0 ef ff ff[ ]*vpermt2b ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 83 f4[ ]*vpmultishiftqb xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 83 f4[ ]*vpmultishiftqb xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 83 f4[ ]*vpmultishiftqb xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 31[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 83 b4 f0 34 12 00 00[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 31[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rcx\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 7f[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 00 08 00 00[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 80[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 7f[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 00 04 00 00[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 80[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 f8 fb ff ff[ ]*vpmultishiftqb xmm30,xmm29,QWORD PTR \[rdx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 83 f4[ ]*vpmultishiftqb ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 83 f4[ ]*vpmultishiftqb ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 83 f4[ ]*vpmultishiftqb ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 31[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 83 b4 f0 34 12 00 00[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 7f[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 00 10 00 00[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 80[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 e0 ef ff ff[ ]*vpmultishiftqb ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512VBMI/VL insns
|
||||
#source: x86-64-avx512vbmi_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 8d f4[ ]*vpermb %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 8d f4[ ]*vpermb %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 8d f4[ ]*vpermb %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 31[ ]*vpermb \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 8d b4 f0 23 01 00 00[ ]*vpermb 0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 7f[ ]*vpermb 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 00 08 00 00[ ]*vpermb 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 80[ ]*vpermb -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 f0 f7 ff ff[ ]*vpermb -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 8d f4[ ]*vpermb %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 8d f4[ ]*vpermb %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 8d f4[ ]*vpermb %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 31[ ]*vpermb \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 8d b4 f0 23 01 00 00[ ]*vpermb 0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 7f[ ]*vpermb 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 00 10 00 00[ ]*vpermb 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 80[ ]*vpermb -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 e0 ef ff ff[ ]*vpermb -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 75 f4[ ]*vpermi2b %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 75 f4[ ]*vpermi2b %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 75 f4[ ]*vpermi2b %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 31[ ]*vpermi2b \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 75 b4 f0 23 01 00 00[ ]*vpermi2b 0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 7f[ ]*vpermi2b 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 00 08 00 00[ ]*vpermi2b 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 80[ ]*vpermi2b -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 f0 f7 ff ff[ ]*vpermi2b -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 75 f4[ ]*vpermi2b %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 75 f4[ ]*vpermi2b %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 75 f4[ ]*vpermi2b %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 31[ ]*vpermi2b \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 75 b4 f0 23 01 00 00[ ]*vpermi2b 0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 7f[ ]*vpermi2b 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 00 10 00 00[ ]*vpermi2b 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 80[ ]*vpermi2b -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 e0 ef ff ff[ ]*vpermi2b -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 7d f4[ ]*vpermt2b %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 7d f4[ ]*vpermt2b %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 7d f4[ ]*vpermt2b %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 31[ ]*vpermt2b \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 7d b4 f0 23 01 00 00[ ]*vpermt2b 0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 7f[ ]*vpermt2b 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 00 08 00 00[ ]*vpermt2b 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 80[ ]*vpermt2b -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 f0 f7 ff ff[ ]*vpermt2b -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 7d f4[ ]*vpermt2b %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 7d f4[ ]*vpermt2b %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 7d f4[ ]*vpermt2b %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 31[ ]*vpermt2b \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 7d b4 f0 23 01 00 00[ ]*vpermt2b 0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 7f[ ]*vpermt2b 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 00 10 00 00[ ]*vpermt2b 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 80[ ]*vpermt2b -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 e0 ef ff ff[ ]*vpermt2b -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 83 f4[ ]*vpmultishiftqb %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 83 f4[ ]*vpmultishiftqb %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 83 f4[ ]*vpmultishiftqb %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 31[ ]*vpmultishiftqb \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 83 b4 f0 23 01 00 00[ ]*vpmultishiftqb 0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 7f[ ]*vpmultishiftqb 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 00 08 00 00[ ]*vpmultishiftqb 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 80[ ]*vpmultishiftqb -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 83 f4[ ]*vpmultishiftqb %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 83 f4[ ]*vpmultishiftqb %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 83 f4[ ]*vpmultishiftqb %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 31[ ]*vpmultishiftqb \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 83 b4 f0 23 01 00 00[ ]*vpmultishiftqb 0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 7f[ ]*vpmultishiftqb 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 00 10 00 00[ ]*vpmultishiftqb 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 80[ ]*vpmultishiftqb -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 e0 ef ff ff[ ]*vpmultishiftqb -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 8d f4[ ]*vpermb %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 8d f4[ ]*vpermb %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 8d f4[ ]*vpermb %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 31[ ]*vpermb \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 8d b4 f0 34 12 00 00[ ]*vpermb 0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 7f[ ]*vpermb 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 00 08 00 00[ ]*vpermb 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d 72 80[ ]*vpermb -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 8d b2 f0 f7 ff ff[ ]*vpermb -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 8d f4[ ]*vpermb %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 8d f4[ ]*vpermb %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 8d f4[ ]*vpermb %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 31[ ]*vpermb \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 8d b4 f0 34 12 00 00[ ]*vpermb 0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 7f[ ]*vpermb 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 00 10 00 00[ ]*vpermb 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d 72 80[ ]*vpermb -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 8d b2 e0 ef ff ff[ ]*vpermb -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 75 f4[ ]*vpermi2b %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 75 f4[ ]*vpermi2b %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 75 f4[ ]*vpermi2b %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 31[ ]*vpermi2b \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 75 b4 f0 34 12 00 00[ ]*vpermi2b 0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 7f[ ]*vpermi2b 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 00 08 00 00[ ]*vpermi2b 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 72 80[ ]*vpermi2b -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 75 b2 f0 f7 ff ff[ ]*vpermi2b -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 75 f4[ ]*vpermi2b %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 75 f4[ ]*vpermi2b %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 75 f4[ ]*vpermi2b %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 31[ ]*vpermi2b \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 75 b4 f0 34 12 00 00[ ]*vpermi2b 0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 7f[ ]*vpermi2b 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 00 10 00 00[ ]*vpermi2b 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 72 80[ ]*vpermi2b -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 75 b2 e0 ef ff ff[ ]*vpermi2b -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 7d f4[ ]*vpermt2b %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 7d f4[ ]*vpermt2b %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 7d f4[ ]*vpermt2b %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 31[ ]*vpermt2b \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 7d b4 f0 34 12 00 00[ ]*vpermt2b 0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 7f[ ]*vpermt2b 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 00 08 00 00[ ]*vpermt2b 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d 72 80[ ]*vpermt2b -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 7d b2 f0 f7 ff ff[ ]*vpermt2b -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 7d f4[ ]*vpermt2b %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 7d f4[ ]*vpermt2b %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 7d f4[ ]*vpermt2b %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 31[ ]*vpermt2b \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 7d b4 f0 34 12 00 00[ ]*vpermt2b 0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 7f[ ]*vpermt2b 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 00 10 00 00[ ]*vpermt2b 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d 72 80[ ]*vpermt2b -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 7d b2 e0 ef ff ff[ ]*vpermt2b -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 83 f4[ ]*vpmultishiftqb %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 83 f4[ ]*vpmultishiftqb %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 83 f4[ ]*vpmultishiftqb %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 31[ ]*vpmultishiftqb \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 83 b4 f0 34 12 00 00[ ]*vpmultishiftqb 0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 7f[ ]*vpmultishiftqb 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 00 08 00 00[ ]*vpmultishiftqb 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 72 80[ ]*vpmultishiftqb -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 83 b2 f0 f7 ff ff[ ]*vpmultishiftqb -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 83 f4[ ]*vpmultishiftqb %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 83 f4[ ]*vpmultishiftqb %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 83 f4[ ]*vpmultishiftqb %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 31[ ]*vpmultishiftqb \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 83 b4 f0 34 12 00 00[ ]*vpmultishiftqb 0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 7f[ ]*vpmultishiftqb 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 00 10 00 00[ ]*vpmultishiftqb 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 72 80[ ]*vpmultishiftqb -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 83 b2 e0 ef ff ff[ ]*vpmultishiftqb -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
#pass
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
# Check 64bit AVX512{VBMI,VL} instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpermb %xmm28, %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermb %xmm28, %xmm29, %xmm30{%k7} # AVX512{VBMI,VL}
|
||||
vpermb %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermb (%rcx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermb 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermb 2032(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermb 2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermb -2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermb -2064(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermb %ymm28, %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermb %ymm28, %ymm29, %ymm30{%k7} # AVX512{VBMI,VL}
|
||||
vpermb %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermb (%rcx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermb 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermb 4064(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermb 4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermb -4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermb -4128(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermi2b %xmm28, %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermi2b %xmm28, %xmm29, %xmm30{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermi2b (%rcx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermi2b 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermi2b 2032(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b 2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermi2b -2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b -2064(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermi2b %ymm28, %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermi2b %ymm28, %ymm29, %ymm30{%k7} # AVX512{VBMI,VL}
|
||||
vpermi2b %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermi2b (%rcx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermi2b 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermi2b 4064(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b 4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermi2b -4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b -4128(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermt2b %xmm28, %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermt2b %xmm28, %xmm29, %xmm30{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermt2b (%rcx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermt2b 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermt2b 2032(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b 2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermt2b -2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b -2064(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpermt2b %ymm28, %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermt2b %ymm28, %ymm29, %ymm30{%k7} # AVX512{VBMI,VL}
|
||||
vpermt2b %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpermt2b (%rcx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermt2b 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermt2b 4064(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b 4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpermt2b -4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b -4128(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %xmm28, %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %xmm28, %xmm29, %xmm30{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%rcx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 2032(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -2048(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -2064(%rdx), %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %ymm28, %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %ymm28, %ymm29, %ymm30{%k7} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%rcx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 4064(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -4096(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -4128(%rdx), %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL}
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpermb xmm30, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermb xmm30{k7}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermb xmm30{k7}{z}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermb xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpermb xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpermb xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpermb xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{VBMI,VL}
|
||||
vpermb xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpermb xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{VBMI,VL}
|
||||
vpermb ymm30, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermb ymm30{k7}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermb ymm30{k7}{z}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermb ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpermb ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpermb ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpermb ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{VBMI,VL}
|
||||
vpermb ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpermb ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm30, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermi2b xmm30{k7}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermi2b xmm30{k7}{z}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermi2b xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{VBMI,VL}
|
||||
vpermi2b xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm30, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermi2b ymm30{k7}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermi2b ymm30{k7}{z}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermi2b ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{VBMI,VL}
|
||||
vpermi2b ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpermi2b ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm30, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermt2b xmm30{k7}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermt2b xmm30{k7}{z}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpermt2b xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{VBMI,VL}
|
||||
vpermt2b xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm30, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermt2b ymm30{k7}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermt2b ymm30{k7}{z}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpermt2b ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{VBMI,VL}
|
||||
vpermt2b ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpermt2b ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30{k7}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30{k7}{z}, xmm29, xmm28 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, [rcx]{1to2} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, [rdx+1016]{1to2} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm30, xmm29, [rdx+1024]{1to2} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb xmm30, xmm29, [rdx-1024]{1to2} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb xmm30, xmm29, [rdx-1032]{1to2} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30{k7}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30{k7}{z}, ymm29, ymm28 # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, [rcx]{1to4} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, [rdx+1016]{1to4} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm30, ymm29, [rdx+1024]{1to4} # AVX512{VBMI,VL}
|
||||
vpmultishiftqb ymm30, ymm29, [rdx-1024]{1to4} # AVX512{VBMI,VL} Disp8
|
||||
vpmultishiftqb ymm30, ymm29, [rdx-1032]{1to4} # AVX512{VBMI,VL}
|
||||
|
|
@ -1,3 +1,17 @@
|
|||
2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
|
||||
|
||||
* i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
|
||||
vpmultishiftqb.
|
||||
* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
|
||||
(cpu_flags): Add CpuAVX512VBMI.
|
||||
* i386-opc.h (enum): Add CpuAVX512VBMI.
|
||||
(i386_cpu_flags): Add cpuavx512vbmi.
|
||||
* i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
|
||||
vpermt2b.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
|
||||
|
||||
* i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
|
||||
|
|
|
|||
|
|
@ -442,7 +442,7 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F3883) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -2113,6 +2113,12 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ "vpermt2p%XW", { XM, Vex, EXx } },
|
||||
},
|
||||
/* PREFIX_EVEX_0F3883 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (EVEX_W_0F3883_P_2) },
|
||||
},
|
||||
/* PREFIX_EVEX_0F3888 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -3579,7 +3585,7 @@ static const struct dis386 evex_table[][256] = {
|
|||
},
|
||||
/* EVEX_W_0F3875_P_2 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vpermi2b", { XM, Vex, EXx } },
|
||||
{ "vpermi2w", { XM, Vex, EXx } },
|
||||
},
|
||||
/* EVEX_W_0F3878_P_2 */
|
||||
|
|
@ -3600,12 +3606,17 @@ static const struct dis386 evex_table[][256] = {
|
|||
},
|
||||
/* EVEX_W_0F387D_P_2 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vpermt2b", { XM, Vex, EXx } },
|
||||
{ "vpermt2w", { XM, Vex, EXx } },
|
||||
},
|
||||
/* EVEX_W_0F3883_P_2 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vpmultishiftqb", { XM, Vex, EXx } },
|
||||
},
|
||||
/* EVEX_W_0F388D_P_2 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vpermb", { XM, Vex, EXx } },
|
||||
{ "vpermw", { XM, Vex, EXx } },
|
||||
},
|
||||
/* EVEX_W_0F3891_P_2 */
|
||||
|
|
|
|||
|
|
@ -1478,6 +1478,7 @@ enum
|
|||
PREFIX_EVEX_0F387D,
|
||||
PREFIX_EVEX_0F387E,
|
||||
PREFIX_EVEX_0F387F,
|
||||
PREFIX_EVEX_0F3883,
|
||||
PREFIX_EVEX_0F3888,
|
||||
PREFIX_EVEX_0F3889,
|
||||
PREFIX_EVEX_0F388A,
|
||||
|
|
@ -2297,6 +2298,7 @@ enum
|
|||
EVEX_W_0F387A_P_2,
|
||||
EVEX_W_0F387B_P_2,
|
||||
EVEX_W_0F387D_P_2,
|
||||
EVEX_W_0F3883_P_2,
|
||||
EVEX_W_0F388D_P_2,
|
||||
EVEX_W_0F3891_P_2,
|
||||
EVEX_W_0F3893_P_2,
|
||||
|
|
|
|||
|
|
@ -243,6 +243,8 @@ static initializer cpu_flag_init[] =
|
|||
"CpuPCOMMIT" },
|
||||
{ "CPU_AVX512IFMA_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512IFMA" },
|
||||
{ "CPU_AVX512VBMI_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VBMI" },
|
||||
};
|
||||
|
||||
static initializer operand_type_init[] =
|
||||
|
|
@ -445,6 +447,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuNo64),
|
||||
BITFIELD (CpuMPX),
|
||||
BITFIELD (CpuAVX512IFMA),
|
||||
BITFIELD (CpuAVX512VBMI),
|
||||
#ifdef CpuUnused
|
||||
BITFIELD (CpuUnused),
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,708 +22,715 @@
|
|||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_PENTIUMPRO_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_NOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVEOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BMI_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_TBM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_CX16_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_FSGSBASE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_RDRND_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_F16C_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_BMI2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_LZCNT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_HLE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_RTM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_INVPCID_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_VMFUNC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512F_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512CD_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512ER_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512PF_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 1, 1 } }
|
||||
|
||||
#define CPU_K1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 1, 1 } }
|
||||
|
||||
#define CPU_ADX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_RDSEED_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_PRFCHW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SMAP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_MPX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SHA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSHOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVEC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_PREFETCHWT1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_SE1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512DQ_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512BW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512VL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_CLWB_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_PCOMMIT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512IFMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0 } }
|
||||
0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512VBMI_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -190,6 +190,8 @@ enum
|
|||
CpuPCOMMIT,
|
||||
/* Intel AVX-512 IFMA Instructions support required. */
|
||||
CpuAVX512IFMA,
|
||||
/* Intel AVX-512 VBMI Instructions support required. */
|
||||
CpuAVX512VBMI,
|
||||
/* 64bit support required */
|
||||
Cpu64,
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -292,6 +294,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuclwb:1;
|
||||
unsigned int cpupcommit:1;
|
||||
unsigned int cpuavx512ifma:1;
|
||||
unsigned int cpuavx512vbmi:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
#ifdef CpuUnused
|
||||
|
|
|
|||
|
|
@ -5905,3 +5905,20 @@ vpmadd52luq, 3, 0x66B4, None, 1, CpuAVX512IFMA|CpuAVX512VL, Modrm|EVex=2|Masking
|
|||
vpmadd52luq, 3, 0x66B4, None, 1, CpuAVX512IFMA|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
// AVX512IFMA instructions end
|
||||
|
||||
// AVX512VBMI instructions
|
||||
|
||||
vpmultishiftqb, 3, 0x6683, None, 1, CpuAVX512VBMI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmultishiftqb, 3, 0x6683, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmultishiftqb, 3, 0x6683, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpermb, 3, 0x668D, None, 1, CpuAVX512VBMI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpermb, 3, 0x668D, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpermb, 3, 0x668D, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpermi2b, 3, 0x6675, None, 1, CpuAVX512VBMI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpermi2b, 3, 0x6675, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpermi2b, 3, 0x6675, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpermt2b, 3, 0x667D, None, 1, CpuAVX512VBMI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpermt2b, 3, 0x667D, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpermt2b, 3, 0x667D, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
// AVX512VBMI instructions end
|
||||
|
|
|
|||
10902
opcodes/i386-tbl.h
10902
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue