* cp1.c (value_fpr): Don't inherit existing FPR_STATE for
uninterpreted formats. If fmt is one of the uninterpreted types don't update the FPR_STATE. Handle fmt_uninterpreted_32 like fmt_word, and fmt_uninterpreted_64 like fmt_long. (store_fpr): When writing an invalid odd register, set the matching even register to fmt_unknown, not the following register. * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to the the memory window at offset 0 set by --memory-size command line option. (sim_store_register): Handle storing 4 bytes to an 8 byte floating point register. (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte register. (sim_monitor): When returning the memory size to the MIPS application, use the value in STATE_MEM_SIZE, not an arbitrary hardcoded value. (cop_lw): Don' mess around with FPR_STATE, just pass fmt_uninterpreted_32 to StoreFPR. (cop_sw): Similarly. (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted. (cop_sd): Similarly. * mips.igen (not_word_value): Single version for mips32, mips64 and mips16.
This commit is contained in:
Thiemo Seufer
parent
b8e558488c
commit
14fb6c5a50
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@ -1,3 +1,31 @@
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2007-02-19 Thiemo Seufer <ths@mips.com>
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Nigel Stephens <nigel@mips.com>
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David Ung <davidu@mips.com>
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* cp1.c (value_fpr): Don't inherit existing FPR_STATE for
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uninterpreted formats. If fmt is one of the uninterpreted types
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don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
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fmt_word, and fmt_uninterpreted_64 like fmt_long.
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(store_fpr): When writing an invalid odd register, set the
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matching even register to fmt_unknown, not the following register.
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* interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
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the the memory window at offset 0 set by --memory-size command
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line option.
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(sim_store_register): Handle storing 4 bytes to an 8 byte floating
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point register.
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(sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
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register.
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(sim_monitor): When returning the memory size to the MIPS
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application, use the value in STATE_MEM_SIZE, not an arbitrary
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hardcoded value.
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(cop_lw): Don' mess around with FPR_STATE, just pass
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fmt_uninterpreted_32 to StoreFPR.
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(cop_sw): Similarly.
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(cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
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(cop_sd): Similarly.
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* mips.igen (not_word_value): Single version for mips32, mips64
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and mips16.
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2007-02-19 Thiemo Seufer <ths@mips.com>
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Nigel Stephens <nigel@mips.com>
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@ -111,10 +111,10 @@ value_fpr (sim_cpu *cpu,
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int err = 0;
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/* Treat unused register values, as fixed-point 64bit values. */
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if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
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if (fmt == fmt_unknown)
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{
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#if 1
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/* If request to read data as "uninterpreted", then use the current
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/* If request to read data as "unknown", then use the current
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encoding: */
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fmt = FPR_STATE[fpr];
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#else
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@ -123,20 +123,23 @@ value_fpr (sim_cpu *cpu,
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}
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/* For values not yet accessed, set to the desired format. */
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if (FPR_STATE[fpr] == fmt_uninterpreted)
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if (fmt < fmt_uninterpreted)
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{
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FPR_STATE[fpr] = fmt;
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if (FPR_STATE[fpr] == fmt_uninterpreted)
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{
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FPR_STATE[fpr] = fmt;
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#ifdef DEBUG
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printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr,
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fpu_format_name (fmt));
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printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr,
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fpu_format_name (fmt));
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#endif /* DEBUG */
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}
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if (fmt != FPR_STATE[fpr])
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{
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sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
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fpr, fpu_format_name (FPR_STATE[fpr]),
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fpu_format_name (fmt), pr_addr (cia));
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FPR_STATE[fpr] = fmt_unknown;
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}
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else if (fmt != FPR_STATE[fpr])
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{
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sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
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fpr, fpu_format_name (FPR_STATE[fpr]),
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fpu_format_name (fmt), pr_addr (cia));
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FPR_STATE[fpr] = fmt_unknown;
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}
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}
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if (FPR_STATE[fpr] == fmt_unknown)
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@ -156,11 +159,13 @@ value_fpr (sim_cpu *cpu,
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{
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switch (fmt)
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{
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case fmt_uninterpreted_32:
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case fmt_single:
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case fmt_word:
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value = (FGR[fpr] & 0xFFFFFFFF);
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break;
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case fmt_uninterpreted_64:
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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@ -177,11 +182,13 @@ value_fpr (sim_cpu *cpu,
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{
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switch (fmt)
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{
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case fmt_uninterpreted_32:
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case fmt_single:
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case fmt_word:
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value = (FGR[fpr] & 0xFFFFFFFF);
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break;
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case fmt_uninterpreted_64:
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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@ -299,7 +306,7 @@ store_fpr (sim_cpu *cpu,
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else
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{
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FPR_STATE[fpr] = fmt_unknown;
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FPR_STATE[fpr + 1] = fmt_unknown;
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FPR_STATE[fpr ^ 1] = fmt_unknown;
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SignalException (ReservedInstruction, 0);
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}
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break;
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@ -131,6 +131,9 @@ static void ColdReset PARAMS((SIM_DESC sd));
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/* Note that the monitor code essentially assumes this layout of memory.
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If you change these, change the monitor code, too. */
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/* FIXME Currently addresses are truncated to 32-bits, see
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mips/sim-main.c:address_translation(). If that changes, then these
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values will need to be extended, and tested for more carefully. */
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#define K0BASE (0x80000000)
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#define K0SIZE (0x20000000)
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#define K1BASE (0xA0000000)
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@ -365,17 +368,67 @@ sim_open (kind, cb, abfd, argv)
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if (board == NULL)
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{
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/* Allocate core managed memory */
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sim_memopt *entry, *match = NULL;
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address_word mem_size = 0;
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int mapped = 0;
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/* For compatibility with the old code - under this (at level one)
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are the kernel spaces K0 & K1. Both of these map to a single
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smaller sub region */
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sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
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sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
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K1BASE, K0SIZE,
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MEM_SIZE, /* actual size */
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K0BASE);
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/* Look for largest memory region defined on command-line at
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phys address 0. */
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#ifdef SIM_HAVE_FLATMEM
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mem_size = STATE_MEM_SIZE (sd);
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#endif
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for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
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{
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/* If we find an entry at address 0, then we will end up
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allocating a new buffer in the "memory alias" command
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below. The region at address 0 will be deleted. */
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address_word size = (entry->modulo != 0
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? entry->modulo : entry->nr_bytes);
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if (entry->addr == 0
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&& (!match || entry->level < match->level))
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match = entry;
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else if (entry->addr == K0BASE || entry->addr == K1BASE)
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mapped = 1;
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else
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{
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sim_memopt *alias;
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for (alias = entry->alias; alias != NULL; alias = alias->next)
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{
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if (alias->addr == 0
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&& (!match || entry->level < match->level))
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match = entry;
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else if (alias->addr == K0BASE || alias->addr == K1BASE)
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mapped = 1;
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}
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}
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}
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if (!mapped)
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{
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if (match)
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{
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/* Get existing memory region size. */
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mem_size = (match->modulo != 0
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? match->modulo : match->nr_bytes);
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/* Delete old region. */
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sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
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match->space, match->addr, match->level);
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}
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else if (mem_size == 0)
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mem_size = MEM_SIZE;
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/* Limit to KSEG1 size (512MB) */
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if (mem_size > K1SIZE)
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mem_size = K1SIZE;
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/* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
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sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
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K1BASE, K1SIZE, (long)mem_size, K0BASE);
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}
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device_init(sd);
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}
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else if (board != NULL
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@ -868,8 +921,16 @@ sim_store_register (sd,rn,memory,length)
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}
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else
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{
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cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
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return 8;
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if (length == 8)
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{
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cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
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return 8;
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}
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else
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{
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cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
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return 4;
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}
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}
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}
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@ -889,8 +950,16 @@ sim_store_register (sd,rn,memory,length)
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}
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else
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{
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cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
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return 8;
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if (length == 8)
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{
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cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
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return 8;
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}
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else
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{
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cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
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return 4;
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}
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}
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return 0;
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@ -939,8 +1008,16 @@ sim_fetch_register (sd,rn,memory,length)
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}
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else
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{
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*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
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return 8;
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if (length == 8)
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{
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*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
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return 8;
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}
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else
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{
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*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
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return 4;
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}
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}
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}
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@ -960,8 +1037,17 @@ sim_fetch_register (sd,rn,memory,length)
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}
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else
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{
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*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
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return 8;
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if (length == 8)
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{
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*(unsigned64*)memory =
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H2T_8 ((unsigned64) (cpu->registers[rn]));
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return 8;
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}
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else
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{
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*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
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return 4;
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}
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}
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return 0;
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@ -1235,8 +1321,39 @@ sim_monitor (SIM_DESC sd,
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/* [A0 + 4] = instruction cache size */
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/* [A0 + 8] = data cache size */
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{
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unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
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unsigned_4 value;
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unsigned_4 zero = 0;
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address_word mem_size;
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sim_memopt *entry, *match = NULL;
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/* Search for memory region mapped to KSEG0 or KSEG1. */
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for (entry = STATE_MEMOPT (sd);
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entry != NULL;
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entry = entry->next)
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{
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if ((entry->addr == K0BASE || entry->addr == K1BASE)
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&& (!match || entry->level < match->level))
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match = entry;
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else
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{
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sim_memopt *alias;
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for (alias = entry->alias;
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alias != NULL;
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alias = alias->next)
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if ((alias->addr == K0BASE || alias->addr == K1BASE)
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&& (!match || entry->level < match->level))
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match = entry;
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}
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}
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/* Get region size, limit to KSEG1 size (512MB). */
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SIM_ASSERT (match != NULL);
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mem_size = (match->modulo != 0
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? match->modulo : match->nr_bytes);
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if (mem_size > K1SIZE)
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mem_size = K1SIZE;
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value = mem_size;
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H2T (value);
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sim_write (sd, A0 + 0, (char *)&value, 4);
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sim_write (sd, A0 + 4, (char *)&zero, 4);
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@ -1924,8 +2041,7 @@ cop_lw (SIM_DESC sd,
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#ifdef DEBUG
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printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
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#endif
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StoreFPR(coproc_reg,fmt_word,(uword64)memword);
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FPR_STATE[coproc_reg] = fmt_uninterpreted;
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StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
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break;
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}
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@ -1956,7 +2072,7 @@ cop_ld (SIM_DESC sd,
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case 1:
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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StoreFPR(coproc_reg,fmt_uninterpreted,memword);
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StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
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break;
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}
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@ -1987,11 +2103,7 @@ cop_sw (SIM_DESC sd,
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case 1:
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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FP_formats hold;
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hold = FPR_STATE[coproc_reg];
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FPR_STATE[coproc_reg] = fmt_word;
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value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
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FPR_STATE[coproc_reg] = hold;
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value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
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break;
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}
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@ -2018,7 +2130,7 @@ cop_sd (SIM_DESC sd,
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case 1:
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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value = ValueFPR(coproc_reg,fmt_uninterpreted);
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value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
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break;
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}
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@ -176,29 +176,18 @@
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*vr4100:
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*vr5000:
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*r3900:
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{
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/* For historical simulator compatibility (until documentation is
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found that makes these operations unpredictable on some of these
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architectures), this check never returns true. */
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return 0;
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}
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:function:::int:not_word_value:unsigned_word value
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*mips32:
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*mips32r2:
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{
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/* On MIPS32, since registers are 32-bits, there's no check to be done. */
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return 0;
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}
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:function:::int:not_word_value:unsigned_word value
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*mips64:
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*mips64r2:
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{
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return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
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#if WITH_TARGET_WORD_BITSIZE == 64
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return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
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#else
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return 0;
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#endif
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}
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// Helper:
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//
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// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
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|
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Loading…
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