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2003-09-12 Dave Brolley <brolley@redhat.com> 

* registers.c (frv_check_spr_read_access): Check for access to
        ACC4-ACC63 and ACCG4-ACCG63.
        * profile.h (frv-desc.h): #include it.
        (spr_busy): New member of FRV_PROFILE_STATE.
        (spr_latency): Ditto.
        (GNER_FOR_GR): New macro.
        (FNER_FOR_FR): New maccro.
        (update_SPR_latency): New function.
        (vliw_wait_for_SPR): New function.
        * profile.c (profile-fr550.h): #include it.
        (update_latencies): Update SPR latencies.
        (update_target_latencies): Ditto.
        (update_SPR_latency): New function.
        (vliw_wait_for_SPR): New function.
        * profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency.
        (frvbf_model_fr500_u_trap): Removed unused variable, ps.
        (frvbf_model_fr500_u_check): Ditto.
        (frvbf_model_fr500_u_clrgr): New unit modeller for fr500.
        (frvbf_model_fr500_u_clrfr): Ditto.
        (frvbf_model_fr500_u_spr2gr): Wait for SPR.
        (frvbf_model_fr500_u_gr2spr): Ditto.
        * frv-sim.h (H_SPR_ACC4): New macro.
        (H_SPR_ACCG4): New macro;
        (H_SPR_ACC0): Removed.
        (H_SPR_ACCG0): Removed.
        * arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
This commit is contained in:
Dave Brolley 2003-09-12 22:05:22 +00:00
parent 23600bb3cd
commit 153431d6b1
11 changed files with 302 additions and 77 deletions
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29
sim/frv/ChangeLog
View File

@ -1,3 +1,32 @@
2003-09-12 Dave Brolley <brolley@redhat.com>
* registers.c (frv_check_spr_read_access): Check for access to
ACC4-ACC63 and ACCG4-ACCG63.
* profile.h (frv-desc.h): #include it.
(spr_busy): New member of FRV_PROFILE_STATE.
(spr_latency): Ditto.
(GNER_FOR_GR): New macro.
(FNER_FOR_FR): New maccro.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile.c (profile-fr550.h): #include it.
(update_latencies): Update SPR latencies.
(update_target_latencies): Ditto.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency.
(frvbf_model_fr500_u_trap): Removed unused variable, ps.
(frvbf_model_fr500_u_check): Ditto.
(frvbf_model_fr500_u_clrgr): New unit modeller for fr500.
(frvbf_model_fr500_u_clrfr): Ditto.
(frvbf_model_fr500_u_spr2gr): Wait for SPR.
(frvbf_model_fr500_u_gr2spr): Ditto.
* frv-sim.h (H_SPR_ACC4): New macro.
(H_SPR_ACCG4): New macro;
(H_SPR_ACC0): Removed.
(H_SPR_ACCG0): Removed.
* arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
2003-09-10 Dave Brolley <brolley@redhat.com>
* profile.c (slot_names): FM1 was listed twice. Changed first

30
sim/frv/arch.h
View File

@ -47,21 +47,21 @@ typedef enum unit_type {
, UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR, UNIT_FR500_U_GR2FR
, UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR, UNIT_FR500_U_SWAP
, UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD, UNIT_FR500_U_GR_R_STORE
, UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CHECK
, UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL
, UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL
, UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF
, UNIT_FR400_U_DCI, UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER
, UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6
, UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD
, UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB
, UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2
, UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR
, UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP
, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD
, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH
, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC
, UNIT_SIMPLE_U_EXEC, UNIT_MAX
, UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CLRFR
, UNIT_FR500_U_CLRGR, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH
, UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC
, UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL
, UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI, UNIT_FR400_U_ICI
, UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND
, UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG
, UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3
, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC
, UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD
, UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR
, UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD
, UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK
, UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL
, UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)

60
sim/frv/decode.c
View File

@ -578,8 +578,8 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_CLRFR, FRVBF_INSN_CLRFR, FRVBF_SFMT_CLRFR },
{ FRV_INSN_CLRGA, FRVBF_INSN_CLRGA, FRVBF_SFMT_REI },
{ FRV_INSN_CLRFA, FRVBF_INSN_CLRFA, FRVBF_SFMT_REI },
{ FRV_INSN_COMMITGR, FRVBF_INSN_COMMITGR, FRVBF_SFMT_CLRGR },
{ FRV_INSN_COMMITFR, FRVBF_INSN_COMMITFR, FRVBF_SFMT_CLRFR },
{ FRV_INSN_COMMITGR, FRVBF_INSN_COMMITGR, FRVBF_SFMT_COMMITGR },
{ FRV_INSN_COMMITFR, FRVBF_INSN_COMMITFR, FRVBF_SFMT_COMMITFR },
{ FRV_INSN_COMMITGA, FRVBF_INSN_COMMITGA, FRVBF_SFMT_REI },
{ FRV_INSN_COMMITFA, FRVBF_INSN_COMMITFA, FRVBF_SFMT_REI },
{ FRV_INSN_FITOS, FRVBF_INSN_FITOS, FRVBF_SFMT_FITOS },
@ -1191,9 +1191,9 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1 : itype = FRVBF_INSN_CLRGA; goto extract_sfmt_rei;
case 2 : itype = FRVBF_INSN_CLRFR; goto extract_sfmt_clrfr;
case 3 : itype = FRVBF_INSN_CLRFA; goto extract_sfmt_rei;
case 4 : itype = FRVBF_INSN_COMMITGR; goto extract_sfmt_clrgr;
case 4 : itype = FRVBF_INSN_COMMITGR; goto extract_sfmt_commitgr;
case 5 : itype = FRVBF_INSN_COMMITGA; goto extract_sfmt_rei;
case 6 : itype = FRVBF_INSN_COMMITFR; goto extract_sfmt_clrfr;
case 6 : itype = FRVBF_INSN_COMMITFR; goto extract_sfmt_commitfr;
case 7 : itype = FRVBF_INSN_COMMITFA; goto extract_sfmt_rei;
case 8 : itype = FRVBF_INSN_ANDCR; goto extract_sfmt_andcr;
case 9 : itype = FRVBF_INSN_ORCR; goto extract_sfmt_andcr;
@ -7496,7 +7496,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_setlos.f
#define FLD(f) abuf->fields.sfmt_swapi.f
UINT f_GRk;
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
@ -7505,6 +7505,13 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_GRk) = f_GRk;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrgr", "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_GRk) = f_GRk;
}
#endif
#undef FLD
return idesc;
}
@ -7513,6 +7520,47 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cfmadds.f
UINT f_FRk;
f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
/* Record the fields for the semantic handler. */
FLD (f_FRk) = f_FRk;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrfr", "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_FRk) = f_FRk;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_commitgr:
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_setlos.f
UINT f_GRk;
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
/* Record the fields for the semantic handler. */
FLD (f_GRk) = f_GRk;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_commitgr", "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
#undef FLD
return idesc;
}
extract_sfmt_commitfr:
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mhsethis.f
UINT f_FRk;
@ -7520,7 +7568,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for the semantic handler. */
FLD (f_FRk) = f_FRk;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrfr", "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_commitfr", "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
#undef FLD
return idesc;

51
sim/frv/decode.h
View File

@ -266,30 +266,31 @@ typedef enum frvbf_sfmt_type {
, FRVBF_SFMT_FCKNE, FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA
, FRVBF_SFMT_CFCKNE, FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI
, FRVBF_SFMT_ICPL, FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR
, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI
, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI
, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD
, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS
, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS
, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS
, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS
, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS
, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH
, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND
, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT
, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI
, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI
, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS
, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS
, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS
, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU
, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU
, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS
, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD
, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH
, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB
, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0
, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
, FRVBF_SFMT_COMMITGR, FRVBF_SFMT_COMMITFR, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI
, FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI
, FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI
, FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS
, FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS
, FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS
, FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS
, FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS
, FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS
, FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH
, FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT
, FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT
, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI
, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS
, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS
, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS
, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS
, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU
, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU
, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW
, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH
, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH
, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE
, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG
, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE;
/* Function unit handlers (user written). */
@ -336,6 +337,8 @@ extern int frvbf_model_fr500_u_gr_r_store (SIM_CPU *, const IDESC *, int /*unit_
extern int frvbf_model_fr500_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
extern int frvbf_model_fr500_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
extern int frvbf_model_fr500_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/);
extern int frvbf_model_fr500_u_clrfr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRk*/);
extern int frvbf_model_fr500_u_clrgr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/);
extern int frvbf_model_fr500_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/);
extern int frvbf_model_fr500_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
extern int frvbf_model_fr500_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);

6
sim/frv/frv-sim.h
View File

@ -1,5 +1,5 @@
/* collection of junk waiting time to sort out
Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU Simulators.
@ -24,9 +24,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "sim-options.h"
/* Not defined in the cgen cpu file for access restriction purposes. */
#define H_SPR_ACC0 1408
#define H_SPR_ACC4 1412
#define H_SPR_ACC63 1471
#define H_SPR_ACCG0 1472
#define H_SPR_ACCG4 1476
#define H_SPR_ACCG63 1535
/* gdb register numbers. */

44
sim/frv/model.c
View File

@ -8485,7 +8485,7 @@ model_frv_cop2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_frv_clrgr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_setlos.f
#define FLD(f) abuf->fields.sfmt_swapi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -8501,7 +8501,7 @@ model_frv_clrgr (SIM_CPU *current_cpu, void *sem_arg)
static int
model_frv_clrfr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mhsethis.f
#define FLD(f) abuf->fields.sfmt_cfmadds.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -24136,14 +24136,17 @@ model_fr500_cop2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_fr500_clrgr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_setlos.f
#define FLD(f) abuf->fields.sfmt_swapi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
INT in_GRk = -1;
in_GRk = FLD (in_GRk);
referenced |= 1 << 0;
cycles += frvbf_model_fr500_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk);
}
return cycles;
#undef FLD
@ -24152,14 +24155,17 @@ model_fr500_clrgr (SIM_CPU *current_cpu, void *sem_arg)
static int
model_fr500_clrfr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mhsethis.f
#define FLD(f) abuf->fields.sfmt_cfmadds.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
INT in_FRk = -1;
in_FRk = FLD (in_FRk);
referenced |= 1 << 0;
cycles += frvbf_model_fr500_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk);
}
return cycles;
#undef FLD
@ -24175,7 +24181,8 @@ model_fr500_clrga (SIM_CPU *current_cpu, void *sem_arg)
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
INT in_GRk = -1;
cycles += frvbf_model_fr500_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk);
}
return cycles;
#undef FLD
@ -24191,7 +24198,8 @@ model_fr500_clrfa (SIM_CPU *current_cpu, void *sem_arg)
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
INT in_FRk = -1;
cycles += frvbf_model_fr500_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk);
}
return cycles;
#undef FLD
@ -37720,7 +37728,7 @@ model_tomcat_cop2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_tomcat_clrgr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_setlos.f
#define FLD(f) abuf->fields.sfmt_swapi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -37736,7 +37744,7 @@ model_tomcat_clrgr (SIM_CPU *current_cpu, void *sem_arg)
static int
model_tomcat_clrfr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mhsethis.f
#define FLD(f) abuf->fields.sfmt_cfmadds.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -52883,7 +52891,7 @@ model_fr400_cop2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_fr400_clrgr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_setlos.f
#define FLD(f) abuf->fields.sfmt_swapi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -52899,7 +52907,7 @@ model_fr400_clrgr (SIM_CPU *current_cpu, void *sem_arg)
static int
model_fr400_clrfr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mhsethis.f
#define FLD(f) abuf->fields.sfmt_cfmadds.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -65535,7 +65543,7 @@ model_simple_cop2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_simple_clrgr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_setlos.f
#define FLD(f) abuf->fields.sfmt_swapi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -65551,7 +65559,7 @@ model_simple_clrgr (SIM_CPU *current_cpu, void *sem_arg)
static int
model_simple_clrfr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mhsethis.f
#define FLD(f) abuf->fields.sfmt_cfmadds.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -70215,10 +70223,10 @@ static const INSN_TIMING fr500_timing[] = {
{ FRVBF_INSN_MEMBAR, model_fr500_membar, { { (int) UNIT_FR500_U_MEMBAR, 1, 1 } } },
{ FRVBF_INSN_COP1, model_fr500_cop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP2, model_fr500_cop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_fr500_clrgr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRFR, model_fr500_clrfr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGA, model_fr500_clrga, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRFA, model_fr500_clrfa, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_fr500_clrgr, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } },
{ FRVBF_INSN_CLRFR, model_fr500_clrfr, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } },
{ FRVBF_INSN_CLRGA, model_fr500_clrga, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } },
{ FRVBF_INSN_CLRFA, model_fr500_clrfa, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } },
{ FRVBF_INSN_COMMITGR, model_fr500_commitgr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COMMITFR, model_fr500_commitfr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COMMITGA, model_fr500_commitga, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },

67
sim/frv/profile-fr500.c
View File

@ -1,6 +1,6 @@
/* frv simulator fr500 dependent profiling code.
Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat
This file is part of the GNU simulators.
@ -382,6 +382,12 @@ frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
update_CCR_latency (cpu, out_ICCi_1, cycles + 19);
set_use_is_cc_complex (cpu, out_ICCi_1);
if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
{
/* GNER has a latency of 18 cycles. */
update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18);
}
/* the idiv resource has a latency of 18 cycles! */
update_idiv_resource_latency (cpu, slot, cycles + 18);
@ -458,7 +464,6 @@ frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc,
INT in_ICCi_2, INT in_FCCi_2)
{
int cycles;
FRV_PROFILE_STATE *ps;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
@ -502,7 +507,6 @@ frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
INT in_ICCi_3, INT in_FCCi_3)
{
int cycles;
FRV_PROFILE_STATE *ps;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
@ -523,6 +527,58 @@ frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
return cycles;
}
int
frvbf_model_fr500_u_clrgr (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRk)
{
int cycles;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
/* Wait for both GNER registers or just the one specified. */
if (in_GRk == -1)
{
vliw_wait_for_SPR (cpu, H_SPR_GNER0);
vliw_wait_for_SPR (cpu, H_SPR_GNER1);
}
else
vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk));
handle_resource_wait (cpu);
trace_vliw_wait_cycles (cpu);
return 0;
}
cycles = idesc->timing->units[unit_num].done;
return cycles;
}
int
frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRk)
{
int cycles;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
/* Wait for both GNER registers or just the one specified. */
if (in_FRk == -1)
{
vliw_wait_for_SPR (cpu, H_SPR_FNER0);
vliw_wait_for_SPR (cpu, H_SPR_FNER1);
}
else
vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk));
handle_resource_wait (cpu);
trace_vliw_wait_cycles (cpu);
return 0;
}
cycles = idesc->timing->units[unit_num].done;
return cycles;
}
int
frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
@ -962,8 +1018,8 @@ frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
/* The entire VLIW insn must wait if there is a dependency on a register
which is not ready yet.
SPR registers appear to have no latency effects. */
which is not ready yet. */
vliw_wait_for_SPR (cpu, in_spr);
vliw_wait_for_GR (cpu, out_GRj);
handle_resource_wait (cpu);
load_wait_for_GR (cpu, out_GRj);
@ -1046,6 +1102,7 @@ frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
decrease_GR_busy (cpu, in_GRj, 1);
}
vliw_wait_for_GR (cpu, in_GRj);
vliw_wait_for_SPR (cpu, out_spr);
handle_resource_wait (cpu);
load_wait_for_GR (cpu, in_GRj);
trace_vliw_wait_cycles (cpu);

55
sim/frv/profile.c
View File

@ -681,6 +681,7 @@ update_latencies (SIM_CPU *cpu, int cycles)
int *gr = ps->gr_busy;
int *fr = ps->fr_busy;
int *acc = ps->acc_busy;
int *spr;
/* This loop handles GR, FR and ACC registers. */
for (i = 0; i < 64; ++i)
{
@ -734,6 +735,16 @@ update_latencies (SIM_CPU *cpu, int cycles)
*ccr -= cycles;
++ccr;
}
/* This loop handles SPR registers. */
spr = ps->spr_busy;
for (i = 0; i < 4096; ++i)
{
if (*spr <= cycles)
*spr = 0;
else
*spr -= cycles;
++spr;
}
/* This loop handles resources. */
idiv = ps->idiv_busy;
fdiv = ps->fdiv_busy;
@ -805,10 +816,12 @@ update_target_latencies (SIM_CPU *cpu)
int *gr_lat = ps->gr_latency;
int *fr_lat = ps->fr_latency;
int *acc_lat = ps->acc_latency;
int *spr_lat;
int *ccr;
int *gr = ps->gr_busy;
int *fr = ps->fr_busy;
int *acc = ps->acc_busy;
int *spr;
/* This loop handles GR, FR and ACC registers. */
for (i = 0; i < 64; ++i)
{
@ -843,6 +856,18 @@ update_target_latencies (SIM_CPU *cpu)
}
++ccr; ++ccr_lat;
}
/* This loop handles SPR registers. */
spr = ps->spr_busy;
spr_lat = ps->spr_latency;
for (i = 0; i < 4096; ++i)
{
if (*spr_lat)
{
*spr = *spr_lat;
*spr_lat = 0;
}
++spr; ++spr_lat;
}
}
/* Run the caches until all pending cache flushes are complete. */
@ -1207,6 +1232,19 @@ update_CCR_latency (SIM_CPU *cpu, INT out_CCR, int cycles)
}
}
/* Top up the latency of the given SPR by the given number of cycles. */
void
update_SPR_latency (SIM_CPU *cpu, INT out_SPR, int cycles)
{
if (out_SPR >= 0)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *spr = ps->spr_latency;
if (spr[out_SPR] < cycles)
spr[out_SPR] = cycles;
}
}
/* Top up the latency of the given integer division resource by the given
number of cycles. */
void
@ -1376,6 +1414,23 @@ vliw_wait_for_ACC (SIM_CPU *cpu, INT in_ACC)
}
}
/* Check the availability of the given SPR register and update the number
of cycles the current VLIW insn must wait until it is available. */
void
vliw_wait_for_SPR (SIM_CPU *cpu, INT in_SPR)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *spr = ps->spr_busy;
/* If the latency of the register is greater than the current wait
then update the current wait. */
if (in_SPR >= 0 && spr[in_SPR] > ps->vliw_wait)
{
if (TRACE_INSN_P (cpu))
sprintf (hazard_name, "Data hazard for spr %d:", in_SPR);
ps->vliw_wait = spr[in_SPR];
}
}
/* Check the availability of the given integer division resource and update
the number of cycles the current VLIW insn must wait until it is available.
*/

21
sim/frv/profile.h
View File

@ -1,5 +1,5 @@
/* Profiling definitions for the FRV simulator
Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU Simulators.
@ -21,6 +21,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#ifndef PROFILE_H
#define PROFILE_H
#include "frv-desc.h"
/* This struct defines the state of profiling. All fields are of general
use to all machines. */
typedef struct
@ -39,6 +41,7 @@ typedef struct
int fr_busy[64]; /* Cycles until FR is available. */
int acc_busy[64]; /* Cycles until FR is available. */
int ccr_busy[8]; /* Cycles until ICC/FCC is available. */
int spr_busy[4096]; /* Cycles until spr is available. */
int idiv_busy[2]; /* Cycles until integer division unit is available. */
int fdiv_busy[2]; /* Cycles until float division unit is available. */
int fsqrt_busy[2]; /* Cycles until square root unit is available. */
@ -48,6 +51,7 @@ typedef struct
int fr_latency[64]; /* Cycles until target FR is available. */
int acc_latency[64]; /* Cycles until target FR is available. */
int ccr_latency[8]; /* Cycles until target ICC/FCC is available. */
int spr_latency[4096]; /* Cycles until target spr is available. */
/* Some registers are busy for a shorter number of cycles than normal
depending on how they are used next. the xxx_busy_adjust arrays keep track
@ -84,6 +88,19 @@ typedef struct
#define DUAL_REG(reg) ((reg) >= 0 && (reg) < 63 ? (reg) + 1 : -1)
#define DUAL_DOUBLE(reg) ((reg) >= 0 && (reg) < 61 ? (reg) + 2 : -1)
/* Return the GNER register associated with the given GR register.
There is no GNER associated with gr0. */
#define GNER_FOR_GR(gr) ((gr) > 63 ? -1 : \
(gr) > 31 ? H_SPR_GNER0 : \
(gr) > 0 ? H_SPR_GNER1 : \
-1)
/* Return the GNER register associated with the given GR register.
There is no GNER associated with gr0. */
#define FNER_FOR_FR(fr) ((fr) > 63 ? -1 : \
(fr) > 31 ? H_SPR_FNER0 : \
(fr) > 0 ? H_SPR_FNER1 : \
-1)
/* Top up the latency of the given GR by the given number of cycles. */
void update_GR_latency (SIM_CPU *, INT, int);
void update_GRdouble_latency (SIM_CPU *, INT, int);
@ -100,6 +117,7 @@ void decrease_GR_busy (SIM_CPU *, INT, int);
void increase_FR_busy (SIM_CPU *, INT, int);
void update_ACC_latency (SIM_CPU *, INT, int);
void update_CCR_latency (SIM_CPU *, INT, int);
void update_SPR_latency (SIM_CPU *, INT, int);
void update_idiv_resource_latency (SIM_CPU *, INT, int);
void update_fdiv_resource_latency (SIM_CPU *, INT, int);
void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
@ -111,6 +129,7 @@ void vliw_wait_for_FR (SIM_CPU *, INT);
void vliw_wait_for_FRdouble (SIM_CPU *, INT);
void vliw_wait_for_CCR (SIM_CPU *, INT);
void vliw_wait_for_ACC (SIM_CPU *, INT);
void vliw_wait_for_SPR (SIM_CPU *, INT);
void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);

6
sim/frv/registers.c
View File

@ -1,5 +1,5 @@
/* frv simulator support code
Copyright (C) 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
@ -4278,8 +4278,8 @@ frv_check_spr_read_access (SIM_CPU *current_cpu, UINT spr)
/* On the fr400: if this is an unimplemented accumulator, then
generate an illegal_instruction_interrupt, otherwise no interrupt.
*/
if (spr >= H_SPR_ACC0 && spr <= H_SPR_ACC63
|| spr >= H_SPR_ACCG0 && spr <= H_SPR_ACCG63)
if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63
|| spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63)
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
}
else

10
sim/frv/sem.c
View File

@ -16532,13 +16532,16 @@ SEM_FN_NAME (frvbf,cop2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (frvbf,clrgr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_setlos.f
#define FLD(f) abuf->fields.sfmt_swapi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
frv_ref_SI (GET_H_GR (FLD (f_GRk)));
frvbf_clear_ne_flags (current_cpu, FLD (f_GRk), 0);
}
return vpc;
#undef FLD
@ -16549,13 +16552,16 @@ frvbf_clear_ne_flags (current_cpu, FLD (f_GRk), 0);
static SEM_PC
SEM_FN_NAME (frvbf,clrfr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mhsethis.f
#define FLD(f) abuf->fields.sfmt_cfmadds.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
frv_ref_SI (GET_H_FR (FLD (f_FRk)));
frvbf_clear_ne_flags (current_cpu, FLD (f_FRk), 1);
}
return vpc;
#undef FLD