2002-05-31 Chris G. Demetriou <cgd@broadcom.com>
* mips-opc.c: Clean up a few whitespace issues, and sort a few entries understanding that 'x' follows 'w' in the alphabet.
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@ -1,3 +1,8 @@
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2002-05-31 Chris G. Demetriou <cgd@broadcom.com>
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* mips-opc.c: Clean up a few whitespace issues, and sort a
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few entries understanding that 'x' follows 'w' in the alphabet.
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2002-05-31 Chris G. Demetriou <cgd@broadcom.com>
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2002-05-31 Chris G. Demetriou <cgd@broadcom.com>
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Ed Satterthwaite <ehs@broadcom.com>
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Ed Satterthwaite <ehs@broadcom.com>
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@ -75,8 +75,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define IS_M INSN_MULT
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#define IS_M INSN_MULT
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#define WR_MACC INSN_WRITE_MDMX_ACC
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#define WR_MACC INSN_WRITE_MDMX_ACC
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#define RD_MACC INSN_READ_MDMX_ACC
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#define RD_MACC INSN_READ_MDMX_ACC
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#define I1 INSN_ISA1
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#define I1 INSN_ISA1
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#define I2 INSN_ISA2
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#define I2 INSN_ISA2
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@ -90,7 +90,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define M3D INSN_MIPS3D
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#define M3D INSN_MIPS3D
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/* MIPS64 MDMX ASE support. */
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/* MIPS64 MDMX ASE support. */
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#define MX INSN_MDMX
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#define MX INSN_MDMX
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#define P3 INSN_4650
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#define P3 INSN_4650
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#define L1 INSN_4010
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#define L1 INSN_4010
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@ -1007,11 +1007,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 },
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{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 },
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{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 },
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{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 },
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{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
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{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
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{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
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{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
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{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
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{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
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{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 },
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{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 },
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{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
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{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
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{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
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{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
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@ -1020,6 +1015,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
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{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
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{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
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{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
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{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
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{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
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{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
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{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
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{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
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{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
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/* No hazard protection on coprocessor instructions--they shouldn't
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/* No hazard protection on coprocessor instructions--they shouldn't
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change the state of the processor and if they do it's up to the
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change the state of the processor and if they do it's up to the
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