Add scheduling support for M{F,T}CR
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@ -301,14 +301,14 @@ void::model-function::ppc_insn_int2:itable_index index, cpu *processor, model_da
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}
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busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]);
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ppc_regs[ppc_RD].next = (model_reg *)0;
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ppc_regs[ppc_RD].in_use = 1;
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if (!Rc)
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busy_ptr->reg = &ppc_regs[ppc_RD];
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else {
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model_reg *reg_CR0 = &ppc_regs[0 + PPC_CR_REG];
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reg_CR0->next = &ppc_regs[ppc_RD];
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busy_ptr->reg = reg_CR0;
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ppc_regs[ppc_RD].next = (model_reg *)0;
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ppc_regs[ppc_RD].in_use = 1;
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if (!Rc)
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busy_ptr->reg = &ppc_regs[ppc_RD];
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else {
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model_reg *reg_CR0 = &ppc_regs[0 + PPC_CR_REG];
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reg_CR0->next = &ppc_regs[ppc_RD];
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busy_ptr->reg = reg_CR0;
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}
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}
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@ -584,6 +584,68 @@ void::model-function::ppc_insn_to_spr:itable_index index, cpu *processor, model_
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busy_ptr->reg = &ppc_regs[ppc_SPR];
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}
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# Schedule a MFCR instruction that moves the CR into an integer regsiter
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void::model-function::ppc_insn_mfcr:itable_index index, cpu *processor, model_data *model_ptr, signed_word *rD
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if (!WITH_MODEL_ISSUE)
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return;
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else {
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registers *cpu_regs = cpu_registers(processor);
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const unsigned ppc_RD = (rD - &cpu_regs->gpr[0]) + PPC_INT_REG;
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model_reg *ppc_regs = model_ptr->registers;
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model_busy *busy_ptr;
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while (ppc_regs[0 + PPC_CR_REG].in_use
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| ppc_regs[1 + PPC_CR_REG].in_use
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| ppc_regs[2 + PPC_CR_REG].in_use
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| ppc_regs[3 + PPC_CR_REG].in_use
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| ppc_regs[4 + PPC_CR_REG].in_use
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| ppc_regs[5 + PPC_CR_REG].in_use
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| ppc_regs[6 + PPC_CR_REG].in_use
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| ppc_regs[7 + PPC_CR_REG].in_use) {
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model_ptr->nr_stalls_data++;
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model_new_cycle(model_ptr);
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}
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busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]);
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ppc_regs[ppc_RD].next = (model_reg *)0;
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ppc_regs[ppc_RD].in_use = 1;
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busy_ptr->reg = &ppc_regs[ppc_RD];
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}
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# Schedule a MTCR instruction that moves an integer register into the CR
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void::model-function::ppc_insn_mtcr:itable_index index, cpu *processor, model_data *model_ptr, signed_word *rT
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if (!WITH_MODEL_ISSUE)
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return;
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else {
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registers *cpu_regs = cpu_registers(processor);
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const unsigned ppc_RT = (rT - &cpu_regs->gpr[0]) + PPC_INT_REG;
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model_reg *ppc_regs = model_ptr->registers;
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model_busy *busy_ptr;
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model_reg *prev_reg;
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int i;
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if (ppc_regs[ppc_RT].in_use) {
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model_new_cycle(model_ptr); /* don't count first dependency as a stall */
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while (ppc_regs[ppc_RT].in_use) {
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model_ptr->nr_stalls_data++;
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model_new_cycle(model_ptr);
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}
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}
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busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]);
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prev_reg = (model_reg *)0;
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for (i = 0; i < 8; i++) {
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ppc_regs[i + PPC_CR_REG].next = prev_reg;
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ppc_regs[i + PPC_CR_REG].in_use = 1;
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prev_reg = &ppc_regs[i + PPC_CR_REG];
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}
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busy_ptr->reg = prev_reg;
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}
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model_data *::model-function::model_create:cpu *processor
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model_data *model_ptr = ZALLOC(model_data);
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ASSERT(CURRENT_MODEL > 0 && CURRENT_MODEL < nr_models);
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@ -2953,6 +3015,7 @@ void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia,
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}
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CR = (MASKED(*rS, 32, 63) & mask) | (CR & ~mask);
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}
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ppc_insn_mtcr(my_index, processor, cpu_model(processor), rS);
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0.31,6.BF,9./,11./,16./,21.512,31./:X:::Move to Condition Register from XER
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@ -2962,6 +3025,7 @@ void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia,
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*603e:PPC_UNIT_SRU, PPC_UNIT_SRU, 1, 1, 0
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*604: PPC_UNIT_MCIU, PPC_UNIT_MCIU, 3, 3, 0
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*rT = (unsigned32)CR;
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ppc_insn_mfcr(my_index, processor, cpu_model(processor), rT);
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#
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# I.4.6.2 Floating-Point Load Instructions
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