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Add missing Cpu flags in bd and bt cores 

gas/testsuite/

2012-09-25  Saravanan Ekanathan <saravanan.ekanathan@amd.com>

	* gas/i386/arch-10-bdver1.d: New file to test bdver1 core.
	* gas/i386/x86-64-arch-2-bdver1.d: Likewise.
	* gas/i386/i386.exp: Run bdver1 testcases.
	* gas/i386/arch-10-bdver2.d: Updated -march flags.
	* gas/i386/arch-10-btver1.d: Likewise.
	* gas/i386/arch-10-btver2.d: Likewise.
	* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
	* gas/i386/x86-64-arch-2-btver1.d: Likewise.
	* gas/i386/x86-64-arch-2-btver2.d: Likewise.

opcodes/

2012-09-25  Saravanan Ekanathan <saravanan.ekanathan@amd.com>

	* gas/i386/arch-10-bdver1.d: New file to test bdver1 core.
	* gas/i386/x86-64-arch-2-bdver1.d: Likewise.
	* gas/i386/i386.exp: Run bdver1 testcases.
	* gas/i386/arch-10-bdver2.d: Updated -march flags.
	* gas/i386/arch-10-btver1.d: Likewise.
	* gas/i386/arch-10-btver2.d: Likewise.
	* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
	* gas/i386/x86-64-arch-2-btver1.d: Likewise.
	* gas/i386/x86-64-arch-2-btver2.d: Likewise.
This commit is contained in:
H.J. Lu 2012-09-25 13:12:34 +00:00
parent 744a805904
commit 160a30bb92
13 changed files with 127 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
gas/testsuite/ChangeLog
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@ -1,3 +1,15 @@
2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
* gas/i386/arch-10-bdver1.d: New file to test bdver1 core.
* gas/i386/x86-64-arch-2-bdver1.d: Likewise.
* gas/i386/i386.exp: Run bdver1 testcases.
* gas/i386/arch-10-bdver2.d: Updated -march flags.
* gas/i386/arch-10-btver1.d: Likewise.
* gas/i386/arch-10-btver2.d: Likewise.
* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
* gas/i386/x86-64-arch-2-btver1.d: Likewise.
* gas/i386/x86-64-arch-2-btver2.d: Likewise.
2012-09-23 Maciej W. Rozycki <macro@codesourcery.com>
* gas/mips/hilo-diff-eb.d: New test.

42
gas/testsuite/gas/i386/arch-10-bdver1.d Normal file
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@ -0,0 +1,42 @@
#source: arch-10.s
#as: -march=bdver1+vmx+smx+xsaveopt+fma+movbe+ept+padlock+bmi+tbm
#objdump: -dw
#name: i386 arch 10 (bdver1)
.*: file format .*
Disassembly of section .text:
0+ <.text>:
[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx
[ ]*[a-f0-9]+: 0f ae 38 clflush \(%eax\)
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3
[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3
[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3
[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3
[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3
[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3
[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
[ ]*[a-f0-9]+: c5 fc 77 vzeroall
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
[ ]*[a-f0-9]+: 0f 37 getsec
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%ecx\)
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%ecx\),%xmm0,%xmm2
[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%esi,2\)
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
[ ]*[a-f0-9]+: 0f 01 da vmload
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
#pass

2
gas/testsuite/gas/i386/arch-10-bdver2.d
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@ -1,5 +1,5 @@
#source: arch-10.s
#as: -march=bdver2+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+ept+clflush+svme+padlock+prfchw
#as: -march=bdver2+vmx+smx+xsaveopt+movbe+ept+padlock
#objdump: -dw
#name: i386 arch 10 (bdver2)

2
gas/testsuite/gas/i386/arch-10-btver1.d
View File

@ -1,5 +1,5 @@
#source: arch-10.s
#as: -march=btver1+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+ept+clflush+svme+padlock+fma+bmi+tbm
#as: -march=btver1+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+ept+padlock+fma+bmi+tbm
#objdump: -dw
#name: i386 arch 10 (btver1)

2
gas/testsuite/gas/i386/arch-10-btver2.d
View File

@ -1,5 +1,5 @@
#source: arch-10.s
#as: -march=btver2+smx+vmx+ept+clflush+svme+padlock+fma+tbm
#as: -march=btver2+smx+vmx+ept+padlock+fma+tbm
#objdump: -dw
#name: i386 arch 10 (btver2)

2
gas/testsuite/gas/i386/i386.exp
View File

@ -129,6 +129,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "arch-10"
run_dump_test "arch-10-lzcnt"
run_dump_test "arch-10-prefetchw"
run_dump_test "arch-10-bdver1"
run_dump_test "arch-10-bdver2"
run_dump_test "arch-10-btver1"
run_dump_test "arch-10-btver2"
@ -396,6 +397,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-arch-2"
run_dump_test "x86-64-arch-2-lzcnt"
run_dump_test "x86-64-arch-2-prefetchw"
run_dump_test "x86-64-arch-2-bdver1"
run_dump_test "x86-64-arch-2-bdver2"
run_dump_test "x86-64-arch-2-btver1"
run_dump_test "x86-64-arch-2-btver2"

42
gas/testsuite/gas/i386/x86-64-arch-2-bdver1.d Normal file
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@ -0,0 +1,42 @@
#source: x86-64-arch-2.s
#as: -march=bdver1+vmx+smx+xsaveopt+fma+movbe+ept+padlock+bmi+tbm
#objdump: -dw
#name: x86-64 arch 2 (bdver1)
.*: file format .*
Disassembly of section .text:
0+ <.text>:
[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx
[ ]*[a-f0-9]+: 0f ae 38 clflush \(%rax\)
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3
[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3
[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3
[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3
[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3
[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3
[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
[ ]*[a-f0-9]+: c5 fc 77 vzeroall
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
[ ]*[a-f0-9]+: 0f 37 getsec
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%rcx\)
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%rcx\),%xmm0,%xmm2
[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
[ ]*[a-f0-9]+: 48 0f c7 0e cmpxchg16b \(%rsi\)
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%rsi,2\)
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
[ ]*[a-f0-9]+: 0f 01 da vmload
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
#pass

2
gas/testsuite/gas/i386/x86-64-arch-2-bdver2.d
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@ -1,5 +1,5 @@
#source: x86-64-arch-2.s
#as: -march=bdver2+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+cx16+ept+clflush+svme+padlock+prfchw
#as: -march=bdver2+vmx+smx+xsaveopt+movbe+ept+padlock
#objdump: -dw
#name: x86-64 arch 2 (bdver2)

2
gas/testsuite/gas/i386/x86-64-arch-2-btver1.d
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@ -1,5 +1,5 @@
#source: x86-64-arch-2.s
#as: -march=btver1+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+cx16+ept+clflush+svme+padlock+fma+bmi+tbm
#as: -march=btver1+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+ept+padlock+fma+bmi+tbm
#objdump: -dw
#name: x86-64 arch 2 (btver1)

2
gas/testsuite/gas/i386/x86-64-arch-2-btver2.d
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@ -1,5 +1,5 @@
#source: x86-64-arch-2.s
#as: -march=btver2+smx+vmx+ept+clflush+svme+padlock+fma+tbm
#as: -march=btver2+smx+vmx+ept+padlock+fma+tbm
#objdump: -dw
#name: x86-64 arch 2 (btver2)

7
opcodes/ChangeLog
View File

@ -1,3 +1,10 @@
2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
* i386-gen.c (cpu_flag_init): Add missing Cpu flags in
CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
and CPU_BTVER2_FLAGS.
* i386-init.h: Regenerated.
2012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,

8
opcodes/i386-gen.c
View File

@ -89,13 +89,13 @@ static initializer cpu_flag_init[] =
{ "CPU_AMDFAM10_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
{ "CPU_BDVER1_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA4|CpuXOP|CpuLWP|CpuCX16" },
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA4|CpuXOP|CpuLWP|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" },
{ "CPU_BDVER2_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16" },
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" },
{ "CPU_BTVER1_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4a|CpuABM|CpuLM|CpuPRFCHW|CpuCX16" },
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4a|CpuABM|CpuLM|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME|CpuLZCNT" },
{ "CPU_BTVER2_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4a|CpuSSE4_1|CpuSSE4_2|CpuABM|CpuLM|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuAVX|CpuMovbe|CpuXsave|CpuXsaveopt|CpuPRFCHW|CpuCX16" },
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4a|CpuSSE4_1|CpuSSE4_2|CpuABM|CpuLM|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuAVX|CpuMovbe|CpuXsave|CpuXsaveopt|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME|CpuLZCNT" },
{ "CPU_8087_FLAGS",
"Cpu8087" },
{ "CPU_287_FLAGS",

24
opcodes/i386-init.h
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@ -158,27 +158,27 @@
0, 0, 0 } }
#define CPU_BDVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, \
1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0 } }
#define CPU_BDVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, \
1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0 } }
#define CPU_BTVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0 } }
#define CPU_BTVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, \
0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, \
0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0 } }
#define CPU_8087_FLAGS \