diff --git a/sim/mips/.Sanitize b/sim/mips/.Sanitize index f56d3bb3ce..fce872ae4e 100644 --- a/sim/mips/.Sanitize +++ b/sim/mips/.Sanitize @@ -17,6 +17,20 @@ Do-first: +r5900_files="r5900.igen" +if ( echo $* | grep keep\-r5900 > /dev/null ) ; then + keep_these_too="${r5900_files} ${keep_these_too}" +else + lose_these_too="${r5900_files} ${lose_these_too}" +fi + +vr5400_files="vr5400.igen" +if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then + keep_these_too="${vr5400_files} ${keep_these_too}" +else + lose_these_too="${vr5400_files} ${lose_these_too}" +fi + # All files listed between the "Things-to-keep:" line and the # "Files-to-sed:" line will be kept. All other files will be removed. # Directories listed in this section will have their own Sanitize @@ -37,6 +51,7 @@ sim-main.h support.h tconfig.in mips.igen +m16.igen mips.dc Things-to-lose: @@ -44,7 +59,7 @@ Things-to-lose: Do-last: -r5900_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc" +r5900_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc m16.igen r5900.igen" if ( echo $* | grep keep\-r5900 > /dev/null ) ; then for i in $r5900_files ; do @@ -74,7 +89,7 @@ else fi -tx19_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc" +tx19_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc m16.igen" if ( echo $* | grep keep\-tx19 > /dev/null ) ; then for i in $tx19_files ; do @@ -104,7 +119,7 @@ else fi -vr5400_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc" +vr5400_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen" if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then for i in $vr5400_files ; do diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index e0ae3731cb..a82c18099d 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,26 @@ +Mon Oct 27 17:53:59 1997 Andrew Cagney + + * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. + + interp.c (sim_engine_run): Do not compile function sim_engine_run + when WITH_IGEN == 1. + + * configure.in (sim_igen_flags, sim_m16_flags): Set according to + target architecture. + + Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to + igen. Replace with configuration variables sim_igen_flags / + sim_m16_flags. + + end-sanitize-v5900 + * r5900.igen: New file. Copy v5900 insns here. + start-sanitize-r5900 + end-sanitize-v5400 + * vr5400.igen: New file. + start-sanitize-vr5400 + * m16.igen: New file. Copy mips16 insns here. + * mips.igen: From here. + Mon Oct 27 13:53:59 1997 Andrew Cagney start-sanitize-vr5400 diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index 391cd248a5..30fe9bd16b 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -54,6 +54,10 @@ SIM_OBJS = \ # List of flags to always pass to $(CC). SIM_SUBTARGET=@SIM_SUBTARGET@ +SIM_NO_CFLAGS = -DWITH_IGEN=0 +SIM_IGEN_CFLAGS = -DWITH_IGEN=1 +SIM_M16_CFLAGS = -DWITH_IGEN=1 + # FIXME: Hack to find syscall.h? Better support for syscall.h # is in progress. SIM_EXTRA_CFLAGS = \ @@ -98,7 +102,6 @@ IGEN_INSN=$(srcdir)/mips.igen IGEN_DC=$(srcdir)/mips.dc -SIM_IGEN_CFLAGS = -DWITH_IGEN SIM_IGEN_ALL = tmp-igen BUILT_SRC_FROM_IGEN = \ @@ -132,8 +135,7 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen -I $(srcdir) \ -Werror \ -Wnodiscard \ - -F 32,64,f \ - -M mipsIV \ + @sim_igen_flags@ \ -G gen-direct-access \ -i $(IGEN_INSN) \ -o $(IGEN_DC) \ @@ -172,7 +174,6 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen -SIM_M16_CFLAGS = -DWITH_IGEN SIM_M16_ALL = tmp-igen $(SIM_M16_ALL) BUILT_SRC_FROM_M16 = \ diff --git a/sim/mips/configure b/sim/mips/configure index eb5c30ec6d..2952623989 100755 --- a/sim/mips/configure +++ b/sim/mips/configure @@ -1772,15 +1772,25 @@ fi # Select the sim generator & architecture # sim_gen=NO +sim_igen_flags="-F 32,64,f -M mipsIV" +sim_m16_flags="-F 16 -M mips16" + case "${target}" in # start-sanitize-tx19 - mipstx19*-*-*) sim_gen=M16 ;; +# mipstx19*-*-*) sim_gen=M16 +# sim_igen_flags="-F 32,64,f -M tx19" +# sim_m16_flags="-F 16 -M tx19" +# ;; # end-sanitize-tx19 # start-sanitize-r5900 -# mips64r59*-*-*) sim_gen=IGEN ;; +# mips64r59*-*-*) sim_gen=IGEN +# sim_igen_flags="-F 32,64,f -M r5900" +# ;; # end-sanitize-r5900 # start-sanitize-vr5400 - mips64vr54*-*-*) sim_gen=IGEN ;; + mips64vr54*-*-*) sim_gen=IGEN + sim_igen_flags="-F 32,64,f -M vr5400" + ;; # end-sanitize-vr5400 # mips16*-*-*) sim_gen=M16 ;; *) sim_gen=NO ;; @@ -1788,21 +1798,23 @@ esac + + for ac_hdr in string.h strings.h stdlib.h stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:1796: checking for $ac_hdr" >&5 +echo "configure:1808: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1806: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1818: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then rm -rf conftest* @@ -1829,7 +1841,7 @@ fi done echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6 -echo "configure:1833: checking for fabs in -lm" >&5 +echo "configure:1845: checking for fabs in -lm" >&5 ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1837,7 +1849,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lm $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:1864: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -1878,12 +1890,12 @@ fi for ac_func in aint anint sqrt do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:1882: checking for $ac_func" >&5 +echo "configure:1894: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:1922: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -2113,6 +2125,8 @@ s%@sim_profile@%$sim_profile%g s%@SIMCONF@%$SIMCONF%g s%@SIM_SUBTARGET@%$SIM_SUBTARGET%g s%@sim_gen@%$sim_gen%g +s%@sim_igen_flags@%$sim_igen_flags%g +s%@sim_m16_flags@%$sim_m16_flags%g CEOF EOF diff --git a/sim/mips/configure.in b/sim/mips/configure.in index c98b231a42..49f0af6be8 100644 --- a/sim/mips/configure.in +++ b/sim/mips/configure.in @@ -95,20 +95,32 @@ SIM_AC_OPTION_FLOAT($mips_fpu) # Select the sim generator & architecture # sim_gen=NO +sim_igen_flags="-F 32,64,f -M mipsIV" +sim_m16_flags="-F 16 -M mips16" + case "${target}" in # start-sanitize-tx19 - mipstx19*-*-*) sim_gen=M16 ;; +# mipstx19*-*-*) sim_gen=M16 +# sim_igen_flags="-F 32,64,f -M tx19" +# sim_m16_flags="-F 16 -M tx19" +# ;; # end-sanitize-tx19 # start-sanitize-r5900 -# mips64r59*-*-*) sim_gen=IGEN ;; +# mips64r59*-*-*) sim_gen=IGEN +# sim_igen_flags="-F 32,64,f -M r5900" +# ;; # end-sanitize-r5900 # start-sanitize-vr5400 - mips64vr54*-*-*) sim_gen=IGEN ;; + mips64vr54*-*-*) sim_gen=IGEN + sim_igen_flags="-F 32,64,f -M vr5400" + ;; # end-sanitize-vr5400 # mips16*-*-*) sim_gen=M16 ;; *) sim_gen=NO ;; esac AC_SUBST(sim_gen) +AC_SUBST(sim_igen_flags) +AC_SUBST(sim_m16_flags) AC_CHECK_HEADERS(string.h strings.h stdlib.h stdlib.h) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index fb311f2ffb..b605dbca1d 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -3557,7 +3557,13 @@ decode_coproc(sd,instruction) /*-- instruction simulation -------------------------------------------------*/ -#if defined (WITH_IGEN) +/* When the IGEN simulator is being built, the function below is be + replaced by a generated version. However, WITH_IGEN == 2 indicates + that the fubction below should be compiled but under a different + name (to allow backward compatibility) */ + +#if (WITH_IGEN != 1) +#if (WITH_IGEN > 1) void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); void old_engine_run (sd, next_cpu_nr, siggnal) @@ -3838,6 +3844,8 @@ sim_engine_run (sd, next_cpu_nr, siggnal) #endif /* FASTSIM */ } } +#endif + /* This code copied from gdb's utils.c. Would like to share this code, but don't know of a common place where both could get to it. */ diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen new file mode 100644 index 0000000000..b80960305c --- /dev/null +++ b/sim/mips/m16.igen @@ -0,0 +1,2668 @@ +// +// MIPS Architecture: +// +// CPU Instruction Set (mips16) +// + +// The instructions in this section are ordered according +// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf. + + +// FIXME: Instead of having the code for mips16 instructions here. +// these instructions should instead call the corresponding 32bit +// instruction (or a function implementing that instructions code). + + +// Load and Store Instructions + + +10000,xxx,ddd,55555:RRI:16::LB +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 0; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); + } + } + } +} + + +10100,xxx,ddd,55555:RRI:16::LBU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 0; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); + } + } + } +} + + +10001,xxx,ddd,HHHHH:RRI:16::LH +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 1; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 1) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 1; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); + } + } + } +} + + +10101,xxx,ddd,HHHHH:RRI:16::LHU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 1; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 1) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 1; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); + } + } + } +} + + +10011,xxx,ddd,WWWWW:RRI:16::LW +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 2; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 2; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); + } + } + } +} + + +10110,ddd,VVVVVVVV,P:RI:16::LWPC +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + int offset = (instruction >> 0) & 0xff; + signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 2; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 2; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); + } + } + } +} + + +10010,ddd,VVVVVVVV,s:RI:16::LWSP +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + int offset = (instruction >> 0) & 0xff; + signed_word op1 = 29; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 2; + } + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 2; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); + } + } + } +} + + +10111,xxx,ddd,WWWWW:RRI:16::LWU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 2; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 2; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); + } + } + } +} + + +00111,xxx,ddd,DDDDD:RRI:16::LD +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 3; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 4; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); + GPR[destreg] = memval; + } + } + } +} + + +11111100,ddd,5.RD,P:RI64:16::LDPC +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 3; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 4; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); + GPR[destreg] = memval; + } + } + } +} + + +11111000,ddd,5.RD,s:RI64:16::LDSP +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + signed_word op1 = 29; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 3; + } + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + SignalExceptionAddressLoad(); + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 4; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); + GPR[destreg] = memval; + } + } + } +} + + +11000,xxx,yyy,55555:RRI:16::SB +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 0; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + byte = ((vaddr & mask) ^ (bigend << shift)); + memval = ((unsigned64) op2 << (8 * byte)); + { + StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +11001,xxx,yyy,HHHHH:RRI:16::SH +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 1; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 1) != 0) + SignalExceptionAddressStore(); + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int shift = 1; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + byte = ((vaddr & mask) ^ (bigend << shift)); + memval = ((unsigned64) op2 << (8 * byte)); + { + StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +11011,xxx,yyy,WWWWW:RRI:16::SW +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 2; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + SignalExceptionAddressStore(); + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); + byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); + memval = ((unsigned64) op2 << (8 * byte)); + { + StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +11010,yyy,VVVVVVVV,s:RI:16::SWSP +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op2 = (instruction >> 8) & 0x7; + int offset = (instruction >> 0) & 0xff; + signed_word op1 = 29; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 2; + } + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + SignalExceptionAddressStore(); + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); + byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); + memval = ((unsigned64) op2 << (8 * byte)); + { + StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +01100010,VVVVVVVV,Q,s:I8:16::SWRASP +*mips16: +{ + unsigned32 instruction = instruction_0; + int offset = (instruction >> 0) & 0xff; + signed_word op2 = 31; + signed_word op1 = 29; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 2; + } + op2 = GPR[op2]; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + SignalExceptionAddressStore(); + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = 0x7; + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); + byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); + memval = ((unsigned64) op2 << (8 * byte)); + { + StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +01111,xxx,yyy,DDDDD:RRI:16::SD +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 3; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + SignalExceptionAddressStore(); + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + memval = op2; + { + StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +11111001,yyy,5.RD,s:RI64:16::SDSP +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op2 = (instruction >> 5) & 0x7; + int offset = (instruction >> 0) & 0x1f; + signed_word op1 = 29; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 3; + } + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + SignalExceptionAddressStore(); + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + memval = op2; + { + StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +11111010,CCCCCCCC,s,Q:I64:16::SDRASP +*mips16: +{ + unsigned32 instruction = instruction_0; + int offset = (instruction >> 0) & 0xff; + signed_word op1 = 29; + signed_word op2 = 31; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + offset <<= 3; + } + op1 = GPR[op1]; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + address_word vaddr = ((unsigned64)op1 + offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + SignalExceptionAddressStore(); + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + memval = op2; + { + StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +// ALU Immediate Instructions + + +01101,ddd,UUUUUUUU,Z:RI:16::LI +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + int op2 = (instruction >> 0) & 0xff; + signed_word op1 = 0; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + have_extendval = 0; + } + else + { + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if (destreg != 0) + GPR[destreg] = (op1 | op2); + } +} + + +01000,xxx,ddd,04444:RRI_A:16::ADDIU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int op2 = (instruction >> 0) & 0xf; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); + if (op2 >= 0x4000) + op2 -= 0x8000; + have_extendval = 0; + } + else + { + if (op2 >= 0x8) + op2 -= 0x10; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 + op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +01001,www,kkkkkkkk:RI:16::ADDIU8 +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg; + int op2 = (instruction >> 0) & 0xff; + if (op1 < 2) + op1 += 16; + destreg = op1; + op1 = GPR[op1]; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + if (op2 >= 0x80) + op2 -= 0x100; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 + op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +01100011,KKKKKKKK,S:I8:16::ADJSP +*mips16: +{ + unsigned32 instruction = instruction_0; + int op2 = (instruction >> 0) & 0xff; + signed_word op1 = 29; + int destreg; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + if (op2 >= 0x80) + op2 -= 0x100; + op2 <<= 3; + } + destreg = op1; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 + op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + int op2 = (instruction >> 0) & 0xff; + signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + op2 <<= 2; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 + op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + int op2 = (instruction >> 0) & 0xff; + signed_word op1 = 29; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + op2 <<= 2; + } + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 + op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +01000,xxx,ddd,14444:RRI_A:16::DADDIU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = (instruction >> 5) & 0x7; + int op2 = (instruction >> 0) & 0xf; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); + if (op2 >= 0x4000) + op2 -= 0x8000; + have_extendval = 0; + } + else + { + if (op2 >= 0x8) + op2 -= 0x10; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 temp = (unsigned64)(op1 + op2); + word64 tempS = (word64)temp; + GPR[destreg] = (unsigned64)temp; + } +} + + +11111101,www,jjjjj:RI64:16::DADDIU5 +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 5) & 0x7; + int destreg; + int op2 = (instruction >> 0) & 0x1f; + if (op1 < 2) + op1 += 16; + destreg = op1; + op1 = GPR[op1]; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + if (op2 >= 0x10) + op2 -= 0x20; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 temp = (unsigned64)(op1 + op2); + word64 tempS = (word64)temp; + GPR[destreg] = (unsigned64)temp; + } +} + + +11111011,KKKKKKKK,S:I64:16::DADJSP +*mips16: +{ + unsigned32 instruction = instruction_0; + int op2 = (instruction >> 0) & 0xff; + signed_word op1 = 29; + int destreg; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + if (op2 >= 0x80) + op2 -= 0x100; + op2 <<= 3; + } + destreg = op1; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 temp = (unsigned64)(op1 + op2); + word64 tempS = (word64)temp; + GPR[destreg] = (unsigned64)temp; + } +} + + +11111110,ddd,EEEEE,P:RI64:16::DADDIUPC +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 5) & 0x7; + int op2 = (instruction >> 0) & 0x1f; + signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + op2 <<= 2; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 temp = (unsigned64)(op1 + op2); + word64 tempS = (word64)temp; + GPR[destreg] = (unsigned64)temp; + } +} + + +11111111,ddd,EEEEE,s:RI64:16::DADDIUSP +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 5) & 0x7; + int op2 = (instruction >> 0) & 0x1f; + signed_word op1 = 29; + if (destreg < 2) + destreg += 16; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + op2 <<= 2; + } + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 temp = (unsigned64)(op1 + op2); + word64 tempS = (word64)temp; + GPR[destreg] = (unsigned64)temp; + } +} + + +01010,xxx,88888888,T:RI:16::SLTI +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int op2 = (instruction >> 0) & 0xff; + int destreg = 24; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if ((word64)op1 < (word64)op2) + GPR[destreg] = 1; + else + GPR[destreg] = 0; + } +} + + +01011,xxx,88888888,T:RI:16::SLTIU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int op2 = (instruction >> 0) & 0xff; + int destreg = 24; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (op2 >= 0x8000) + op2 -= 0x10000; + have_extendval = 0; + } + else + { + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if ((unsigned64)op1 < (unsigned64)op2) + GPR[destreg] = 1; + else + GPR[destreg] = 0; + } +} + + +11101,xxx,yyy,01010,T:RR:16::CMP +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg = 24; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = (op1 ^ op2); + } +} + + +01110,xxx,UUUUUUUU,T:RI:16::CMPI +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int op2 = (instruction >> 0) & 0xff; + int destreg = 24; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + { + op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + have_extendval = 0; + } + else + { + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = (op1 ^ op2); + } +} + + +// Two/Three Operand, Register-Type + + +11100,xxx,yyy,ddd,01:RRR:16::ADDU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg = (instruction >> 2) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 + op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +11100,xxx,yyy,ddd,11:RRR:16::SUBU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg = (instruction >> 2) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 - op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +11100,xxx,yyy,ddd,00:RRR:16::DADDU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg = (instruction >> 2) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 temp = (unsigned64)(op1 + op2); + word64 tempS = (word64)temp; + GPR[destreg] = (unsigned64)temp; + } +} + + +11100,xxx,yyy,ddd,10:RRR:16::DSUBU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg = (instruction >> 2) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (destreg < 2) + destreg += 16; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 temp = (unsigned64)(op1 - op2); + word64 tempS = (word64)temp; + GPR[destreg] = (unsigned64)temp; + } +} + + +11101,xxx,yyy,00010,T:RR:16::SLT +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg = 24; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if ((word64)op1 < (word64)op2) + GPR[destreg] = 1; + else + GPR[destreg] = 0; + } +} + + +11101,xxx,yyy,00011,T:RR:16::SLTU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg = 24; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if ((unsigned64)op1 < (unsigned64)op2) + GPR[destreg] = 1; + else + GPR[destreg] = 0; + } +} + + +11101,ddd,yyy,01011,Z:RR:16::NEG +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + signed_word op1 = 0; + if (destreg < 2) + destreg += 16; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int temp = (unsigned int)(op1 - op2); + signed int tempS = (signed int)temp; + GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); + } +} + + +11101,www,yyy,01100:RR:16::AND +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + destreg = op1; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = (op1 & op2); + } +} + + +11101,www,yyy,01101:RR:16::OR +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + destreg = op1; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if (destreg != 0) + GPR[destreg] = (op1 | op2); + } +} + + +11101,www,yyy,01110:RR:16::XOR +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + destreg = op1; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = (op1 ^ op2); + } +} + + +11101,ddd,yyy,01111,Z:RR:16::NOT +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + signed_word op1 = 0; + if (destreg < 2) + destreg += 16; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if (destreg != 0) + GPR[destreg] = ~(op1 | op2); + } +} + + +01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32 +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 5) & 0x7; + signed_word op1 = (instruction >> 0) & 0x1f; + signed_word op2 = 0; + if (destreg < 2) + destreg += 16; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if (destreg != 0) + GPR[destreg] = (op1 | op2); + } +} + + +01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 3) & 0x1f; + signed_word op1 = (instruction >> 0) & 0x7; + signed_word op2 = 0; + destreg = (destreg >> 2) | ((destreg & 3) << 3); + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + if (destreg != 0) + GPR[destreg] = (op1 | op2); + } +} + + +00110,ddd,yyy,sss,00:ISHIFT:16::SLL +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int op1 = (instruction >> 2) & 0x7; + if (destreg < 2) + destreg += 16; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + op1 = (extendval >> 6) & 0x1f; + have_extendval = 0; + } + else + { + if (op1 == 0) + op1 = 8; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = ((unsigned64)op2 << op1); + GPR[destreg] = SIGNEXTEND(GPR[destreg],32); + } +} + + +00110,ddd,yyy,sss,10:ISHIFT:16::SRL +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int op1 = (instruction >> 2) & 0x7; + if (destreg < 2) + destreg += 16; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + op1 = (extendval >> 6) & 0x1f; + have_extendval = 0; + } + else + { + if (op1 == 0) + op1 = 8; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); + GPR[destreg] = SIGNEXTEND(GPR[destreg],32); + } +} + + +00110,ddd,yyy,sss,11:ISHIFT:16::SRA +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int op1 = (instruction >> 2) & 0x7; + if (destreg < 2) + destreg += 16; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + op1 = (extendval >> 6) & 0x1f; + have_extendval = 0; + } + else + { + if (op1 == 0) + op1 = 8; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int highbit = (unsigned int)1 << 31; + GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); + GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); + GPR[destreg] = SIGNEXTEND(GPR[destreg],32); + } +} + + +11101,xxx,vvv,00100:RR:16::SLLV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + op1 &= 0x1F; + GPR[destreg] = ((unsigned64)op2 << op1); + GPR[destreg] = SIGNEXTEND(GPR[destreg],32); + } +} + + +11101,xxx,vvv,00110:RR:16::SRLV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + op1 &= 0x1F; + GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); + GPR[destreg] = SIGNEXTEND(GPR[destreg],32); + } +} + + +11101,xxx,vvv,00111:RR:16::SRAV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned int highbit = (unsigned int)1 << 31; + op1 &= 0x1F; + GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); + GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); + GPR[destreg] = SIGNEXTEND(GPR[destreg],32); + } +} + + +00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int op1 = (instruction >> 2) & 0x7; + if (destreg < 2) + destreg += 16; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + { + op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); + have_extendval = 0; + } + else + { + if (op1 == 0) + op1 = 8; + } + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = ((unsigned64)op2 << op1); + } +} + + +11101,XXX,vvv,01000:RR:16::DSRL +*mips16: +{ + unsigned32 instruction = instruction_0; + int op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (have_extendval) + { + op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); + have_extendval = 0; + } + else + { + if (op1 == 0) + op1 = 8; + } + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = ((unsigned64)(op2) >> op1); + } +} + + +11101,xxx,vvv,10011:RR:16::DSRA +*mips16: +{ + unsigned32 instruction = instruction_0; + int op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (have_extendval) + { + op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); + have_extendval = 0; + } + else + { + if (op1 == 0) + op1 = 8; + } + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 highbit = (unsigned64)1 << 63; + GPR[destreg] = ((unsigned64)(op2) >> op1); + GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); + } +} + + +11101,xxx,vvv,10100:RR:16::DSLLV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + op1 &= 0x3F; + GPR[destreg] = ((unsigned64)op2 << op1); + } +} + + +11101,xxx,vvv,10110:RR:16::DSRLV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + op1 &= 0x3F; + GPR[destreg] = ((unsigned64)(op2) >> op1); + } +} + + +11101,xxx,vvv,10111:RR:16::DSRAV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + int destreg; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + destreg = op2; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + unsigned64 highbit = (unsigned64)1 << 63; + op1 &= 0x3F; + GPR[destreg] = ((unsigned64)(op2) >> op1); + GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); + } +} + + +// Multiply /Divide Instructions + + +11101,xxx,yyy,11000:RR:16::MULT +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Multiplication"); + { + unsigned64 temp = ((word64) op1 * (word64) op2); + LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); + HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); + } + } +} + + +11101,xxx,yyy,11001:RR:16::MULTU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Multiplication"); + { + unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff)); + LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); + HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); + } + } +} + + +11101,xxx,yyy,11010:RR:16::DIV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Division"); + { + int d1 = op1; + int d2 = op2; + if (d2 == 0) + { + LO = SIGNEXTEND(0x80000000,32); + HI = SIGNEXTEND(0,32); + } + else if (d2 == -1 && d1 == 0x80000000) + { + LO = SIGNEXTEND(0x80000000,32); + HI = SIGNEXTEND(0,32); + } + else + { + LO = SIGNEXTEND((d1 / d2),32); + HI = SIGNEXTEND((d1 % d2),32); + } + } + } +} + + +11101,xxx,yyy,11011:RR:16::DIVU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Division"); + { + unsigned int d1 = op1; + unsigned int d2 = op2; + if (d2 == 0) + { + LO = SIGNEXTEND(0x80000000,32); + HI = SIGNEXTEND(0,32); + } + else if (d2 == -1 && d1 == 0x80000000) + { + LO = SIGNEXTEND(0x80000000,32); + HI = SIGNEXTEND(0,32); + } + else + { + LO = SIGNEXTEND((d1 / d2),32); + HI = SIGNEXTEND((d1 % d2),32); + } + } + } +} + + +11101,ddd,00010000:RR:16::MFHI +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + if (destreg < 2) + destreg += 16; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = HI; + HIACCESS = 3; /* 3rd instruction will be safe */ + } +} + + +11101,ddd,00010010:RR:16::MFLO +*mips16: +{ + unsigned32 instruction = instruction_0; + int destreg = (instruction >> 8) & 0x7; + if (destreg < 2) + destreg += 16; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = LO; + LOACCESS = 3; /* 3rd instruction will be safe */ + } +} + + +11101,xxx,yyy,11100:RR:16::DMULT +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Multiplication"); + { + unsigned64 mid; + unsigned64 midhi; + unsigned64 temp; + int sign = 0; + if (op1 < 0) { op1 = - op1; ++sign; } + if (op2 < 0) { op2 = - op2; ++sign; } + LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); + HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); + mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); + midhi = SET64HI(VL4_8(mid)); + temp = (LO + midhi); + if ((temp == midhi) ? (LO != 0) : (temp < midhi)) + HI += 1; + HI += VH4_8(mid); + mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); + midhi = SET64HI(VL4_8(mid)); + LO = (temp + midhi); + if ((LO == midhi) ? (temp != 0) : (LO < midhi)) + HI += 1; + HI += VH4_8(mid); + if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; } + } + } +} + + +11101,xxx,yyy,11101:RR:16::DMULTU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Multiplication"); + { + unsigned64 mid; + unsigned64 midhi; + unsigned64 temp; + LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); + HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); + mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); + midhi = SET64HI(VL4_8(mid)); + temp = (LO + midhi); + if ((temp == midhi) ? (LO != 0) : (temp < midhi)) + HI += 1; + HI += VH4_8(mid); + mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); + midhi = SET64HI(VL4_8(mid)); + LO = (temp + midhi); + if ((LO == midhi) ? (temp != 0) : (LO < midhi)) + HI += 1; + HI += VH4_8(mid); + } + } +} + + +11101,xxx,yyy,11110:RR:16::DDIV +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Division"); + { + word64 d1 = op1; + word64 d2 = op2; + if (d2 == 0) + { + LO = SIGNED64 (0x8000000000000000); + HI = 0; + } + else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) + { + LO = SIGNED64 (0x8000000000000000); + HI = 0; + } + else + { + LO = (d1 / d2); + HI = (d1 % d2); + } + } + } +} + + +11101,xxx,yyy,11111:RR:16::DDIVU +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + signed_word op2 = (instruction >> 5) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (op2 < 2) + op2 += 16; + op2 = GPR[op2]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + CHECKHILO("Division"); + { + unsigned64 d1 = op1; + unsigned64 d2 = op2; + if (d2 == 0) + { + LO = SIGNED64 (0x8000000000000000); + HI = 0; + } + else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) + { + LO = SIGNED64 (0x8000000000000000); + HI = 0; + } + else + { + LO = (d1 / d2); + HI = (d1 % d2); + } + } + } +} + + +// Jump and Branch Instructions + + +// JALX +// JAL +00011,aaaaaaaaaaa:I:16::JAL +*mips16: +{ + unsigned32 instruction = instruction_0; + unsigned_word op1 = (instruction >> 0) & 0x7ff; + { + address_word paddr; + int uncached; + if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL)) + { + unsigned64 memval; + unsigned int reverse = (ReverseEndian ? 3 : 0); + unsigned int bigend = (BigEndianCPU ? 3 : 0); + unsigned int byte; + paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1))); + LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL); + byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1)); + memval = (memval >> (8 * byte)) & 0xffff; + op1 = (((op1 & 0x1f) << 23) + | ((op1 & 0x3e0) << 13) + | (memval << 2)); + if ((instruction & 0x400) == 0) + op1 |= 1; + PC += 2; + } + } + op1 |= PC & ~ (unsigned64) 0x0fffffff; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + int destreg = 31; + GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ + /* NOTE: ??? Gdb gets confused if the PC is sign-extended, + so we just truncate it to 32 bits here. */ + op1 = VL4_8(op1); + /* NOTE: The jump occurs AFTER the next instruction has been executed */ + DELAY_SLOT op1; + JALDELAYSLOT(); + } +} + + +11101,xxx,00000000:RR:16::JR +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + /* NOTE: ??? Gdb gets confused if the PC is sign-extended, + so we just truncate it to 32 bits here. */ + op1 = VL4_8(op1); + /* NOTE: The jump occurs AFTER the next instruction has been executed */ + DELAY_SLOT op1; + DELAYSLOT(); + } +} + + +1110100000100000,r:RR:16::JRRA +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = 31; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + /* NOTE: ??? Gdb gets confused if the PC is sign-extended, + so we just truncate it to 32 bits here. */ + op1 = VL4_8(op1); + /* NOTE: The jump occurs AFTER the next instruction has been executed */ + DELAY_SLOT op1; + DELAYSLOT(); + } +} + + +11101,xxx,01000000,R:RR:16::JALR +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int destreg = 31; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ + /* NOTE: ??? Gdb gets confused if the PC is sign-extended, + so we just truncate it to 32 bits here. */ + op1 = VL4_8(op1); + /* NOTE: The jump occurs AFTER the next instruction has been executed */ + DELAY_SLOT op1; + DELAYSLOT(); + } +} + + +00100,xxx,pppppppp,z:RI:16::BEQZ +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int offset = (instruction >> 0) & 0xff; + signed_word op2 = 0; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + if (offset >= 0x80) + offset -= 0x100; + } + offset *= 2; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + int condition = (op1 == op2); + if (condition) + PC = PC + offset; + } +} + + +00101,xxx,pppppppp,z:RI:16::BNEZ +*mips16: +{ + unsigned32 instruction = instruction_0; + signed_word op1 = (instruction >> 8) & 0x7; + int offset = (instruction >> 0) & 0xff; + signed_word op2 = 0; + if (op1 < 2) + op1 += 16; + op1 = GPR[op1]; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + if (offset >= 0x80) + offset -= 0x100; + } + offset *= 2; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + int condition = (op1 != op2); + if (condition) + PC = PC + offset; + } +} + + +01100000,pppppppp,t,z:I8:16::BTEQZ +*mips16: +{ + unsigned32 instruction = instruction_0; + int offset = (instruction >> 0) & 0xff; + signed_word op1 = 24; + signed_word op2 = 0; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + if (offset >= 0x80) + offset -= 0x100; + } + offset *= 2; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + int condition = (op1 == op2); + if (condition) + PC = PC + offset; + } +} + + +01100001,pppppppp,t,z:I8:16::BTNEZ +*mips16: +{ + unsigned32 instruction = instruction_0; + int offset = (instruction >> 0) & 0xff; + signed_word op1 = 24; + signed_word op2 = 0; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + if (offset >= 0x80) + offset -= 0x100; + } + offset *= 2; + op1 = GPR[op1]; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + int condition = (op1 != op2); + if (condition) + PC = PC + offset; + } +} + + +00010,qqqqqqqqqqq,z,Z:I:16::B +*mips16: +{ + unsigned32 instruction = instruction_0; + int offset = (instruction >> 0) & 0x7ff; + signed_word op2 = 0; + signed_word op1 = 0; + if (have_extendval) + { + offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); + if (offset >= 0x8000) + offset -= 0x10000; + have_extendval = 0; + } + else + { + if (offset >= 0x400) + offset -= 0x800; + } + offset *= 2; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + int condition = (op1 == op2); + if (condition) + PC = PC + offset; + } +} + + +// Special Instructions + + +// See the front of the mips16 doc +11110,eeeeeeeeeee:I:16::EXTEND +*mips16: +{ + unsigned32 instruction = instruction_0; + int ext = (instruction >> 0) & 0x7ff; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + extendval = ext; + have_extendval = 1; + } +} + + +01100,******,00101:RR:16::BREAK +*mips16: +{ + unsigned32 instruction = instruction_0; + if (have_extendval) + SignalException (ReservedInstruction, instruction); + { + SignalException(BreakPoint,instruction); + } +} + diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 692900a57d..96743befb1 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -4975,5163 +4975,12 @@ // end-sanitize-r5900 -// -// MIPS Architecture: -// -// CPU Instruction Set (mips16) -// - -// The instructions in this section are ordered according -// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf. - - -// FIXME: Instead of having the code for mips16 instructions here. -// these instructions should instead call the corresponding 32bit -// instruction (or a function implementing that instructions code). - - -// Load and Store Instructions - - -10000,xxx,ddd,55555:RRI:16::LB -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 0; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); - } - } - } -} - - -10100,xxx,ddd,55555:RRI:16::LBU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 0; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); - } - } - } -} - - -10001,xxx,ddd,HHHHH:RRI:16::LH -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 1; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 1) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 1; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); - } - } - } -} - - -10101,xxx,ddd,HHHHH:RRI:16::LHU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 1; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 1) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 1; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); - } - } - } -} - - -10011,xxx,ddd,WWWWW:RRI:16::LW -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 2; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); - } - } - } -} - - -10110,ddd,VVVVVVVV,P:RI:16::LWPC -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - int offset = (instruction >> 0) & 0xff; - signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 2; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); - } - } - } -} - - -10010,ddd,VVVVVVVV,s:RI:16::LWSP -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - int offset = (instruction >> 0) & 0xff; - signed_word op1 = 29; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 2; - } - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); - } - } - } -} - - -10111,xxx,ddd,WWWWW:RRI:16::LWU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 2; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); - } - } - } -} - - -00111,xxx,ddd,DDDDD:RRI:16::LD -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 3; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 4; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - GPR[destreg] = memval; - } - } - } -} - - -11111100,ddd,5.RD,P:RI64:16::LDPC -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 3; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 4; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - GPR[destreg] = memval; - } - } - } -} - - -11111000,ddd,5.RD,s:RI64:16::LDSP -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - signed_word op1 = 29; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 3; - } - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 4; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - GPR[destreg] = memval; - } - } - } -} - - -11000,xxx,yyy,55555:RRI:16::SB -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 0; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - byte = ((vaddr & mask) ^ (bigend << shift)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -11001,xxx,yyy,HHHHH:RRI:16::SH -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 1; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 1) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 1; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - byte = ((vaddr & mask) ^ (bigend << shift)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -11011,xxx,yyy,WWWWW:RRI:16::SW -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 2; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -11010,yyy,VVVVVVVV,s:RI:16::SWSP -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op2 = (instruction >> 8) & 0x7; - int offset = (instruction >> 0) & 0xff; - signed_word op1 = 29; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 2; - } - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -01100010,VVVVVVVV,Q,s:I8:16::SWRASP -*mips16: -{ - unsigned32 instruction = instruction_0; - int offset = (instruction >> 0) & 0xff; - signed_word op2 = 31; - signed_word op1 = 29; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 2; - } - op2 = GPR[op2]; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -01111,xxx,yyy,DDDDD:RRI:16::SD -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 3; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = op2; - { - StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -11111001,yyy,5.RD,s:RI64:16::SDSP -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op2 = (instruction >> 5) & 0x7; - int offset = (instruction >> 0) & 0x1f; - signed_word op1 = 29; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 3; - } - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = op2; - { - StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -11111010,CCCCCCCC,s,Q:I64:16::SDRASP -*mips16: -{ - unsigned32 instruction = instruction_0; - int offset = (instruction >> 0) & 0xff; - signed_word op1 = 29; - signed_word op2 = 31; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - offset <<= 3; - } - op1 = GPR[op1]; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = op2; - { - StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - - -// ALU Immediate Instructions - - -01101,ddd,UUUUUUUU,Z:RI:16::LI -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - int op2 = (instruction >> 0) & 0xff; - signed_word op1 = 0; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - have_extendval = 0; - } - else - { - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if (destreg != 0) - GPR[destreg] = (op1 | op2); - } -} - - -01000,xxx,ddd,04444:RRI_A:16::ADDIU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int op2 = (instruction >> 0) & 0xf; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); - if (op2 >= 0x4000) - op2 -= 0x8000; - have_extendval = 0; - } - else - { - if (op2 >= 0x8) - op2 -= 0x10; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 + op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -01001,www,kkkkkkkk:RI:16::ADDIU8 -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg; - int op2 = (instruction >> 0) & 0xff; - if (op1 < 2) - op1 += 16; - destreg = op1; - op1 = GPR[op1]; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - if (op2 >= 0x80) - op2 -= 0x100; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 + op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -01100011,KKKKKKKK,S:I8:16::ADJSP -*mips16: -{ - unsigned32 instruction = instruction_0; - int op2 = (instruction >> 0) & 0xff; - signed_word op1 = 29; - int destreg; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - if (op2 >= 0x80) - op2 -= 0x100; - op2 <<= 3; - } - destreg = op1; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 + op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - int op2 = (instruction >> 0) & 0xff; - signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - op2 <<= 2; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 + op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - int op2 = (instruction >> 0) & 0xff; - signed_word op1 = 29; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - op2 <<= 2; - } - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 + op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -01000,xxx,ddd,14444:RRI_A:16::DADDIU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = (instruction >> 5) & 0x7; - int op2 = (instruction >> 0) & 0xf; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); - if (op2 >= 0x4000) - op2 -= 0x8000; - have_extendval = 0; - } - else - { - if (op2 >= 0x8) - op2 -= 0x10; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 temp = (unsigned64)(op1 + op2); - word64 tempS = (word64)temp; - GPR[destreg] = (unsigned64)temp; - } -} - - -11111101,www,jjjjj:RI64:16::DADDIU5 -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 5) & 0x7; - int destreg; - int op2 = (instruction >> 0) & 0x1f; - if (op1 < 2) - op1 += 16; - destreg = op1; - op1 = GPR[op1]; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - if (op2 >= 0x10) - op2 -= 0x20; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 temp = (unsigned64)(op1 + op2); - word64 tempS = (word64)temp; - GPR[destreg] = (unsigned64)temp; - } -} - - -11111011,KKKKKKKK,S:I64:16::DADJSP -*mips16: -{ - unsigned32 instruction = instruction_0; - int op2 = (instruction >> 0) & 0xff; - signed_word op1 = 29; - int destreg; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - if (op2 >= 0x80) - op2 -= 0x100; - op2 <<= 3; - } - destreg = op1; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 temp = (unsigned64)(op1 + op2); - word64 tempS = (word64)temp; - GPR[destreg] = (unsigned64)temp; - } -} - - -11111110,ddd,EEEEE,P:RI64:16::DADDIUPC -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 5) & 0x7; - int op2 = (instruction >> 0) & 0x1f; - signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - op2 <<= 2; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 temp = (unsigned64)(op1 + op2); - word64 tempS = (word64)temp; - GPR[destreg] = (unsigned64)temp; - } -} - - -11111111,ddd,EEEEE,s:RI64:16::DADDIUSP -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 5) & 0x7; - int op2 = (instruction >> 0) & 0x1f; - signed_word op1 = 29; - if (destreg < 2) - destreg += 16; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - op2 <<= 2; - } - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 temp = (unsigned64)(op1 + op2); - word64 tempS = (word64)temp; - GPR[destreg] = (unsigned64)temp; - } -} - - -01010,xxx,88888888,T:RI:16::SLTI -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int op2 = (instruction >> 0) & 0xff; - int destreg = 24; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if ((word64)op1 < (word64)op2) - GPR[destreg] = 1; - else - GPR[destreg] = 0; - } -} - - -01011,xxx,88888888,T:RI:16::SLTIU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int op2 = (instruction >> 0) & 0xff; - int destreg = 24; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (op2 >= 0x8000) - op2 -= 0x10000; - have_extendval = 0; - } - else - { - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if ((unsigned64)op1 < (unsigned64)op2) - GPR[destreg] = 1; - else - GPR[destreg] = 0; - } -} - - -11101,xxx,yyy,01010,T:RR:16::CMP -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg = 24; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = (op1 ^ op2); - } -} - - -01110,xxx,UUUUUUUU,T:RI:16::CMPI -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int op2 = (instruction >> 0) & 0xff; - int destreg = 24; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - { - op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - have_extendval = 0; - } - else - { - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = (op1 ^ op2); - } -} - - -// Two/Three Operand, Register-Type - - -11100,xxx,yyy,ddd,01:RRR:16::ADDU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg = (instruction >> 2) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 + op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -11100,xxx,yyy,ddd,11:RRR:16::SUBU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg = (instruction >> 2) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 - op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -11100,xxx,yyy,ddd,00:RRR:16::DADDU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg = (instruction >> 2) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 temp = (unsigned64)(op1 + op2); - word64 tempS = (word64)temp; - GPR[destreg] = (unsigned64)temp; - } -} - - -11100,xxx,yyy,ddd,10:RRR:16::DSUBU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg = (instruction >> 2) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (destreg < 2) - destreg += 16; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 temp = (unsigned64)(op1 - op2); - word64 tempS = (word64)temp; - GPR[destreg] = (unsigned64)temp; - } -} - - -11101,xxx,yyy,00010,T:RR:16::SLT -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg = 24; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if ((word64)op1 < (word64)op2) - GPR[destreg] = 1; - else - GPR[destreg] = 0; - } -} - - -11101,xxx,yyy,00011,T:RR:16::SLTU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg = 24; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if ((unsigned64)op1 < (unsigned64)op2) - GPR[destreg] = 1; - else - GPR[destreg] = 0; - } -} - - -11101,ddd,yyy,01011,Z:RR:16::NEG -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - signed_word op1 = 0; - if (destreg < 2) - destreg += 16; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int temp = (unsigned int)(op1 - op2); - signed int tempS = (signed int)temp; - GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); - } -} - - -11101,www,yyy,01100:RR:16::AND -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - destreg = op1; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = (op1 & op2); - } -} - - -11101,www,yyy,01101:RR:16::OR -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - destreg = op1; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if (destreg != 0) - GPR[destreg] = (op1 | op2); - } -} - - -11101,www,yyy,01110:RR:16::XOR -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - destreg = op1; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = (op1 ^ op2); - } -} - - -11101,ddd,yyy,01111,Z:RR:16::NOT -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - signed_word op1 = 0; - if (destreg < 2) - destreg += 16; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if (destreg != 0) - GPR[destreg] = ~(op1 | op2); - } -} - - -01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32 -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 5) & 0x7; - signed_word op1 = (instruction >> 0) & 0x1f; - signed_word op2 = 0; - if (destreg < 2) - destreg += 16; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if (destreg != 0) - GPR[destreg] = (op1 | op2); - } -} - - -01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 3) & 0x1f; - signed_word op1 = (instruction >> 0) & 0x7; - signed_word op2 = 0; - destreg = (destreg >> 2) | ((destreg & 3) << 3); - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - if (destreg != 0) - GPR[destreg] = (op1 | op2); - } -} - - -00110,ddd,yyy,sss,00:ISHIFT:16::SLL -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int op1 = (instruction >> 2) & 0x7; - if (destreg < 2) - destreg += 16; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - op1 = (extendval >> 6) & 0x1f; - have_extendval = 0; - } - else - { - if (op1 == 0) - op1 = 8; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = ((unsigned64)op2 << op1); - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } -} - - -00110,ddd,yyy,sss,10:ISHIFT:16::SRL -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int op1 = (instruction >> 2) & 0x7; - if (destreg < 2) - destreg += 16; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - op1 = (extendval >> 6) & 0x1f; - have_extendval = 0; - } - else - { - if (op1 == 0) - op1 = 8; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } -} - - -00110,ddd,yyy,sss,11:ISHIFT:16::SRA -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int op1 = (instruction >> 2) & 0x7; - if (destreg < 2) - destreg += 16; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - op1 = (extendval >> 6) & 0x1f; - have_extendval = 0; - } - else - { - if (op1 == 0) - op1 = 8; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int highbit = (unsigned int)1 << 31; - GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); - GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } -} - - -11101,xxx,vvv,00100:RR:16::SLLV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - op1 &= 0x1F; - GPR[destreg] = ((unsigned64)op2 << op1); - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } -} - - -11101,xxx,vvv,00110:RR:16::SRLV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - op1 &= 0x1F; - GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } -} - - -11101,xxx,vvv,00111:RR:16::SRAV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned int highbit = (unsigned int)1 << 31; - op1 &= 0x1F; - GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); - GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } -} - - -00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int op1 = (instruction >> 2) & 0x7; - if (destreg < 2) - destreg += 16; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - { - op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); - have_extendval = 0; - } - else - { - if (op1 == 0) - op1 = 8; - } - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = ((unsigned64)op2 << op1); - } -} - - -11101,XXX,vvv,01000:RR:16::DSRL -*mips16: -{ - unsigned32 instruction = instruction_0; - int op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (have_extendval) - { - op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); - have_extendval = 0; - } - else - { - if (op1 == 0) - op1 = 8; - } - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = ((unsigned64)(op2) >> op1); - } -} - - -11101,xxx,vvv,10011:RR:16::DSRA -*mips16: -{ - unsigned32 instruction = instruction_0; - int op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (have_extendval) - { - op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); - have_extendval = 0; - } - else - { - if (op1 == 0) - op1 = 8; - } - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 highbit = (unsigned64)1 << 63; - GPR[destreg] = ((unsigned64)(op2) >> op1); - GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); - } -} - - -11101,xxx,vvv,10100:RR:16::DSLLV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - op1 &= 0x3F; - GPR[destreg] = ((unsigned64)op2 << op1); - } -} - - -11101,xxx,vvv,10110:RR:16::DSRLV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - op1 &= 0x3F; - GPR[destreg] = ((unsigned64)(op2) >> op1); - } -} - - -11101,xxx,vvv,10111:RR:16::DSRAV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - int destreg; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - destreg = op2; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - unsigned64 highbit = (unsigned64)1 << 63; - op1 &= 0x3F; - GPR[destreg] = ((unsigned64)(op2) >> op1); - GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); - } -} - - -// Multiply /Divide Instructions - - -11101,xxx,yyy,11000:RR:16::MULT -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Multiplication"); - { - unsigned64 temp = ((word64) op1 * (word64) op2); - LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); - HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); - } - } -} - - -11101,xxx,yyy,11001:RR:16::MULTU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Multiplication"); - { - unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff)); - LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); - HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); - } - } -} - - -11101,xxx,yyy,11010:RR:16::DIV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Division"); - { - int d1 = op1; - int d2 = op2; - if (d2 == 0) - { - LO = SIGNEXTEND(0x80000000,32); - HI = SIGNEXTEND(0,32); - } - else if (d2 == -1 && d1 == 0x80000000) - { - LO = SIGNEXTEND(0x80000000,32); - HI = SIGNEXTEND(0,32); - } - else - { - LO = SIGNEXTEND((d1 / d2),32); - HI = SIGNEXTEND((d1 % d2),32); - } - } - } -} - - -11101,xxx,yyy,11011:RR:16::DIVU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Division"); - { - unsigned int d1 = op1; - unsigned int d2 = op2; - if (d2 == 0) - { - LO = SIGNEXTEND(0x80000000,32); - HI = SIGNEXTEND(0,32); - } - else if (d2 == -1 && d1 == 0x80000000) - { - LO = SIGNEXTEND(0x80000000,32); - HI = SIGNEXTEND(0,32); - } - else - { - LO = SIGNEXTEND((d1 / d2),32); - HI = SIGNEXTEND((d1 % d2),32); - } - } - } -} - - -11101,ddd,00010000:RR:16::MFHI -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - if (destreg < 2) - destreg += 16; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = HI; - HIACCESS = 3; /* 3rd instruction will be safe */ - } -} - - -11101,ddd,00010010:RR:16::MFLO -*mips16: -{ - unsigned32 instruction = instruction_0; - int destreg = (instruction >> 8) & 0x7; - if (destreg < 2) - destreg += 16; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = LO; - LOACCESS = 3; /* 3rd instruction will be safe */ - } -} - - -11101,xxx,yyy,11100:RR:16::DMULT -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Multiplication"); - { - unsigned64 mid; - unsigned64 midhi; - unsigned64 temp; - int sign = 0; - if (op1 < 0) { op1 = - op1; ++sign; } - if (op2 < 0) { op2 = - op2; ++sign; } - LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); - HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); - mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); - midhi = SET64HI(VL4_8(mid)); - temp = (LO + midhi); - if ((temp == midhi) ? (LO != 0) : (temp < midhi)) - HI += 1; - HI += VH4_8(mid); - mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); - midhi = SET64HI(VL4_8(mid)); - LO = (temp + midhi); - if ((LO == midhi) ? (temp != 0) : (LO < midhi)) - HI += 1; - HI += VH4_8(mid); - if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; } - } - } -} - - -11101,xxx,yyy,11101:RR:16::DMULTU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Multiplication"); - { - unsigned64 mid; - unsigned64 midhi; - unsigned64 temp; - LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); - HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); - mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); - midhi = SET64HI(VL4_8(mid)); - temp = (LO + midhi); - if ((temp == midhi) ? (LO != 0) : (temp < midhi)) - HI += 1; - HI += VH4_8(mid); - mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); - midhi = SET64HI(VL4_8(mid)); - LO = (temp + midhi); - if ((LO == midhi) ? (temp != 0) : (LO < midhi)) - HI += 1; - HI += VH4_8(mid); - } - } -} - - -11101,xxx,yyy,11110:RR:16::DDIV -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Division"); - { - word64 d1 = op1; - word64 d2 = op2; - if (d2 == 0) - { - LO = SIGNED64 (0x8000000000000000); - HI = 0; - } - else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) - { - LO = SIGNED64 (0x8000000000000000); - HI = 0; - } - else - { - LO = (d1 / d2); - HI = (d1 % d2); - } - } - } -} - - -11101,xxx,yyy,11111:RR:16::DDIVU -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - signed_word op2 = (instruction >> 5) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (op2 < 2) - op2 += 16; - op2 = GPR[op2]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - CHECKHILO("Division"); - { - unsigned64 d1 = op1; - unsigned64 d2 = op2; - if (d2 == 0) - { - LO = SIGNED64 (0x8000000000000000); - HI = 0; - } - else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) - { - LO = SIGNED64 (0x8000000000000000); - HI = 0; - } - else - { - LO = (d1 / d2); - HI = (d1 % d2); - } - } - } -} - - -// Jump and Branch Instructions - - -// JALX -// JAL -00011,aaaaaaaaaaa:I:16::JAL -*mips16: -{ - unsigned32 instruction = instruction_0; - unsigned_word op1 = (instruction >> 0) & 0x7ff; - { - address_word paddr; - int uncached; - if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL)) - { - unsigned64 memval; - unsigned int reverse = (ReverseEndian ? 3 : 0); - unsigned int bigend = (BigEndianCPU ? 3 : 0); - unsigned int byte; - paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1))); - LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL); - byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1)); - memval = (memval >> (8 * byte)) & 0xffff; - op1 = (((op1 & 0x1f) << 23) - | ((op1 & 0x3e0) << 13) - | (memval << 2)); - if ((instruction & 0x400) == 0) - op1 |= 1; - PC += 2; - } - } - op1 |= PC & ~ (unsigned64) 0x0fffffff; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - int destreg = 31; - GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ - /* NOTE: ??? Gdb gets confused if the PC is sign-extended, - so we just truncate it to 32 bits here. */ - op1 = VL4_8(op1); - /* NOTE: The jump occurs AFTER the next instruction has been executed */ - DELAY_SLOT op1; - JALDELAYSLOT(); - } -} - - -11101,xxx,00000000:RR:16::JR -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - /* NOTE: ??? Gdb gets confused if the PC is sign-extended, - so we just truncate it to 32 bits here. */ - op1 = VL4_8(op1); - /* NOTE: The jump occurs AFTER the next instruction has been executed */ - DELAY_SLOT op1; - DELAYSLOT(); - } -} - - -1110100000100000,r:RR:16::JRRA -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = 31; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - /* NOTE: ??? Gdb gets confused if the PC is sign-extended, - so we just truncate it to 32 bits here. */ - op1 = VL4_8(op1); - /* NOTE: The jump occurs AFTER the next instruction has been executed */ - DELAY_SLOT op1; - DELAYSLOT(); - } -} - - -11101,xxx,01000000,R:RR:16::JALR -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int destreg = 31; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ - /* NOTE: ??? Gdb gets confused if the PC is sign-extended, - so we just truncate it to 32 bits here. */ - op1 = VL4_8(op1); - /* NOTE: The jump occurs AFTER the next instruction has been executed */ - DELAY_SLOT op1; - DELAYSLOT(); - } -} - - -00100,xxx,pppppppp,z:RI:16::BEQZ -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int offset = (instruction >> 0) & 0xff; - signed_word op2 = 0; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - if (offset >= 0x80) - offset -= 0x100; - } - offset *= 2; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - int condition = (op1 == op2); - if (condition) - PC = PC + offset; - } -} - - -00101,xxx,pppppppp,z:RI:16::BNEZ -*mips16: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = (instruction >> 8) & 0x7; - int offset = (instruction >> 0) & 0xff; - signed_word op2 = 0; - if (op1 < 2) - op1 += 16; - op1 = GPR[op1]; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - if (offset >= 0x80) - offset -= 0x100; - } - offset *= 2; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - int condition = (op1 != op2); - if (condition) - PC = PC + offset; - } -} - - -01100000,pppppppp,t,z:I8:16::BTEQZ -*mips16: -{ - unsigned32 instruction = instruction_0; - int offset = (instruction >> 0) & 0xff; - signed_word op1 = 24; - signed_word op2 = 0; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - if (offset >= 0x80) - offset -= 0x100; - } - offset *= 2; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - int condition = (op1 == op2); - if (condition) - PC = PC + offset; - } -} - - -01100001,pppppppp,t,z:I8:16::BTNEZ -*mips16: -{ - unsigned32 instruction = instruction_0; - int offset = (instruction >> 0) & 0xff; - signed_word op1 = 24; - signed_word op2 = 0; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - if (offset >= 0x80) - offset -= 0x100; - } - offset *= 2; - op1 = GPR[op1]; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - int condition = (op1 != op2); - if (condition) - PC = PC + offset; - } -} - - -00010,qqqqqqqqqqq,z,Z:I:16::B -*mips16: -{ - unsigned32 instruction = instruction_0; - int offset = (instruction >> 0) & 0x7ff; - signed_word op2 = 0; - signed_word op1 = 0; - if (have_extendval) - { - offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); - if (offset >= 0x8000) - offset -= 0x10000; - have_extendval = 0; - } - else - { - if (offset >= 0x400) - offset -= 0x800; - } - offset *= 2; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - int condition = (op1 == op2); - if (condition) - PC = PC + offset; - } -} - - -// Special Instructions - - -// See the front of the mips16 doc -11110,eeeeeeeeeee:I:16::EXTEND -*mips16: -{ - unsigned32 instruction = instruction_0; - int ext = (instruction >> 0) & 0x7ff; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - extendval = ext; - have_extendval = 1; - } -} - - -01100,******,00101:RR:16::BREAK -*mips16: -{ - unsigned32 instruction = instruction_0; - if (have_extendval) - SignalException (ReservedInstruction, instruction); - { - SignalException(BreakPoint,instruction); - } -} - - +:include::m16.igen +// start-sanitize-vr5400 +:include::vr5400.igen +// end-sanitize-vr5400 // start-sanitize-r5900 - -// FIXME: The instructions below which are typically r5900 specific -// need to be merged back into the above. - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,0000000000011010:MMINORM:32::DIV1 -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - CHECKHILO("Division"); - { - int d1 = op1; - int d2 = op2; - if (d2 == 0) - { - LO1 = SIGNEXTEND(0x80000000,32); - HI1 = SIGNEXTEND(0,32); - } - else if (d2 == -1 && d1 == 0x80000000) - { - LO1 = SIGNEXTEND(0x80000000,32); - HI1 = SIGNEXTEND(0,32); - } - else - { - LO1 = SIGNEXTEND((d1 / d2),32); - HI1 = SIGNEXTEND((d1 % d2),32); - } - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,0000000000011011:MMINORM:32::DIVU1 -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - CHECKHILO("Division"); - { - unsigned int d1 = op1; - unsigned int d2 = op2; - if (d2 == 0) - { - LO1 = SIGNEXTEND(0x80000000,32); - HI1 = SIGNEXTEND(0,32); - } - else if (d2 == -1 && d1 == 0x80000000) - { - LO1 = SIGNEXTEND(0x80000000,32); - HI1 = SIGNEXTEND(0,32); - } - else - { - LO1 = SIGNEXTEND((d1 / d2),32); - HI1 = SIGNEXTEND((d1 % d2),32); - } - } - } -} - -// end-sanitize-r5900 - -011101,26.INSTR_INDEX:NORMAL:32::JALX -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 -{ - unsigned32 instruction = instruction_0; - unsigned_word op1 = (((instruction >> 0) & 0x03FFFFFF) << 2); - op1 |= (PC & ~0x0FFFFFFF); /* address of instruction in delay slot for the jump */ - { - int destreg = 31; - GPR[destreg] = (PC + 4); /* NOTE: The PC is already 4 ahead within the simulator */ - op1 ^= 1; - /* NOTE: ??? Gdb gets confused if the PC is sign-extended, - so we just truncate it to 32 bits here. */ - op1 = VL4_8(op1); - /* NOTE: The jump occurs AFTER the next instruction has been executed */ - DELAY_SLOT op1; - /* JALDELAYSLOT(); FIXME */ - } -} - -// start-sanitize-r5900 - -011110,5.RS,5.RT,16.OFFSET:NORMAL:128::LQ -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 15) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 8; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL); - GPR[destreg] = memval; - GPR1[destreg] = memval1; - } - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000000000:MMINORM:32::MADD -*r5900: -*r3900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - word64 prod = (word64)WORD64(VL4_8(HI),VL4_8(LO)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32)); - LO = SIGNEXTEND(prod,32); - HI = SIGNEXTEND( VH4_8(prod), 32); - if( destreg != 0 ) GPR[destreg] = LO; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000000001:MMINORM:32::MADDU -*r5900: -*r3900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - unsigned64 prod = (unsigned64)WORD64(VL4_8(HI),VL4_8(LO)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2)); - LO = SIGNEXTEND(prod,32); - HI = SIGNEXTEND( VH4_8(prod), 32); - if( destreg != 0 ) GPR[destreg] = LO; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000100000:MMINORM:32::MADD1 -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - word64 prod = (word64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32)); - LO1 = SIGNEXTEND(prod,32); - HI1 = SIGNEXTEND( VH4_8(prod), 32); - if( destreg != 0 ) GPR[destreg] = LO1; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000100001:MMINORM:32::MADDU1 -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - unsigned64 prod = (unsigned64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2)); - LO1 = SIGNEXTEND(prod,32); - HI1 = SIGNEXTEND( VH4_8(prod), 32); - if( destreg != 0 ) GPR[destreg] = LO1; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -0111000000000000,5.RD,00000010000:MMINORM:32::MFHI1 -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - { - GPR[destreg] = HI1; - HI1ACCESS = 3; /* 3rd instruction will be safe */ - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -0111000000000000,5.RD,00000010010:MMINORM:32::MFLO1 -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - { - GPR[destreg] = LO1; - LO1ACCESS = 3; /* 3rd instruction will be safe */ - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -0000000000000000,5.RD,00000101000:SPECIAL:32::MFSA -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - { - GPR[destreg] = SA; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,000000000000000010001:MMINORM:32::MTHI1 -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - if (HI1ACCESS != 0) - sim_io_error(sd,"MT (move-to) over-writing HI register value\n"); - HI1 = op1; - HI1ACCESS = 3; /* 3rd instruction will be safe */ - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,000000000000000010011:MMINORM:32::MTLO1 -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - if (LO1ACCESS != 0) - sim_io_error(sd,"MT (move-to) over-writing LO register value"); - LO1 = op1; - LO1ACCESS = 3; /* 3rd instruction will be safe */ - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -000000,5.RS,000000000000000101001:SPECIAL:32::MTSA -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - SA = op1; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -000001,5.RS,11000,16.IMMEDIATE:REGIMM:32::MTSAB -*r5900: -{ - SA = ((GPR[RA] & 0xF) ^ (IMMEDIATE & 0xF)) * 8; -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -000001,5.RS,11001,16.IMMEDIATE:REGIMM:32::MTSAH -*r5900: -{ - SA = ((GPR[RS] & 0x7) ^ (IMMEDIATE & 0x7)) * 16; -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000011000:MMINORM:32::MULT1 -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - CHECKHILO("Multiplication"); - { - unsigned64 temp = ((word64) op1 * (word64) op2); - LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32); - HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32); - if ( destreg != 0 ) - GPR[destreg] = LO1; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000011001:MMINORM:32::MULTU1 -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - CHECKHILO("Multiplication"); - { - unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff)); - LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32); - HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32); - if ( destreg != 0 ) - GPR[destreg] = LO1; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,00101101000:MMI1:32::PABSH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i= 0) - GPR_SH(destreg,i) = RT_SH(i); - else if (RT_SH(i) == -32768) - GPR_SH(destreg,i) = 32767; - else - GPR_SH(destreg,i) = -RT_SH(i); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,00001101000:MMI1:32::PABSW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i= 0) - GPR_SW(destreg,i) = RT_SW(i); - else if (RT_SW(i) == (int)0x80000000) - GPR_SW(destreg,i) = (int)0x7FFFFFFF; - else - GPR_SW(destreg,i) = -RT_SW(i); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01000001000:MMI0:32::PADDB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < BYTES_IN_MMI_REGS; i++) - { - int s = RS_SB(i); - int t = RT_SB(i); - int r = s + t; - GPR_SB(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00100001000:MMI0:32::PADDH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) - { - int s = RS_SH(i); - int t = RT_SH(i); - int r = s + t; - GPR_SH(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000001000:MMI0:32::PADDW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < WORDS_IN_MMI_REGS; i++) - { - signed64 s = RS_SW(i); - signed64 t = RT_SW(i); - signed64 r = s + t; - GPR_SW(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,11000001000:MMI0:32::PADDSB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < BYTES_IN_MMI_REGS; i++) - { - int s = RS_SB(i); - int t = RT_SB(i); - int r = s + t; - if (r > 127) - GPR_SB(destreg,i) = 127; - else if (r < -128) - GPR_SB(destreg,i) = -128; - else - GPR_SB(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10100001000:MMI0:32::PADDSH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) - { - int s = RS_SH(i); - int t = RT_SH(i); - int r = s + t; - if (r > 32767) - GPR_SH(destreg,i) = 32767; - else if (r < -32768) - GPR_SH(destreg,i) = -32768; - else - GPR_SH(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10000001000:MMI0:32::PADDSW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < WORDS_IN_MMI_REGS; i++) - { - signed64 s = RS_SW(i); - signed64 t = RT_SW(i); - signed64 r = s + t; - if (r > (int)0x7FFFFFFF) - GPR_SW(destreg,i) = (int)0x7FFFFFFF; - else if (r < (int)0x80000000) - GPR_SW(destreg,i) = (int)0x80000000; - else - GPR_SW(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,11000101000:MMI1:32::PADDUB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < BYTES_IN_MMI_REGS; i++) - { - unsigned int s = RS_UB(i); - unsigned int t = RT_UB(i); - unsigned int r = s + t; - if (r > 0xFF) - GPR_UB(destreg,i) = 0xFF; - else - GPR_UB(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10100101000:MMI1:32::PADDUH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) - { - unsigned int s = RS_UH(i); - unsigned int t = RT_UH(i); - unsigned int r = s + t; - if (r > 0xFFFF) - GPR_UH(destreg,i) = 0xFFFF; - else - GPR_UH(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10000101000:MMI1:32::PADDUW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < WORDS_IN_MMI_REGS; i++) - { - unsigned64 s = RS_UW(i); - unsigned64 t = RT_UW(i); - unsigned64 r = s + t; - if (r > 0xFFFFFFFF) - GPR_UW(destreg,i) = 0xFFFFFFFF; - else - GPR_UW(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00100101000:MMI1:32::PADSBH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i RT_SB(i)) GPR_SB(destreg,i) = 0xFF; - else GPR_SB(destreg,i) = 0; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00110001000:MMI0:32::PCGTH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF; - else GPR_SH(destreg,i) = 0; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00010001000:MMI0:32::PCGTW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF; - else GPR_SW(destreg,i) = 0; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11011101001:MMI3:32::PCPYH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,7) = GPR_UH(destreg,6) = GPR_UH(destreg,5) = GPR_UH(destreg,4) = RT_UH(4); - GPR_UH(destreg,3) = GPR_UH(destreg,2) = GPR_UH(destreg,1) = GPR_UH(destreg,0) = RT_UH(0); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01110001001:MMI2:32::PCPYLD -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UD(destreg,0) = RT_UD(0); - GPR_UD(destreg,1) = RS_UD(0); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01110101001:MMI3:32::PCPYUD -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UD(destreg,0) = RS_UD(1); - GPR_UD(destreg,1) = RT_UD(1); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,0000011101001001:MMI2:32::PDIVBW -*r5900: -{ - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - signed32 devisor = RT_SH(0); - if (devisor == -1) - { - LO_SW(0) = -RS_SW(0); - HI_SW(0) = 0; - LO_SW(1) = -RS_SW(1); - HI_SW(1) = 0; - LO_SW(2) = -RS_SW(2); - HI_SW(2) = 0; - LO_SW(3) = -RS_SW(3); - HI_SW(3) = 0; - } - else if (devisor != 0) - { - LO_SW(0) = RS_SW(0) / devisor; - HI_SW(0) = SIGNEXTEND( (RS_SW(0) % devisor), 16 ); - LO_SW(1) = RS_SW(1) / devisor; - HI_SW(1) = SIGNEXTEND( (RS_SW(1) % devisor), 16 ); - LO_SW(2) = RS_SW(2) / devisor; - HI_SW(2) = SIGNEXTEND( (RS_SW(2) % devisor), 16 ); - LO_SW(3) = RS_SW(3) / devisor; - HI_SW(3) = SIGNEXTEND( (RS_SW(3) % devisor), 16 ); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,0000001101101001:MMI3:32::PDIVUW -*r5900: -{ - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - if (RT_UW(0) != 0) - { - LO = (signed32)(RS_UW(0) / RT_UW(0)); - HI = (signed32)(RS_UW(0) % RT_UW(0)); - } - if (RT_UW(2) != 0) - { - LO1 = (signed32)(RS_UW(2) / RT_UW(2)); - HI1 = (signed32)(RS_UW(2) % RT_UW(2)); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,0000001101001001:MMI2:32::PDIVW -*r5900: -{ - signed_word rs_reg = GPR[RS]; - signed_word rs_reg1 = GPR1[RS]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - if (RT_SW(0) == -1) - { - LO = -RS_SW(0); - HI = 0; - } - else if (RT_UW(0) != 0) - { - LO = (signed32)(RS_SW(0) / RT_SW(0)); - HI = (signed32)(RS_SW(0) % RT_SW(0)); - } - if (RT_SW(2) == -1) - { - LO1 = -RS_SW(2); - HI1 = 0; - } - else if (RT_UW(2) != 0) - { - LO1 = (signed32)(RS_SW(2) / RT_SW(2)); - HI1 = (signed32)(RS_SW(2) % RT_SW(2)); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11010101001:MMI3:32::PEXCH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(0); - GPR_UH(destreg,1) = RT_UH(2); - GPR_UH(destreg,2) = RT_UH(1); - GPR_UH(destreg,3) = RT_UH(3); - GPR_UH(destreg,4) = RT_UH(4); - GPR_UH(destreg,5) = RT_UH(6); - GPR_UH(destreg,6) = RT_UH(5); - GPR_UH(destreg,7) = RT_UH(7); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11110101001:MMI3:32::PEXCW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UW(destreg,0) = RT_UW(0); - GPR_UW(destreg,1) = RT_UW(2); - GPR_UW(destreg,2) = RT_UW(1); - GPR_UW(destreg,3) = RT_UW(3); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11010001001:MMI2:32::PEXOH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(2); - GPR_UH(destreg,1) = RT_UH(1); - GPR_UH(destreg,2) = RT_UH(0); - GPR_UH(destreg,3) = RT_UH(3); - GPR_UH(destreg,4) = RT_UH(6); - GPR_UH(destreg,5) = RT_UH(5); - GPR_UH(destreg,6) = RT_UH(4); - GPR_UH(destreg,7) = RT_UH(7); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11110001001:MMI2:32::PEXOW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UW(destreg,0) = RT_UW(2); - GPR_UW(destreg,1) = RT_UW(1); - GPR_UW(destreg,2) = RT_UW(0); - GPR_UW(destreg,3) = RT_UW(3); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11110001000:MMI0:32::PEXT5 -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UB(destreg,0) = RT_UB(0); - GPR_UB(destreg,1) = RS_UB(0); - GPR_UB(destreg,2) = RT_UB(1); - GPR_UB(destreg,3) = RS_UB(1); - GPR_UB(destreg,4) = RT_UB(2); - GPR_UB(destreg,5) = RS_UB(2); - GPR_UB(destreg,6) = RT_UB(3); - GPR_UB(destreg,7) = RS_UB(3); - GPR_UB(destreg,8) = RT_UB(4); - GPR_UB(destreg,9) = RS_UB(4); - GPR_UB(destreg,10) = RT_UB(5); - GPR_UB(destreg,11) = RS_UB(5); - GPR_UB(destreg,12) = RT_UB(6); - GPR_UB(destreg,13) = RS_UB(6); - GPR_UB(destreg,14) = RT_UB(7); - GPR_UB(destreg,15) = RS_UB(7); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10110001000:MMI0:32::PEXTLH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(0); - GPR_UH(destreg,1) = RS_UH(0); - GPR_UH(destreg,2) = RT_UH(1); - GPR_UH(destreg,3) = RS_UH(1); - GPR_UH(destreg,4) = RT_UH(2); - GPR_UH(destreg,5) = RS_UH(2); - GPR_UH(destreg,6) = RT_UH(3); - GPR_UH(destreg,7) = RS_UH(3); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10010001000:MMI0:32::PEXTLW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UW(destreg,0) = RT_UW(0); - GPR_UW(destreg,1) = RS_UW(0); - GPR_UW(destreg,2) = RT_UW(1); - GPR_UW(destreg,3) = RS_UW(1); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,11010101000:MMI1:32::PEXTUB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UB(destreg,0) = RT_UB(8); - GPR_UB(destreg,1) = RS_UB(8); - GPR_UB(destreg,2) = RT_UB(9); - GPR_UB(destreg,3) = RS_UB(9); - GPR_UB(destreg,4) = RT_UB(10); - GPR_UB(destreg,5) = RS_UB(10); - GPR_UB(destreg,6) = RT_UB(11); - GPR_UB(destreg,7) = RS_UB(11); - GPR_UB(destreg,8) = RT_UB(12); - GPR_UB(destreg,9) = RS_UB(12); - GPR_UB(destreg,10) = RT_UB(13); - GPR_UB(destreg,11) = RS_UB(13); - GPR_UB(destreg,12) = RT_UB(14); - GPR_UB(destreg,13) = RS_UB(14); - GPR_UB(destreg,14) = RT_UB(15); - GPR_UB(destreg,15) = RS_UB(15); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10110101000:MMI1:32::PEXTUH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(4); - GPR_UH(destreg,1) = RS_UH(4); - GPR_UH(destreg,2) = RT_UH(5); - GPR_UH(destreg,3) = RS_UH(5); - GPR_UH(destreg,4) = RT_UH(6); - GPR_UH(destreg,5) = RS_UH(6); - GPR_UH(destreg,6) = RT_UH(7); - GPR_UH(destreg,7) = RS_UH(7); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10010101000:MMI1:32::PEXTUW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UW(destreg,0) = RT_UW(2); - GPR_UW(destreg,1) = RS_UW(2); - GPR_UW(destreg,2) = RT_UW(3); - GPR_UW(destreg,3) = RS_UW(3); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10001001001:MMI2:32::PHMADDH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) + (RS_SH(0) * RT_SH(0)); - GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) + (RS_SH(2) * RT_SH(2)); - GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) + (RS_SH(4) * RT_SH(4)); - GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) + (RS_SH(6) * RT_SH(6)); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10101001001:MMI2:32::PHMSUBH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) - (RS_SH(0) * RT_SH(0)); - GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) - (RS_SH(2) * RT_SH(2)); - GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) - (RS_SH(4) * RT_SH(4)); - GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) - (RS_SH(6) * RT_SH(6)); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01010001001:MMI2:32::PINTH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(0); - GPR_UH(destreg,1) = RS_UH(4); - GPR_UH(destreg,2) = RT_UH(1); - GPR_UH(destreg,3) = RS_UH(5); - GPR_UH(destreg,4) = RT_UH(2); - GPR_UH(destreg,5) = RS_UH(6); - GPR_UH(destreg,6) = RT_UH(3); - GPR_UH(destreg,7) = RS_UH(7); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01010101001:MMI3:32::PINTOH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(0); - GPR_UH(destreg,1) = RS_UH(0); - GPR_UH(destreg,2) = RT_UH(2); - GPR_UH(destreg,3) = RS_UH(2); - GPR_UH(destreg,4) = RT_UH(4); - GPR_UH(destreg,5) = RS_UH(4); - GPR_UH(destreg,6) = RT_UH(6); - GPR_UH(destreg,7) = RS_UH(6); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,00000,5.RD,00000000100:MMINORM:32::PLZCW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - { - unsigned long value; - int test; - int count; - int i; - value = RS_UW(0); - count = 0; - test = !!(value & (1 << 31)); - for(i=30; i>=0 && (test == !!(value & (1 << i))); i--) - count++; - GPR_UW(destreg,0) = count; - value = RS_UW(1); - count = 0; - test = !!(value & (1 << 31)); - for(i=30; i>=0 && (test == !!(value & (1 << i))); i--) - count++; - GPR_UW(destreg,1) = count; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10000001001:MMI2:32::PMADDH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_SW(destreg,0) = LO_SW(0) += (RS_SH(0) * RT_SH(0)); - LO_SW(1) += (RS_SH(1) * RT_SH(1)); - GPR_SW(destreg,1) = HI_SW(0) += (RS_SH(2) * RT_SH(2)); - HI_SW(1) += (RS_SH(3) * RT_SH(3)); - GPR_SW(destreg,2) = LO_SW(2) += (RS_SH(4) * RT_SH(4)); - LO_SW(3) += (RS_SH(5) * RT_SH(5)); - GPR_SW(destreg,3) = HI_SW(2) += (RS_SH(6) * RT_SH(6)); - HI_SW(3) += (RS_SH(7) * RT_SH(7)); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000101001:MMI3:32::PMADDUW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - unsigned64 sum0 = U8_4 (HI_SW(0), LO_SW(0)); - unsigned64 sum1 = U8_4 (HI_SW(2), LO_SW(2)); - unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0); - unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2); - sum0 += prod0; - sum1 += prod1; - GPR_UD(destreg,0) = sum0; - GPR_UD(destreg,1) = sum1; - LO = SIGNEXTEND( sum0, 32 ); - HI = SIGNEXTEND( VH4_8(sum0), 32 ); - LO1 = SIGNEXTEND( sum1, 32 ); - HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00000001001:MMI2:32::PMADDW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) ); - signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) ); - signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0); - signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2); - sum0 += prod0; - sum1 += prod1; - GPR_SD(destreg,0) = sum0; - GPR_SD(destreg,1) = sum1; - LO = SIGNEXTEND( sum0, 32 ); - HI = SIGNEXTEND( VH4_8(sum0), 32 ); - LO1 = SIGNEXTEND( sum1, 32 ); - HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00111001000:MMI0:32::PMAXH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i); - else GPR_SH(destreg,i) = RT_SH(i); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00011001000:MMI0:32::PMAXW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i); - else GPR_SW(destreg,i) = RT_SW(i); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -0111000000000000,5.RD,01000001001:MMI2:32::PMFHI -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - { - GPR_SD(destreg,0) = HI; - GPR_SD(destreg,1) = HI1; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -0111000000000000,5.RD,01001001001:MMI2:32::PMFLO -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - { - GPR_SD(destreg,0) = LO; - GPR_SD(destreg,1) = LO1; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -0111000000000000,5.RD,5.SHIFT,110000:MMINORM:32::PMFHL -*r5900: -{ - unsigned32 instruction = instruction_0; - int op1 = ((instruction >> 6) & 0x0000001F); - int destreg = ((instruction >> 11) & 0x0000001F); - { - if (op1 == 0) - { - GPR_UW(destreg,0) = LO_UW(0); - GPR_UW(destreg,1) = HI_UW(0); - GPR_UW(destreg,2) = LO_UW(2); - GPR_UW(destreg,3) = HI_UW(2); - } - else if (op1 == 1) - { - GPR_UW(destreg,0) = LO_UW(1); - GPR_UW(destreg,1) = HI_UW(1); - GPR_UW(destreg,2) = LO_UW(3); - GPR_UW(destreg,3) = HI_UW(3); - } - else if (op1 == 2) - { - /* NOTE: This code implements a saturate according to the - figure on page B-115 and not according to the - definition on page B-113 */ - signed64 t = ((unsigned64)HI_UW(0) << 32) | (unsigned64)LO_UW(0); - signed64 u = ((unsigned64)HI_UW(2) << 32) | (unsigned64)LO_UW(2); - if ( t > SIGNED64 (0x000000007FFFFFFF) ) - GPR_SD(destreg,0) = SIGNED64 (0x000000007FFFFFFF); - else if ( t < - SIGNED64 (0x0000000080000000) ) - GPR_SD(destreg,0) = - SIGNED64 (0x0000000080000000); - else - GPR_SD(destreg,0) = t; - if ( u > SIGNED64 (0x000000007FFFFFFF) ) - GPR_SD(destreg,1) = SIGNED64 (0x000000007FFFFFFF); - else if ( u < - SIGNED64 (0x0000000080000000) ) - GPR_SD(destreg,1) = - SIGNED64 (0x0000000080000000); - else - GPR_SD(destreg,1) = u; - } - else if (op1 == 3) - { - GPR_UH(destreg,0) = LO_UH(0); - GPR_UH(destreg,1) = LO_UH(2); - GPR_UH(destreg,2) = HI_UH(0); - GPR_UH(destreg,3) = HI_UH(2); - GPR_UH(destreg,4) = LO_UH(4); - GPR_UH(destreg,5) = LO_UH(6); - GPR_UH(destreg,6) = HI_UH(4); - GPR_UH(destreg,7) = HI_UH(6); - } - else if (op1 == 4) - { - if (LO_SW(0) > 0x7FFF) - GPR_UH(destreg,0) = 0x7FFF; - else if (LO_SW(0) < -0x8000) - GPR_UH(destreg,0) = 0x8000; - else - GPR_UH(destreg,0) = LO_UH(0); - if (LO_SW(1) > 0x7FFF) - GPR_UH(destreg,1) = 0x7FFF; - else if (LO_SW(1) < -0x8000) - GPR_UH(destreg,1) = 0x8000; - else - GPR_UH(destreg,1) = LO_UH(2); - if (HI_SW(0) > 0x7FFF) - GPR_UH(destreg,2) = 0x7FFF; - else if (HI_SW(0) < -0x8000) - GPR_UH(destreg,2) = 0x8000; - else - GPR_UH(destreg,2) = HI_UH(0); - if (HI_SW(1) > 0x7FFF) - GPR_UH(destreg,3) = 0x7FFF; - else if (HI_SW(1) < -0x8000) - GPR_UH(destreg,3) = 0x8000; - else - GPR_UH(destreg,3) = HI_UH(2); - if (LO_SW(2) > 0x7FFF) - GPR_UH(destreg,4) = 0x7FFF; - else if (LO_SW(2) < -0x8000) - GPR_UH(destreg,4) = 0x8000; - else - GPR_UH(destreg,4) = LO_UH(4); - if (LO_SW(3) > 0x7FFF) - GPR_UH(destreg,5) = 0x7FFF; - else if (LO_SW(3) < -0x8000) - GPR_UH(destreg,5) = 0x8000; - else - GPR_UH(destreg,5) = LO_UH(6); - if (HI_SW(2) > 0x7FFF) - GPR_UH(destreg,6) = 0x7FFF; - else if (HI_SW(2) < -0x8000) - GPR_UH(destreg,6) = 0x8000; - else - GPR_UH(destreg,6) = HI_UH(4); - if (HI_SW(3) > 0x7FFF) - GPR_UH(destreg,7) = 0x7FFF; - else if (HI_SW(3) < -0x8000) - GPR_UH(destreg,7) = 0x8000; - else - GPR_UH(destreg,7) = HI_UH(6); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00111101000:MMI1:32::PMINH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_SW(destreg,0) = LO_SW(0) -= (RS_SH(0) * RT_SH(0)); - LO_SW(1) -= (RS_SH(1) * RT_SH(1)); - GPR_SW(destreg,1) = HI_SW(0) -= (RS_SH(2) * RT_SH(2)); - HI_SW(1) -= (RS_SH(3) * RT_SH(3)); - GPR_SW(destreg,2) = LO_SW(2) -= (RS_SH(4) * RT_SH(4)); - LO_SW(3) -= (RS_SH(5) * RT_SH(5)); - GPR_SW(destreg,3) = HI_SW(2) -= (RS_SH(6) * RT_SH(6)); - HI_SW(3) -= (RS_SH(7) * RT_SH(7)); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00100001001:MMI2:32::PMSUBW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) ); - signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) ); - signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0); - signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2); - sum0 -= prod0; - sum1 -= prod1; - GPR_SD(destreg,0) = sum0; - GPR_SD(destreg,1) = sum1; - LO = SIGNEXTEND( sum0, 32 ); - HI = SIGNEXTEND( VH4_8(sum0), 32 ); - LO1 = SIGNEXTEND( sum1, 32 ); - HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,000000000001000101001:MMI3:32::PMTHI -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - { - HI = RS_SD(0); - HI1 = RS_SD(1); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,000000000001001101001:MMI3:32::PMTLO -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - { - LO = RS_SD(0); - LO1 = RS_SD(1); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,000000000000000110001:MMINORM:32::PMTHL.LW -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - { - LO_UW(0) = RS_UW(0); - HI_UW(0) = RS_UW(1); - LO_UW(2) = RS_UW(2); - HI_UW(2) = RS_UW(3); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,11100001001:MMI2:32::PMULTH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(0) * RT_SH(0)); - LO_SW(1) = (RS_SH(1) * RT_SH(1)); - GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(2) * RT_SH(2)); - HI_SW(1) = (RS_SH(3) * RT_SH(3)); - GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(4) * RT_SH(4)); - LO_SW(3) = (RS_SH(5) * RT_SH(5)); - GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(6) * RT_SH(6)); - HI_SW(3) = (RS_SH(7) * RT_SH(7)); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01100101001:MMI3:32::PMULTUW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - unsigned64 sum0 = 0; - unsigned64 sum1 = 0; - unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0); - unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2); - sum0 = prod0; - sum1 = prod1; - GPR_UD(destreg,0) = sum0; - GPR_UD(destreg,1) = sum1; - LO = SIGNEXTEND( sum0, 32 ); - HI = SIGNEXTEND( VH4_8(sum0), 32 ); - LO1 = SIGNEXTEND( sum1, 32 ); - HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01100001001:MMI2:32::PMULTW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - signed64 sum0 = 0; - signed64 sum1 = 0; - signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0); - signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2); - sum0 = prod0; - sum1 = prod1; - GPR_SD(destreg,0) = sum0; - GPR_SD(destreg,1) = sum1; - LO = SIGNEXTEND( sum0, 32 ); - HI = SIGNEXTEND( VH4_8(sum0), 32 ); - LO1 = SIGNEXTEND( sum1, 32 ); - HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10011101001:MMI3:32::PNOR -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> (31 - 15)) - | ((x & (31 << 19)) >> (19 - 10)) - | ((x & (31 << 11)) >> (11 - 5)) - | ((x & (31 << 3)) >> (3 - 0)); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,11011001000:MMI0:32::PPACB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UB(destreg,0) = RT_UB(0); - GPR_UB(destreg,1) = RT_UB(2); - GPR_UB(destreg,2) = RT_UB(4); - GPR_UB(destreg,3) = RT_UB(6); - GPR_UB(destreg,4) = RT_UB(8); - GPR_UB(destreg,5) = RT_UB(10); - GPR_UB(destreg,6) = RT_UB(12); - GPR_UB(destreg,7) = RT_UB(14); - GPR_UB(destreg,8) = RS_UB(0); - GPR_UB(destreg,9) = RS_UB(2); - GPR_UB(destreg,10) = RS_UB(4); - GPR_UB(destreg,11) = RS_UB(6); - GPR_UB(destreg,12) = RS_UB(8); - GPR_UB(destreg,13) = RS_UB(10); - GPR_UB(destreg,14) = RS_UB(12); - GPR_UB(destreg,15) = RS_UB(14); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10111001000:MMI0:32::PPACH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(0); - GPR_UH(destreg,1) = RT_UH(2); - GPR_UH(destreg,2) = RT_UH(4); - GPR_UH(destreg,3) = RT_UH(6); - GPR_UH(destreg,4) = RS_UH(0); - GPR_UH(destreg,5) = RS_UH(2); - GPR_UH(destreg,6) = RS_UH(4); - GPR_UH(destreg,7) = RS_UH(6); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10011001000:MMI0:32::PPACW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UW(destreg,0) = RT_UW(0); - GPR_UW(destreg,1) = RT_UW(2); - GPR_UW(destreg,2) = RS_UW(0); - GPR_UW(destreg,3) = RS_UW(2); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11011001001:MMI2:32::PREVH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UH(destreg,0) = RT_UH(3); - GPR_UH(destreg,1) = RT_UH(2); - GPR_UH(destreg,2) = RT_UH(1); - GPR_UH(destreg,3) = RT_UH(0); - GPR_UH(destreg,4) = RT_UH(7); - GPR_UH(destreg,5) = RT_UH(6); - GPR_UH(destreg,6) = RT_UH(5); - GPR_UH(destreg,7) = RT_UH(4); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,11111001001:MMI2:32::PROT3W -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UW(destreg,0) = RT_UW(0); - GPR_UW(destreg,1) = RT_UW(3); - GPR_UW(destreg,2) = RT_UW(1); - GPR_UW(destreg,3) = RT_UW(2); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,5.SHIFT,110100:MMINORM:32::PSLLH -*r5900: -{ - unsigned32 instruction = instruction_0; - int op1 = ((instruction >> 6) & 0x0000001F); - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int shift_by = op1 & (16-1); - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int s0 = (RS_UB(0) & 0x1F); - int s1 = (RS_UB(8) & 0x1F); - signed32 temp0 = RT_UW(0) << s0; - signed32 temp1 = RT_UW(2) << s1; - GPR_SD(destreg,0) = (signed64)temp0; - GPR_SD(destreg,1) = (signed64)temp1; - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,5.SHIFT,111100:MMINORM:32::PSLLW -*r5900: -{ - unsigned32 instruction = instruction_0; - int op1 = ((instruction >> 6) & 0x0000001F); - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int shift_by = op1 & (32-1); - int i; - for(i=0;i> 6) & 0x0000001F); - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int shift_by = op1 & (16-1); - int i; - for(i=0;i> shift_by), (16-shift_by) ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00011101001:MMI3:32::PSRAVW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_SD(destreg,0) = SIGNEXTEND( (RT_SW (0) >> (RS_UB(0) & 0x1F)), 32-(RS_UB(0) & 0x1F) ); - GPR_SD(destreg,1) = SIGNEXTEND( (RT_SW (2) >> (RS_UB(8) & 0x1F)), 32-(RS_UB(8) & 0x1F) ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,5.SHIFT,111111:MMINORM:32::PSRAW -*r5900: -{ - unsigned32 instruction = instruction_0; - int op1 = ((instruction >> 6) & 0x0000001F); - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int shift_by = op1 & (32-1); - int i; - for(i=0;i> shift_by), (32-shift_by) ); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,5.SHIFT,110110:MMINORM:32::PSRLH -*r5900: -{ - unsigned32 instruction = instruction_0; - int op1 = ((instruction >> 6) & 0x0000001F); - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int shift_by = op1 & (16-1); - int i; - for(i=0;i> shift_by); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00011001001:MMI2:32::PSRLVW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - GPR_UD(destreg,0) = SIGNEXTEND ( RT_UW(0) >> (RS_UB(0) & 0x1F), 31); - GPR_UD(destreg,1) = SIGNEXTEND ( RT_UW(2) >> (RS_UB(8) & 0x1F), 31); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -01110000000,5.RT,5.RD,5.SHIFT,111110:MMINORM:32::PSRLW -*r5900: -{ - unsigned32 instruction = instruction_0; - int op1 = ((instruction >> 6) & 0x0000001F); - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int shift_by = op1 & (32-1); - int i; - for(i=0;i> shift_by); - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,01001001000:MMI0:32::PSUBB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < BYTES_IN_MMI_REGS; i++) - { - int s = RS_SB(i); - int t = RT_SB(i); - int r = s - t; - GPR_SB(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00101001000:MMI0:32::PSUBH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) - { - int s = RS_SH(i); - int t = RT_SH(i); - int r = s - t; - GPR_SH(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,11001001000:MMI0:32::PSUBSB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < BYTES_IN_MMI_REGS; i++) - { - int s = RS_SB(i); - int t = RT_SB(i); - int r = s - t; - if (r > 127) - GPR_SB(destreg,i) = 127; - else if (r < -128) - GPR_SB(destreg,i) = -128; - else - GPR_SB(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10101001000:MMI0:32::PSUBSH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) - { - int s = RS_SH(i); - int t = RT_SH(i); - int r = s - t; - if (r > 32767) - GPR_SH(destreg,i) = 32767; - else if (r < -32768) - GPR_SH(destreg,i) = -32768; - else - GPR_SH(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10001001000:MMI0:32::PSUBSW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < WORDS_IN_MMI_REGS; i++) - { - signed64 s = RS_SW(i); - signed64 t = RT_SW(i); - signed64 r = s - t; - if (r > (int)0x7FFFFFFF) - GPR_SW(destreg,i) = (int)0x7FFFFFFF; - else if (r < (int)0x80000000) - GPR_SW(destreg,i) = (int)0x80000000; - else - GPR_SW(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,11001101000:MMI1:32::PSUBUB -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < BYTES_IN_MMI_REGS; i++) - { - unsigned int s = RS_UB(i); - unsigned int t = RT_UB(i); - unsigned int r = s - t; - if (r > 0xFF) - GPR_UB(destreg,i) = 0; - else - GPR_UB(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10101101000:MMI1:32::PSUBUH -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) - { - unsigned int s = RS_UH(i); - unsigned int t = RT_UH(i); - unsigned int r = s - t; - if (r > 0xFFFF) - GPR_UH(destreg,i) = 0; - else - GPR_UH(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10001101000:MMI1:32::PSUBUW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < WORDS_IN_MMI_REGS; i++) - { - unsigned64 s = RS_UW(i); - unsigned64 t = RT_UW(i); - unsigned64 r = s - t; - if (r > 0xFFFFFFFF) - GPR_UW(destreg,i) = 0; - else - GPR_UW(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,00001001000:MMI0:32::PSUBW -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for (i=0; i < WORDS_IN_MMI_REGS; i++) - { - signed64 s = RS_SW(i); - signed64 t = RT_SW(i); - signed64 r = s - t; - GPR_SW(destreg,i) = r; - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011100,5.RS,5.RT,5.RD,10011001001:MMI2:32::PXOR -*r5900: -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int i; - for(i=0;i> 11) & 0x0000001F); - signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - int bytes = (SA / 8) % 16; - if (SA % 8) - SignalException(ReservedInstruction,instruction); - else - { - int i; - for(i=0;i<(16-bytes);i++) - GPR_SB(destreg,i) = RT_SB(bytes+i); - for(;i<16;i++) - GPR_SB(destreg,i) = RS_SB(i-(16-bytes)); - } - } -} - -// end-sanitize-r5900 -// start-sanitize-r5900 - -011111,5.RS,5.RT,16.OFFSET:NORMAL:128::SQ -*r5900: -{ - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - signed_word rt_reg = GPR[RT]; - signed_word rt_reg1 = GPR1[RT]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 15) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = rsigned_word; - memval1 = rsigned_word1; - { - StoreMemory(uncached,AccessLength_QUADWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } -} - +:include::r5900.igen // end-sanitize-r5900 // start-sanitize-cygnus-never diff --git a/sim/mips/vr5400.igen b/sim/mips/vr5400.igen new file mode 100644 index 0000000000..d15abba597 --- /dev/null +++ b/sim/mips/vr5400.igen @@ -0,0 +1 @@ +// Empty