* simops.c: Fix restoring the PC for "ret" and "retf" instructions.
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@ -1,3 +1,14 @@
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Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix restoring the PC for "ret" and "retf" instructions.
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Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
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* gencode.c (write_opcodes): Also write out the format of the
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opcode.
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* mn10300_sim.h (simops): Add "format" field.
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* interp.c (sim_resume): Deal with endianness issues here.
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Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c (REG0_4): Define.
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@ -2690,7 +2690,6 @@ void OP_DF0000 (insn, extension)
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unsigned long mask;
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State.regs[REG_SP] += insn & 0xff;
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State.pc = State.regs[REG_MDR] - 3;
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sp = State.regs[REG_SP];
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mask = (insn & 0xff00) >> 8;
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@ -2737,6 +2736,14 @@ void OP_DF0000 (insn, extension)
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State.regs[REG_D0 + 2] = load_mem (sp, 4);
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sp += 4;
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}
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/* And make sure to update the stack pointer. */
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State.regs[REG_SP] = sp;
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/* Restore the PC value. */
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State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
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| (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
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State.pc -= 3;
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}
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/* retf reg_list,imm8 */
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@ -2748,9 +2755,7 @@ void OP_DE0000 (insn, extension)
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sp = State.regs[REG_SP] + (insn & 0xff);
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State.regs[REG_SP] = sp;
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State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
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| (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
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State.pc -= 3;
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State.pc = State.regs[REG_MDR] - 3;
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sp = State.regs[REG_SP];
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@ -2798,6 +2803,9 @@ void OP_DE0000 (insn, extension)
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State.regs[REG_D0 + 2] = load_mem (sp, 4);
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sp += 4;
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}
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/* And make sure to update the stack pointer. */
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State.regs[REG_SP] = sp;
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}
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/* rets */
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