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include/opcode/ 

* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
	Use "source" rather than "destination" for microMIPS "G".

gas/
	* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
This commit is contained in:
Richard Sandiford 2013-06-26 07:04:57 +00:00
parent ddacd3c8e9
commit 18870af79b
4 changed files with 14 additions and 5 deletions
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4
gas/ChangeLog
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@ -1,3 +1,7 @@
2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (mips_set_options): Add insn32 member.

2
gas/config/tc-mips.c
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@ -10975,7 +10975,7 @@ validate_mips_insn (const struct mips_opcode *opc)
case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
case '[': break;
case ']': break;
case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break;
case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;

5
include/opcode/ChangeLog
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@ -1,3 +1,8 @@
2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
Use "source" rather than "destination" for microMIPS "G".
2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum

8
include/opcode/mips.h
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@ -377,7 +377,7 @@ struct mips_opcode
Each of these characters corresponds to a mask field defined above.
"1" 5 bit sync type (OP_*_SHAMT)
"1" 5 bit sync type (OP_*_STYPE)
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET)
@ -1742,7 +1742,7 @@ extern const int bfd_mips16_num_opcodes;
others too).
"." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
"1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
"1" 5-bit sync type (MICROMIPSOP_*_STYPE)
"<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32
(MICROMIPSOP_*_SHAMT)
@ -1814,9 +1814,9 @@ extern const int bfd_mips16_num_opcodes;
Coprocessor instructions:
"E" 5-bit target register (MICROMIPSOP_*_RT)
"G" 5-bit destination register (MICROMIPSOP_*_RS)
"G" 5-bit source register (MICROMIPSOP_*_RS)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
"+D" combined destination register ("G") and sel ("H") for CP0 ops,
"+D" combined source register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only
Macro instructions: