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* config/tc-aarch64.c (parse_sys_reg): Support
	S2_<op1>_<Cn>_<Cm>_<op2>.

gas/testsuite/

	* gas/testsuite/sysreg.s: Add test.
	* gas/testsuite/sysreg.d: Update.
This commit is contained in:
Yufeng Zhang 2013-11-18 11:34:43 +00:00
parent a203d9b72f
commit 18cf6de400
5 changed files with 20 additions and 5 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2013-11-18 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* config/tc-aarch64.c (parse_sys_reg): Support
S2_<op1>_<Cn>_<Cm>_<op2>.
2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
Revert

10
gas/config/tc-aarch64.c
View File

@ -3270,7 +3270,7 @@ parse_barrier (char **str)
Returns the encoding for the option, or PARSE_FAIL.
If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
static int
parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
@ -3295,7 +3295,7 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
return PARSE_FAIL;
else
{
/* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
/* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
registers. */
unsigned int op0, op1, cn, cm, op2;
if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
@ -3303,11 +3303,11 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
/* The architecture specifies the encoding space for implementation
defined registers as:
op0 op1 CRn CRm op2
11 xxx 1x11 xxxx xxx
1x xxx 1x11 xxxx xxx
For convenience GAS accepts a wider encoding space, as follows:
op0 op1 CRn CRm op2
11 xxx xxxx xxxx xxx */
if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
1x xxx xxxx xxxx xxx */
if ((op0 != 2 && op0 != 3) || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
return PARSE_FAIL;
value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
}

5
gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2013-11-18 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* gas/testsuite/sysreg.s: Add test.
* gas/testsuite/sysreg.d: Update.
2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
Revert

2
gas/testsuite/gas/aarch64/sysreg.d
View File

@ -26,3 +26,5 @@ Disassembly of section \.text:
48: d538cc00 mrs x0, s3_0_c12_c12_0
4c: d5384600 mrs x0, s3_0_c4_c6_0
50: d5184600 msr s3_0_c4_c6_0, x0
54: d5310300 mrs x0, s2_1_c0_c3_0
58: d5110300 msr s2_1_c0_c3_0, x0

3
gas/testsuite/gas/aarch64/sysreg.s
View File

@ -26,3 +26,6 @@
mrs x0, s3_0_c12_c12_0
mrs x0, s3_0_c4_c6_0
msr s3_0_c4_c6_0, x0
mrs x0, s2_1_c0_c3_0
msr s2_1_c0_c3_0, x0