gas/
* config/tc-aarch64.c (parse_sys_reg): Support S2_<op1>_<Cn>_<Cm>_<op2>. gas/testsuite/ * gas/testsuite/sysreg.s: Add test. * gas/testsuite/sysreg.d: Update.
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@ -1,3 +1,8 @@
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2013-11-18 Zhenqiang Chen <zhenqiang.chen@linaro.org>
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* config/tc-aarch64.c (parse_sys_reg): Support
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S2_<op1>_<Cn>_<Cm>_<op2>.
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2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
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Revert
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@ -3270,7 +3270,7 @@ parse_barrier (char **str)
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Returns the encoding for the option, or PARSE_FAIL.
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If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
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implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
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implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
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static int
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parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
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@ -3295,7 +3295,7 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
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return PARSE_FAIL;
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else
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{
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/* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
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/* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
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registers. */
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unsigned int op0, op1, cn, cm, op2;
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if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
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@ -3303,11 +3303,11 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
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/* The architecture specifies the encoding space for implementation
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defined registers as:
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op0 op1 CRn CRm op2
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11 xxx 1x11 xxxx xxx
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1x xxx 1x11 xxxx xxx
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For convenience GAS accepts a wider encoding space, as follows:
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op0 op1 CRn CRm op2
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11 xxx xxxx xxxx xxx */
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if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
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1x xxx xxxx xxxx xxx */
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if ((op0 != 2 && op0 != 3) || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
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return PARSE_FAIL;
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value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
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}
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@ -1,3 +1,8 @@
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2013-11-18 Zhenqiang Chen <zhenqiang.chen@linaro.org>
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* gas/testsuite/sysreg.s: Add test.
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* gas/testsuite/sysreg.d: Update.
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2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
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Revert
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@ -26,3 +26,5 @@ Disassembly of section \.text:
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48: d538cc00 mrs x0, s3_0_c12_c12_0
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4c: d5384600 mrs x0, s3_0_c4_c6_0
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50: d5184600 msr s3_0_c4_c6_0, x0
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54: d5310300 mrs x0, s2_1_c0_c3_0
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58: d5110300 msr s2_1_c0_c3_0, x0
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@ -26,3 +26,6 @@
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mrs x0, s3_0_c12_c12_0
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mrs x0, s3_0_c4_c6_0
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msr s3_0_c4_c6_0, x0
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mrs x0, s2_1_c0_c3_0
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msr s2_1_c0_c3_0, x0
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