Allow lock on cmpxch16b.
gas/testsuite/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/lock-1.s: Add cmpxchg16b test. * gas/i386/lock-1-intel.d: Updated. * gas/i386/lock-1.d: Likewise. opcodes/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add IsLockable to cmpxch16b. * i386-tbl.h: Regenerated.
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@ -1,3 +1,9 @@
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2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/lock-1.s: Add cmpxchg16b test.
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* gas/i386/lock-1-intel.d: Updated.
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* gas/i386/lock-1.d: Likewise.
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2009-11-19 Nick Clifton <nickc@redhat.com>
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PR binutils/10924
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@ -22,6 +22,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64
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[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax
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[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b OWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\]
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@ -51,6 +52,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64
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[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax
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[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b OWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\]
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[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\]
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@ -21,6 +21,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\)
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[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\)
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[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\)
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[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b \(%rbx\)
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[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\)
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[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\)
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[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\)
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@ -50,6 +51,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\)
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[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\)
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[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\)
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[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b \(%rbx\)
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[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\)
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[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\)
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[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\)
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@ -16,6 +16,7 @@ foo:
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lock bts $0x64, (%rbx)
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lock cmpxchg %eax,(%rbx)
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lock cmpxchg8b (%rbx)
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lock cmpxchg16b (%rbx)
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lock decl (%rbx)
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lock incl (%rbx)
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lock negl (%rbx)
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@ -47,6 +48,7 @@ foo:
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lock bts DWORD PTR [rbx],0x64
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lock cmpxchg DWORD PTR [rbx],eax
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lock cmpxchg8b QWORD PTR [rbx]
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lock cmpxchg16b OWORD PTR [rbx]
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lock dec DWORD PTR [rbx]
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lock inc DWORD PTR [rbx]
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lock neg DWORD PTR [rbx]
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@ -1,3 +1,8 @@
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2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Add IsLockable to cmpxch16b.
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* i386-tbl.h: Regenerated.
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2009-11-19 Nick Clifton <nickc@redhat.com>
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PR binutils/10924
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@ -1505,7 +1505,7 @@ addsubpd, 2, 0x66d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|
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addsubpd, 2, 0x660fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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addsubps, 2, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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addsubps, 2, 0xf20fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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cmpxchg16b, 1, 0xfc7, 0x1, 2, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX, { Oword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
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cmpxchg16b, 1, 0xfc7, 0x1, 2, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX|IsLockable, { Oword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
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fisttp, 1, 0xdf, 0x1, 1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|NoAVX, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fisttp, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fisttpll, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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@ -14962,7 +14962,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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