* m32r-sim.h (m32r_trap): Update prototype.
* traps.c (m32r_trap): New arg `pc'. * sem.c,sem-switch.c: Regenerated. * cpux.h,readx.c,semx.c: Regenerated.
This commit is contained in:
Doug Evans
parent
3efbfbebdc
commit
190659a22d
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@ -1,5 +1,33 @@
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Wed Sep 9 15:29:36 1998 Doug Evans <devans@canuck.cygnus.com>
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* m32r-sim.h (m32r_trap): Update prototype.
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* traps.c (m32r_trap): New arg `pc'.
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* sem.c,sem-switch.c: Regenerated.
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start-sanitize-m32rx
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* cpux.h,readx.c,semx.c: Regenerated.
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end-sanitize-m32rx
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Mon Aug 3 12:59:17 1998 Doug Evans <devans@seba.cygnus.com>
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Rename cpu m32r to m32rb to distinguish from architecture name.
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* Makefile.in (mloop.c): cpu m32r renamed to m32rb.
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(stamp-cpu): Ditto.
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* sim-main.h (WANT_CPU_M32RB): Renamed from WANT_CPU_M32R.
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* tconfig.in (WANT_CPU_M32RB): Ditto.
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* m32r.c (WANT_CPU_M32RB): Ditto.
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(*): m32r_ cpu fns renamed to m32rb_.
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* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Update.
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* arch.h,arch.c: Regenerate.
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* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
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* sem-switch.c,sem.c: Regenerate.
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* sim-if.c (sim_open): Don't allocate memory on top of any user
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specified memory.
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(h_gr_get,h_gr_set): Delete.
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* sim-main.h (h_gr_get,h_gr_set): Delete.
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* traps.c (m32r_trap): Replace calls to h_gr_[gs]et with
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a_m32r_h_gr_[gs]et.
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* Makefile.in (INCLUDE_DEPS): Add include/opcode/cgen.h.
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* sim-if.c (sim_open): Open opcode table.
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@ -100,6 +100,7 @@ typedef struct {
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#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
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} M32RX_CPU_DATA;
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/* Cover fns for register access. */
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USI m32rx_h_pc_get (SIM_CPU *);
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void m32rx_h_pc_set (SIM_CPU *, USI);
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SI m32rx_h_gr_get (SIM_CPU *, UINT);
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@ -285,19 +286,11 @@ struct argbuf {
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UINT f_acc;
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UINT f_r2;
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} fmt_machi_a;
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struct { /* e.g. macwhi $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_macwhi;
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struct { /* e.g. mulhi $src1,$src2,$acc */
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UINT f_r1;
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UINT f_acc;
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UINT f_r2;
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} fmt_mulhi_a;
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struct { /* e.g. mulwhi $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_mulwhi;
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struct { /* e.g. mv $dr,$sr */
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UINT f_r1;
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UINT f_r2;
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@ -395,6 +388,10 @@ struct argbuf {
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UINT f_r1;
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UINT f_r2;
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} fmt_macwu1;
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struct { /* e.g. msblo $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_msblo;
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struct { /* e.g. mulwu1 $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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@ -959,20 +956,6 @@ struct scache {
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f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_MACWHI_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_FMT_MACWHI_CODE \
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length = 2; \
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f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_MULHI_A_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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@ -989,20 +972,6 @@ struct scache {
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f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_MULWHI_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_FMT_MULWHI_CODE \
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length = 2; \
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f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_MV_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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@ -1363,6 +1332,20 @@ struct scache {
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f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_MSBLO_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_FMT_MSBLO_CODE \
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length = 2; \
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f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_MULWU1_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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@ -1544,19 +1527,10 @@ struct parexec {
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SI src1;
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SI src2;
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} fmt_machi_a;
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struct { /* e.g. macwhi $src1,$src2 */
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DI accum;
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SI src1;
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SI src2;
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} fmt_macwhi;
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struct { /* e.g. mulhi $src1,$src2,$acc */
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SI src1;
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SI src2;
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} fmt_mulhi_a;
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struct { /* e.g. mulwhi $src1,$src2 */
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SI src1;
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SI src2;
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} fmt_mulwhi;
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struct { /* e.g. mv $dr,$sr */
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SI sr;
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} fmt_mv;
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@ -1629,8 +1603,8 @@ struct parexec {
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SI src1;
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} fmt_st_plus;
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struct { /* e.g. trap $uimm4 */
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USI pc;
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USI h_cr_0;
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SI pc;
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SI uimm4;
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} fmt_trap;
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struct { /* e.g. unlock $src1,@$src2 */
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@ -1654,6 +1628,11 @@ struct parexec {
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SI src1;
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SI src2;
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} fmt_macwu1;
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struct { /* e.g. msblo $src1,$src2 */
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DI accum;
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SI src1;
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SI src2;
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} fmt_msblo;
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struct { /* e.g. mulwu1 $src1,$src2 */
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SI src1;
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SI src2;
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@ -33,12 +33,25 @@ typedef struct {
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unsigned int fillnop_count;
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/* number of parallel insns */
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unsigned int parallel_count;
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/* FIXME: generalize this to handle all insn lengths, move to common. */
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/* number of short insns, not including parallel ones */
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unsigned int short_count;
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/* number of long insns */
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unsigned int long_count;
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/* Working area for computing cycle counts. */
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unsigned long insn_cycles;
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unsigned long cti_stall;
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unsigned long load_stall;
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unsigned long biggest_cycles;
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} M32R_MISC_PROFILE;
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/* Initialize the working area. */
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void m32r_init_insn_cycles (SIM_CPU *, int);
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/* Update the totals for the insn. */
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void m32r_record_insn_cycles (SIM_CPU *, int);
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/* This is invoked by the nop pattern in the .cpu file. */
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#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
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do { \
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@ -78,7 +91,9 @@ do { \
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- NEW_PC_SKIP, sc/snc insn
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- NEW_PC_2, 2 byte non-branch non-sc/snc insn
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- NEW_PC_4, 4 byte non-branch insn
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The special values have bit 1 set so it's cheap to distinguish them. */
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The special values have bit 1 set so it's cheap to distinguish them.
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This works because all cti's are defined to zero the bottom two bits. */
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/* FIXME: replace 0xffff0001 with 1? */
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#define NEW_PC_BASE 0xffff0001
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#define NEW_PC_SKIP NEW_PC_BASE
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#define NEW_PC_2 (NEW_PC_BASE + 2)
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@ -154,6 +169,6 @@ extern device m32r_devices;
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struct _device { int foo; };
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/* Handle the trap insn. */
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USI m32r_trap (SIM_CPU *, int);
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USI m32r_trap (SIM_CPU *, PCADDR, int);
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#endif /* M32R_SIM_H */
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@ -852,8 +852,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
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EXTRACT_FMT_TRAP_CODE
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/* Fetch the input operands for the semantic handler. */
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OPRND (pc) = CPU (h_pc);
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OPRND (h_cr_0) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 0));
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OPRND (pc) = CPU (h_pc);
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OPRND (uimm4) = f_uimm4;
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#undef OPRND
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}
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File diff suppressed because it is too large
Load Diff
1532
sim/m32r/sem.c
1532
sim/m32r/sem.c
File diff suppressed because it is too large
Load Diff
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@ -3853,7 +3853,7 @@ do {
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TRACE_RESULT (current_cpu, "cr-0", 'x', opval);
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}
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{
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SI opval = m32r_trap (current_cpu, OPRND (uimm4));
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SI opval = m32r_trap (current_cpu, OPRND (pc), OPRND (uimm4));
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BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
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taken_p = 1;
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TRACE_RESULT (current_cpu, "pc", 'x', opval);
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@ -103,7 +103,7 @@ syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
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Preprocessing like saving the various registers has already been done. */
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USI
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a_m32r_trap (SIM_CPU *current_cpu, int num)
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m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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host_callback *cb = STATE_CALLBACK (sd);
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@ -115,7 +115,7 @@ a_m32r_trap (SIM_CPU *current_cpu, int num)
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{
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/* First try sim-break.c. If it's a breakpoint the simulator "owns"
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it doesn't return. Otherwise it returns and let's us try. */
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sim_handle_breakpoint (sd, current_cpu, sim_pc_get (current_cpu));
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sim_handle_breakpoint (sd, current_cpu, pc);
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/* Fall through. */
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}
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#endif
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@ -135,25 +135,24 @@ a_m32r_trap (SIM_CPU *current_cpu, int num)
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CB_SYSCALL s;
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CB_SYSCALL_INIT (&s);
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s.func = h_gr_get (current_cpu, 0);
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s.arg1 = h_gr_get (current_cpu, 1);
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s.arg2 = h_gr_get (current_cpu, 2);
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s.arg3 = h_gr_get (current_cpu, 3);
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s.func = a_m32r_h_gr_get (current_cpu, 0);
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s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
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s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
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s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
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if (s.func == TARGET_SYS_exit)
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{
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sim_engine_halt (sd, current_cpu, NULL, sim_pc_get (current_cpu),
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sim_exited, s.arg1);
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
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}
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s.p1 = (PTR) sd;
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s.p2 = (PTR) current_cpu;
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s.read_mem = syscall_read_mem;
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s.write_mem = syscall_write_mem;
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cb_syscall (STATE_CALLBACK (sd), &s);
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h_gr_set (current_cpu, 2, s.errcode);
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h_gr_set (current_cpu, 0, s.result);
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h_gr_set (current_cpu, 1, s.result2);
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cb_syscall (cb, &s);
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a_m32r_h_gr_set (current_cpu, 2, s.errcode);
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a_m32r_h_gr_set (current_cpu, 0, s.result);
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a_m32r_h_gr_set (current_cpu, 1, s.result2);
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break;
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}
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@ -170,5 +169,5 @@ a_m32r_trap (SIM_CPU *current_cpu, int num)
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}
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/* Fake an "rte" insn. */
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return (sim_pc_get (current_cpu) & -4) + 4;
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return (pc & -4) + 4;
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}
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