sim: bfin: import optimizations from 32bit test into 16bit test
The 32bit allopcodes test had quite a bit of optimization added to it so that it ran in a reasonable amount of time out of uncached memory. Port those changes over to the 16bit test so the two share common code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
410bbc9498
commit
191a54be54
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@ -1,3 +1,7 @@
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2012-03-18 Mike Frysinger <vapier@gentoo.org>
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* se_all16bitopcodes.S: Merge code from se_all32bitopcodes.S.
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2011-09-28 Mike Frysinger <vapier@gentoo.org>
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* vit_max2.s: New tests for parallel VIT_MAX insns.
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@ -31,24 +31,23 @@
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SYSCFG = R0;
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/* Lower to the code we want to single step through */
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loadsym R1, _usr;
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RETI = R1;
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loadsym P1, _usr;
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RETI = P1;
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/* set up pointers to valid data (32Meg), to reduce address violations */
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init_p_regs 0x2000000;
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init_i_regs 0x2000000;
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init_b_regs 0x2000000;
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init_l_regs 0;
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imm32 fp, 0x2000000;
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usp = p0;
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.macro reset_regs
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imm32 r0, 0x2000000;
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l0 = 0; l1 = 0; l2 = 0; l3 = 0;
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p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0;
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usp = r0; fp = r0;
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i0 = r0; i1 = r0; i2 = r0; i3 = r0;
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b0 = r0; b1 = r0; b2 = r0; b3 = r0;
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.endm
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reset_regs
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RTI;
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.align 4;
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_usr:
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.dd 0x0000;
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jump fail_lvl;
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_evx:
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/* Make sure exception reason is single step */
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R3 = SEQSTAT;
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@ -56,12 +55,14 @@ _evx:
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R3 = R3 & R4;
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/* find a match */
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loadsym P0, _usr;
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loadsym P2, _location;
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P1 = [P2];
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R0 = W[P0];
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loadsym P5, _usr;
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loadsym P4, _location;
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R2 = W[P5];
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P1 = [P4];
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R0 = R2;
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_match:
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P2 = P1;
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R7 = W[P1++];
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R6 = W[P1++];
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R5 = W[P1++];
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@ -69,7 +70,7 @@ _match:
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/* is this the end of the table? */
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R4 = 0;
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CC = R4 == R7;
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IF CC jump _legal_instruction;
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IF CC jump _new_instruction;
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/* is the opcode (R0) greater than the 2nd entry in the table (R6) */
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/* if so look at the next line in the table */
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@ -88,14 +89,38 @@ _match:
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_match_done:
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/* back up, and store the location to search next */
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R0 = P1;
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/* 3 back, * word/byte) */
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R0 += (-3 * 2);
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[P2] = R0;
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[P4] = P2;
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/* it matches, so fall through */
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jump _next_instruction;
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_new_instruction:
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jump _legal_instruction;
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/* output the insn (R0) and excause (R3) if diff from last */
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loadsym P0, _last_excause;
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R2 = [P0];
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CC = R2 == R3;
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IF CC jump _next_instruction;
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[P0] = R3;
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.ifdef BFIN_JTAG_xxxxx
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R1 = R0;
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R0 = 0x4;
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call __emu_out;
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R0 = R1 << 16;
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R0 = R0 | R3;
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call __emu_out;
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.else
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loadsym P0, _next_location;
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P1 = [P0];
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W[P1++] = R0;
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W[P1++] = R3;
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[P0] = P1;
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.endif
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jump _next_instruction;
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_legal_instruction:
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R4 = 0x10;
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CC = R3 == R4;
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@ -104,31 +129,29 @@ _legal_instruction:
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_next_instruction:
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/* increment, and go again. */
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loadsym P0, _usr;
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R0 = W[P0];
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R0 = R2;
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R0 += 1;
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W[P0] = R0;
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/* finish once we hit the 32bit limit */
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R1 = 0xC000 (Z);
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CC = R1 == R0;
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IF CC JUMP pass_lvl;
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W[P5] = R0;
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/* Make sure the opcode isn't in a write buffer */
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SSYNC;
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loadsym R1, _usr
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R1 = P5;
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RETX = R1;
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/* set up pointers to valid data (32Meg), to reduce address violations */
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init_p_regs 0x2000000;
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init_i_regs 0x2000000;
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init_b_regs 0x2000000;
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init_l_regs 0;
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imm32 fp, 0x2000000;
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usp = p0;
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RETS = p0;
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RETN = p0;
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RETE = p0;
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RETI = p0;
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reset_regs
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RETS = r0;
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RETN = r0;
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RETE = r0;
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RETI = r0;
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RTX;
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pass_lvl:
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@ -136,10 +159,20 @@ pass_lvl:
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fail_lvl:
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dbg_fail;
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.section .text.usr
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.align 4
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_usr:
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.dw 0x0000;
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loadsym P0, fail_lvl;
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JUMP (P0);
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/* this table must be sorted, and end with zero */
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.data
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.align 4;
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_last_excause:
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.dd 0xffff
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_next_location:
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.dd _table_end
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_location:
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.dd 0
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_table:
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@ -442,3 +475,4 @@ _table:
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.dw 0x9ef0, 0x9eff, 0x21
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.dw 0x9f70, 0x9f7f, 0x21
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.dw 0x0000, 0x0000, 0x00
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_table_end:
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