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* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define. 

(EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define.
	(EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype
	instead of CGEN_INSN_INT.
plus, cgen files: Regenerate.
This commit is contained in:
Doug Evans 2009-11-23 04:12:17 +00:00
parent 1fbb9298a4
commit 197fa1aa2c
43 changed files with 1072 additions and 957 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
sim/ChangeLog
View File

@ -1,3 +1,13 @@
2009-11-22 Doug Evans <dje@sebabeach.org>
* cris/cpuall.h: Regenerate.
* cris/cpuv10.h: Regenerate.
* cris/cpuv32.h: Regenerate.
* cris/decodev10.c: Regenerate.
* cris/decodev10.h: Regenerate.
* cris/decodev32.c: Regenerate.
* cris/decodev32.h: Regenerate.
2009-11-12 Tristan Gingold <gingold@adacore.com>
* avr/interp.c (sim_write): Allow byte access.

5
sim/common/ChangeLog
View File

@ -1,5 +1,10 @@
2009-11-22 Doug Evans <dje@sebabeach.org>
* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define.
(EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define.
(EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype
instead of CGEN_INSN_INT.
* cgen-trace.h (trace_extract): Add cast to fix warning.
2009-11-05 Doug Evans <dje@sebabeach.org>

26
sim/common/cgen-engine.h
View File

@ -17,9 +17,11 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This file must be included after eng.h and before ${cpu}.h.
/* This file is included by ${cpu}.h.
It needs CGEN_INSN_WORD which is defined by ${cpu}.h.
??? A lot of this could be moved to genmloop.sh to be put in eng.h
and thus remove some conditional compilation. Worth it? */
and thus remove some conditional compilation. We'd still need
CGEN_INSN_WORD though. */
/* Semantic functions come in six versions on two axes:
fast/full-featured, and using one of the simple/scache/compilation engines.
@ -62,12 +64,26 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#define EXTRACT_LSB0_UINT(val, total, start, length) \
(((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \
>> ((sizeof (UINT) * 8) - (length)))
#define EXTRACT_MSB0_LGSINT(val, total, start, length) \
(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \
>> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
#define EXTRACT_MSB0_LGUINT(val, total, start, length) \
(((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \
>> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
#define EXTRACT_LSB0_LGSINT(val, total, start, length) \
(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \
>> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
#define EXTRACT_LSB0_LGUINT(val, total, start, length) \
(((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \
>> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
/* Semantic routines. */
/* Type of the machine generated extraction fns. */
/* ??? No longer used. */
typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_INT, ARGBUF *);
typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_WORD, ARGBUF *);
/* Type of the machine generated semantic fns. */
@ -89,9 +105,9 @@ typedef unsigned int SEM_STATUS;
/* Instruction fields are extracted by the semantic routine.
??? TODO: multi word insns. */
#if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_INT);
typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_WORD);
#else
typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_INT);
typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_WORD);
#endif
#endif

5
sim/cris/cpuall.h
View File

@ -29,35 +29,30 @@ This file is part of the GNU simulators.
#ifdef WANT_CPU_CRISV0F
#include "engv0.h"
#include "cgen-engine.h"
#include "cpuv0.h"
#include "decodev0.h"
#endif
#ifdef WANT_CPU_CRISV3F
#include "engv3.h"
#include "cgen-engine.h"
#include "cpuv3.h"
#include "decodev3.h"
#endif
#ifdef WANT_CPU_CRISV8F
#include "engv8.h"
#include "cgen-engine.h"
#include "cpuv8.h"
#include "decodev8.h"
#endif
#ifdef WANT_CPU_CRISV10F
#include "engv10.h"
#include "cgen-engine.h"
#include "cpuv10.h"
#include "decodev10.h"
#endif
#ifdef WANT_CPU_CRISV32F
#include "engv32.h"
#include "cgen-engine.h"
#include "cpuv32.h"
#include "decodev32.h"
#endif

6
sim/cris/cpuv10.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

6
sim/cris/cpuv32.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

222
sim/cris/decodev10.c
View File

@ -316,14 +316,14 @@ crisv10f_init_idesc_table (SIM_CPU *cpu)
const IDESC *
crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn,
CGEN_INSN_WORD base_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
CRISV10F_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 4) & (255 << 0)));
@ -2413,7 +2413,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -2441,7 +2441,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_d_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -2469,7 +2469,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movepcr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_moveq.f
UINT f_operand2;
@ -2493,7 +2493,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_moveq:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_moveq.f
UINT f_operand2;
INT f_s6;
@ -2520,7 +2520,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -2548,7 +2548,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -2578,7 +2578,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -2608,7 +2608,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecdr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -2638,7 +2638,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movscbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
UINT f_operand2;
INT f_indir_pc__byte;
@ -2668,7 +2668,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movscwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
UINT f_operand2;
INT f_indir_pc__word;
@ -2698,7 +2698,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movucbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
UINT f_operand2;
INT f_indir_pc__byte;
@ -2728,7 +2728,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movucwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
UINT f_operand2;
INT f_indir_pc__word;
@ -2758,7 +2758,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addq:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addq.f
UINT f_operand2;
UINT f_u6;
@ -2786,7 +2786,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_r_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -2814,7 +2814,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2846,7 +2846,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2878,7 +2878,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2910,7 +2910,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -2940,7 +2940,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -2970,7 +2970,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcdr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -3000,7 +3000,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpq:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_andq.f
UINT f_operand2;
INT f_s6;
@ -3027,7 +3027,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpucbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -3057,7 +3057,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpucwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -3087,7 +3087,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3119,7 +3119,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3151,7 +3151,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3183,7 +3183,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3215,7 +3215,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3247,7 +3247,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_sprv10:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
UINT f_operand2;
UINT f_operand1;
@ -3275,7 +3275,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_spr_rv10:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
UINT f_operand2;
UINT f_operand1;
@ -3303,7 +3303,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ret_type:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
UINT f_operand2;
@ -3327,7 +3327,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_sprv10:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
UINT f_operand2;
UINT f_memmode;
@ -3359,7 +3359,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_c_sprv10_p5:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f
UINT f_operand2;
INT f_indir_pc__word;
@ -3389,7 +3389,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_c_sprv10_p9:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -3419,7 +3419,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_spr_mv10:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
UINT f_operand2;
UINT f_memmode;
@ -3464,7 +3464,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movem_r_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movem_r_m.f
UINT f_operand2;
UINT f_memmode;
@ -3512,7 +3512,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movem_m_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movem_m_r.f
UINT f_operand2;
UINT f_memmode;
@ -3559,7 +3559,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movem_m_pc:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movem_m_r.f
UINT f_memmode;
UINT f_operand1;
@ -3602,7 +3602,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -3631,7 +3631,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_d_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -3660,7 +3660,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3693,7 +3693,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3726,7 +3726,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3759,7 +3759,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -3790,7 +3790,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -3821,7 +3821,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcdr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcdr.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -3852,7 +3852,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcpc:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
INT f_indir_pc__dword;
/* Contents of trailing part of insn. */
@ -3878,7 +3878,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_adds_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3911,7 +3911,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_adds_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3944,7 +3944,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addscbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -3975,7 +3975,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addscwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -4025,7 +4025,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_operand1;
@ -4054,7 +4054,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_neg_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -4082,7 +4082,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_neg_d_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -4110,7 +4110,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
UINT f_memmode;
UINT f_operand1;
@ -4138,7 +4138,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
UINT f_memmode;
UINT f_operand1;
@ -4166,7 +4166,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
UINT f_memmode;
UINT f_operand1;
@ -4194,7 +4194,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -4226,7 +4226,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -4258,7 +4258,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -4290,7 +4290,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_muls_b:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -4320,7 +4320,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mstep:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -4349,7 +4349,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_dstep:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -4378,7 +4378,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -4407,7 +4407,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_d_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -4436,7 +4436,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -4469,7 +4469,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -4502,7 +4502,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -4535,7 +4535,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcbr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -4566,7 +4566,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcwr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -4597,7 +4597,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcdr:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcdr.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -4628,7 +4628,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andq:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_andq.f
UINT f_operand2;
INT f_s6;
@ -4656,7 +4656,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_swap:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
UINT f_operand2;
UINT f_operand1;
@ -4684,7 +4684,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_asrq:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_asrq.f
UINT f_operand2;
UINT f_u5;
@ -4712,7 +4712,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lsrr_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -4741,7 +4741,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lsrr_d_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -4770,7 +4770,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btst:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -4798,7 +4798,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btstq:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_asrq.f
UINT f_operand2;
UINT f_u5;
@ -4825,7 +4825,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_setf:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_setf.f
UINT f_operand2;
UINT f_operand1;
@ -4846,7 +4846,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcc_b:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_b.f
UINT f_operand2;
UINT f_disp9_lo;
@ -4882,7 +4882,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ba_b:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_b.f
UINT f_disp9_lo;
INT f_disp9_hi;
@ -4915,7 +4915,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcc_w:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_w.f
SI f_indir_pc__word_pcrel;
UINT f_operand2;
@ -4944,7 +4944,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ba_w:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_w.f
SI f_indir_pc__word_pcrel;
/* Contents of trailing part of insn. */
@ -4970,7 +4970,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jump_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
UINT f_operand2;
UINT f_operand1;
@ -4998,7 +4998,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jump_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
UINT f_operand2;
UINT f_memmode;
@ -5030,7 +5030,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jump_c:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -5060,7 +5060,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_break:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_break.f
UINT f_u4;
@ -5083,7 +5083,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -5116,7 +5116,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -5149,7 +5149,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -5182,7 +5182,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cb:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -5213,7 +5213,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cw:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -5244,7 +5244,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cd:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -5275,7 +5275,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_scc:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
UINT f_operand2;
UINT f_operand1;
@ -5302,7 +5302,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addoq:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addoq.f
UINT f_operand2;
INT f_s8;
@ -5329,7 +5329,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bdapqpc:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addoq.f
INT f_s8;
@ -5352,7 +5352,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bdap_32_pc:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
INT f_indir_pc__dword;
/* Contents of trailing part of insn. */
@ -5378,7 +5378,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_pcplus_p0:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
UINT f_memmode;
@ -5401,7 +5401,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_spplus_p8:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
UINT f_memmode;
@ -5426,7 +5426,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_b_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -5458,7 +5458,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_w_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -5490,7 +5490,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_d_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -5522,7 +5522,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cb:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -5552,7 +5552,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cw:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -5582,7 +5582,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cd:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -5612,7 +5612,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_dip_m:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
UINT f_memmode;
UINT f_operand1;
@ -5640,7 +5640,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_dip_c:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
INT f_indir_pc__dword;
/* Contents of trailing part of insn. */
@ -5660,7 +5660,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi_acr_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_b_r.f
UINT f_operand2;
UINT f_operand1;
@ -5688,7 +5688,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_biap_pc_b_r:
{
const IDESC *idesc = &crisv10f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addoq.f
UINT f_operand2;

2
sim/cris/decodev10.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define CRISV10F_DECODE_H
extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT,
CGEN_INSN_WORD,
ARGBUF *);
extern void crisv10f_init_idesc_table (SIM_CPU *);
extern void crisv10f_sem_init_idesc_table (SIM_CPU *);

208
sim/cris/decodev32.c
View File

@ -320,14 +320,14 @@ crisv32f_init_idesc_table (SIM_CPU *cpu)
const IDESC *
crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn,
CGEN_INSN_WORD base_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
CRISV32F_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 4) & (255 << 0)));
@ -1923,7 +1923,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -1951,7 +1951,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -1979,7 +1979,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_moveq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_moveq.f
UINT f_operand2;
INT f_s6;
@ -2006,7 +2006,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -2034,7 +2034,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -2064,7 +2064,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -2094,7 +2094,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -2124,7 +2124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movscbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
UINT f_operand2;
INT f_indir_pc__byte;
@ -2154,7 +2154,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movscwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
UINT f_operand2;
INT f_indir_pc__word;
@ -2184,7 +2184,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movucbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
UINT f_operand2;
INT f_indir_pc__byte;
@ -2214,7 +2214,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movucwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
UINT f_operand2;
INT f_indir_pc__word;
@ -2244,7 +2244,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addq.f
UINT f_operand2;
UINT f_u6;
@ -2272,7 +2272,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_r_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -2300,7 +2300,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -2332,7 +2332,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -2364,7 +2364,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -2396,7 +2396,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -2426,7 +2426,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -2456,7 +2456,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -2486,7 +2486,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_andq.f
UINT f_operand2;
INT f_s6;
@ -2513,7 +2513,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpucbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -2543,7 +2543,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpucwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -2573,7 +2573,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2605,7 +2605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2637,7 +2637,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2669,7 +2669,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2701,7 +2701,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -2733,7 +2733,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_sprv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_operand1;
@ -2761,7 +2761,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_spr_rv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
UINT f_operand1;
@ -2789,7 +2789,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_sprv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_memmode;
@ -2821,7 +2821,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_c_sprv32_p2:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -2851,7 +2851,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_spr_mv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_memmode;
@ -2883,7 +2883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_ss_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_operand1;
@ -2910,7 +2910,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_ss:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
UINT f_operand1;
@ -2937,7 +2937,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movem_r_m_v32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
UINT f_operand2;
UINT f_memmode;
@ -2985,7 +2985,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movem_m_r_v32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
UINT f_operand2;
UINT f_memmode;
@ -3033,7 +3033,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -3062,7 +3062,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -3091,7 +3091,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3124,7 +3124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3157,7 +3157,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3190,7 +3190,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -3221,7 +3221,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -3252,7 +3252,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcdr.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -3283,7 +3283,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_adds_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3316,7 +3316,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_adds_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3349,7 +3349,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addscbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -3380,7 +3380,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addscwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -3411,7 +3411,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addc_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -3444,7 +3444,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lapc_d:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_lapc_d.f
SI f_indir_pc__dword_pcrel;
UINT f_operand2;
@ -3474,7 +3474,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lapcq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_lapcq.f
UINT f_operand2;
SI f_qo;
@ -3501,7 +3501,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -3530,7 +3530,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_neg_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -3558,7 +3558,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_neg_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -3586,7 +3586,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_memmode;
UINT f_operand1;
@ -3614,7 +3614,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_memmode;
UINT f_operand1;
@ -3642,7 +3642,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_memmode;
UINT f_operand1;
@ -3670,7 +3670,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -3702,7 +3702,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -3734,7 +3734,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -3766,7 +3766,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_muls_b:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -3796,7 +3796,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mcp:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
UINT f_operand1;
@ -3825,7 +3825,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_dstep:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -3854,7 +3854,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -3883,7 +3883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -3912,7 +3912,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3945,7 +3945,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -3978,7 +3978,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@ -4011,7 +4011,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -4042,7 +4042,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@ -4073,7 +4073,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcdr.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -4104,7 +4104,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_andq.f
UINT f_operand2;
INT f_s6;
@ -4132,7 +4132,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_swap:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_operand1;
@ -4160,7 +4160,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_asrq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_asrq.f
UINT f_operand2;
UINT f_u5;
@ -4188,7 +4188,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lsrr_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -4217,7 +4217,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lsrr_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@ -4246,7 +4246,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btst:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -4274,7 +4274,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btstq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_asrq.f
UINT f_operand2;
UINT f_u5;
@ -4301,7 +4301,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_setf:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_setf.f
UINT f_operand2;
UINT f_operand1;
@ -4423,7 +4423,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcc_b:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_b.f
UINT f_operand2;
UINT f_disp9_lo;
@ -4459,7 +4459,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ba_b:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_b.f
UINT f_disp9_lo;
INT f_disp9_hi;
@ -4492,7 +4492,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcc_w:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_w.f
SI f_indir_pc__word_pcrel;
UINT f_operand2;
@ -4521,7 +4521,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ba_w:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_w.f
SI f_indir_pc__word_pcrel;
/* Contents of trailing part of insn. */
@ -4547,7 +4547,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jas_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_operand1;
@ -4575,7 +4575,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jas_c:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -4605,7 +4605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jump_p:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
@ -4629,7 +4629,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bas_c:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bas_c.f
SI f_indir_pc__dword_pcrel;
UINT f_operand2;
@ -4659,7 +4659,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jasc_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_operand1;
@ -4687,7 +4687,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_break:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_break.f
UINT f_u4;
@ -4710,7 +4710,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cb:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -4741,7 +4741,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cw:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -4772,7 +4772,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cd:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -4803,7 +4803,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_scc:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_operand1;
@ -4830,7 +4830,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addoq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addoq.f
UINT f_operand2;
INT f_s8;
@ -4857,7 +4857,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -4889,7 +4889,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -4921,7 +4921,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@ -4953,7 +4953,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cb:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@ -4983,7 +4983,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cw:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@ -5013,7 +5013,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cd:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@ -5043,7 +5043,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi_acr_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@ -5071,7 +5071,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fidxi:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand1;

2
sim/cris/decodev32.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define CRISV32F_DECODE_H
extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT,
CGEN_INSN_WORD,
ARGBUF *);
extern void crisv32f_init_idesc_table (SIM_CPU *);
extern void crisv32f_sem_init_idesc_table (SIM_CPU *);

7
sim/frv/ChangeLog
View File

@ -1,3 +1,10 @@
2009-11-22 Doug Evans <dje@sebabeach.org>
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode.c: Regenerate.
* decode.h: Regenerate.
2009-11-03 Doug Evans <dje@sebabeach.org>
* arch.c: Regenerate.

6
sim/frv/cpu.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 8
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

1
sim/frv/cpuall.h
View File

@ -29,7 +29,6 @@ This file is part of the GNU simulators.
#ifdef WANT_CPU_FRVBF
#include "eng.h"
#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif

520
sim/frv/decode.c
View File

File diff suppressed because it is too large Load Diff

2
sim/frv/decode.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define FRVBF_DECODE_H
extern const IDESC *frvbf_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void frvbf_init_idesc_table (SIM_CPU *);
extern void frvbf_sem_init_idesc_table (SIM_CPU *);

7
sim/iq2000/ChangeLog
View File

@ -1,3 +1,10 @@
2009-11-22 Doug Evans <dje@sebabeach.org>
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode.c: Regenerate.
* decode.h: Regenerate.
2009-11-03 Doug Evans <dje@sebabeach.org>
* arch.c: Regenerate.

6
sim/iq2000/cpu.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

2
sim/iq2000/cpuall.h
View File

@ -29,14 +29,12 @@ This file is part of the GNU simulators.
#ifdef WANT_CPU_IQ2000BF
#include "eng.h"
#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif
#ifdef WANT_CPU_IQ10BF
#include "eng.h"
#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif

56
sim/iq2000/decode.c
View File

@ -256,14 +256,14 @@ iq2000bf_init_idesc_table (SIM_CPU *cpu)
const IDESC *
iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
IQ2000BF_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 26) & (63 << 0)));
@ -892,7 +892,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rt;
@ -915,7 +915,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -938,7 +938,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ram:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ram.f
UINT f_rs;
UINT f_rt;
@ -967,7 +967,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sll:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ram.f
UINT f_rt;
UINT f_rd;
@ -990,7 +990,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slmv:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ram.f
UINT f_rs;
UINT f_rt;
@ -1016,7 +1016,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slt:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rt;
@ -1039,7 +1039,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slti:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1062,7 +1062,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bbi:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
UINT f_rt;
@ -1091,7 +1091,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bbv:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
UINT f_rt;
@ -1120,7 +1120,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bgez:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
SI f_offset;
@ -1146,7 +1146,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bgezal:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
SI f_offset;
@ -1172,7 +1172,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jalr:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rd;
@ -1198,7 +1198,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jr:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
@ -1221,7 +1221,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lb:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1244,7 +1244,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lh:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1267,7 +1267,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lui:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rt;
UINT f_imm;
@ -1287,7 +1287,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1310,7 +1310,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sb:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1333,7 +1333,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sh:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1356,7 +1356,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1411,7 +1411,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andoui:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1434,7 +1434,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mrgb:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rt;
@ -1473,7 +1473,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1496,7 +1496,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sdw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@ -1519,7 +1519,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_j:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_j.f
USI f_jtarg;
@ -1542,7 +1542,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jal:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_j.f
USI f_jtarg;

2
sim/iq2000/decode.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define IQ2000BF_DECODE_H
extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void iq2000bf_init_idesc_table (SIM_CPU *);
extern void iq2000bf_sem_init_idesc_table (SIM_CPU *);

7
sim/lm32/ChangeLog
View File

@ -1,3 +1,10 @@
2009-11-22 Doug Evans <dje@sebabeach.org>
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode.c: Regenerate.
* decode.h: Regenerate.
2009-11-03 Doug Evans <dje@sebabeach.org>
* arch.c: Regenerate.

6
sim/lm32/cpu.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

1
sim/lm32/cpuall.h
View File

@ -29,7 +29,6 @@ This file is part of the GNU simulators.
#ifdef WANT_CPU_LM32BF
#include "eng.h"
#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif

46
sim/lm32/decode.c
View File

@ -174,14 +174,14 @@ lm32bf_init_idesc_table (SIM_CPU *cpu)
const IDESC *
lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
LM32BF_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 26) & (63 << 0)));
@ -361,7 +361,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_user.f
UINT f_r0;
UINT f_r1;
@ -384,7 +384,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r0;
UINT f_r1;
@ -407,7 +407,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andi:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_andi.f
UINT f_r0;
UINT f_r1;
@ -430,7 +430,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andhii:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_andi.f
UINT f_r0;
UINT f_r1;
@ -453,7 +453,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_b:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_be.f
UINT f_r0;
@ -470,7 +470,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bi:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bi.f
SI f_call;
@ -487,7 +487,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_be:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_be.f
UINT f_r0;
UINT f_r1;
@ -510,7 +510,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_call:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_be.f
UINT f_r0;
@ -527,7 +527,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_calli:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bi.f
SI f_call;
@ -544,7 +544,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_divu:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_user.f
UINT f_r0;
UINT f_r1;
@ -567,7 +567,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lb:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r0;
UINT f_r1;
@ -590,7 +590,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lh:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r0;
UINT f_r1;
@ -613,7 +613,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lw:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r0;
UINT f_r1;
@ -636,7 +636,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ori:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_andi.f
UINT f_r0;
UINT f_r1;
@ -659,7 +659,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_rcsr:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_rcsr.f
UINT f_csr;
UINT f_r2;
@ -679,7 +679,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sb:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r0;
UINT f_r1;
@ -702,7 +702,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sextb:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_user.f
UINT f_r0;
UINT f_r2;
@ -722,7 +722,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sh:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r0;
UINT f_r1;
@ -745,7 +745,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sw:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r0;
UINT f_r1;
@ -768,7 +768,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_user:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_user.f
UINT f_r0;
UINT f_r1;
@ -794,7 +794,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_wcsr:
{
const IDESC *idesc = &lm32bf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_wcsr.f
UINT f_csr;
UINT f_r1;

2
sim/lm32/decode.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define LM32BF_DECODE_H
extern const IDESC *lm32bf_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void lm32bf_init_idesc_table (SIM_CPU *);
extern void lm32bf_sem_init_idesc_table (SIM_CPU *);

13
sim/m32r/ChangeLog
View File

@ -1,3 +1,16 @@
2009-11-22 Doug Evans <dje@sebabeach.org>
* cpu.h: Regenerate.
* cpu2.h: Regenerate.
* cpux.h: Regenerate.
* cpuall.h: Regenerate.
* decode.c: Regenerate.
* decode.h: Regenerate.
* decode2.c: Regenerate.
* decode2.h: Regenerate.
* decodex.c: Regenerate.
* decodex.h: Regenerate.
2009-11-03 Doug Evans <dje@sebabeach.org>
* arch.c: Regenerate.

6
sim/m32r/cpu.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

6
sim/m32r/cpu2.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 2
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

3
sim/m32r/cpuall.h
View File

@ -29,21 +29,18 @@ This file is part of the GNU simulators.
#ifdef WANT_CPU_M32RBF
#include "eng.h"
#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif
#ifdef WANT_CPU_M32RXF
#include "engx.h"
#include "cgen-engine.h"
#include "cpux.h"
#include "decodex.h"
#endif
#ifdef WANT_CPU_M32R2F
#include "eng2.h"
#include "cgen-engine.h"
#include "cpu2.h"
#include "decode2.h"
#endif

6
sim/m32r/cpux.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 2
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

114
sim/m32r/decode.c
View File

@ -216,14 +216,14 @@ m32rbf_init_idesc_table (SIM_CPU *cpu)
const IDESC *
m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
M32RBF_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
@ -586,7 +586,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -617,7 +617,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add3:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -650,7 +650,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and3:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_and3.f
UINT f_r1;
UINT f_r2;
@ -683,7 +683,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_or3:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_and3.f
UINT f_r1;
UINT f_r2;
@ -716,7 +716,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r1;
INT f_simm8;
@ -745,7 +745,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addv:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -776,7 +776,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addv3:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -809,7 +809,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addx:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -840,7 +840,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bc8:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -863,7 +863,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bc24:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -886,7 +886,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beq:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_r1;
UINT f_r2;
@ -919,7 +919,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beqz:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_r2;
SI f_disp16;
@ -947,7 +947,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bl8:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -971,7 +971,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bl24:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -995,7 +995,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bra8:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1018,7 +1018,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bra24:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1041,7 +1041,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -1071,7 +1071,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpi:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r2;
INT f_simm16;
@ -1099,7 +1099,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_div:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -1130,7 +1130,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jl:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1156,7 +1156,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jmp:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1181,7 +1181,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1211,7 +1211,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld_d:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1244,7 +1244,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldb:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1274,7 +1274,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldb_d:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1307,7 +1307,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldh:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1337,7 +1337,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldh_d:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1370,7 +1370,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld_plus:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1401,7 +1401,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld24:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld24.f
UINT f_r1;
UINT f_uimm24;
@ -1429,7 +1429,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldi8:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r1;
INT f_simm8;
@ -1457,7 +1457,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldi16:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
INT f_simm16;
@ -1485,7 +1485,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lock:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1515,7 +1515,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_machi:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -1545,7 +1545,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mulhi:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -1575,7 +1575,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mv:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1605,7 +1605,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvfachi:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_seth.f
UINT f_r1;
@ -1630,7 +1630,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvfc:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1658,7 +1658,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvtachi:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
@ -1683,7 +1683,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvtc:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1756,7 +1756,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_seth:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_seth.f
UINT f_r1;
UINT f_hi16;
@ -1784,7 +1784,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sll3:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1817,7 +1817,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slli:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_slli.f
UINT f_r1;
UINT f_uimm5;
@ -1846,7 +1846,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -1876,7 +1876,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st_d:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -1909,7 +1909,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -1939,7 +1939,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb_d:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -1972,7 +1972,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2002,7 +2002,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth_d:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -2035,7 +2035,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st_plus:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2066,7 +2066,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_trap:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_trap.f
UINT f_uimm4;
@ -2089,7 +2089,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_unlock:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2119,7 +2119,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_clrpsw:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
@ -2136,7 +2136,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_setpsw:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
@ -2153,7 +2153,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bset:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;
@ -2184,7 +2184,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btst:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;

2
sim/m32r/decode.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define M32RBF_DECODE_H
extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void m32rbf_init_idesc_table (SIM_CPU *);
extern void m32rbf_sem_init_idesc_table (SIM_CPU *);

138
sim/m32r/decode2.c
View File

@ -259,14 +259,14 @@ m32r2f_init_idesc_table (SIM_CPU *cpu)
const IDESC *
m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
M32R2F_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
@ -775,7 +775,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -806,7 +806,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add3:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -839,7 +839,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and3:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_and3.f
UINT f_r1;
UINT f_r2;
@ -872,7 +872,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_or3:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_and3.f
UINT f_r1;
UINT f_r2;
@ -905,7 +905,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r1;
INT f_simm8;
@ -934,7 +934,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addv:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -965,7 +965,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addv3:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -998,7 +998,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addx:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -1029,7 +1029,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bc8:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1052,7 +1052,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bc24:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1075,7 +1075,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beq:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_r1;
UINT f_r2;
@ -1108,7 +1108,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beqz:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_r2;
SI f_disp16;
@ -1136,7 +1136,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bl8:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1160,7 +1160,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bl24:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1184,7 +1184,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcl8:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1208,7 +1208,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcl24:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1232,7 +1232,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bra8:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1255,7 +1255,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bra24:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1278,7 +1278,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -1308,7 +1308,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpi:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r2;
INT f_simm16;
@ -1336,7 +1336,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpz:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r2;
@ -1361,7 +1361,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_div:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -1392,7 +1392,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jc:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1417,7 +1417,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jl:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1443,7 +1443,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jmp:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1468,7 +1468,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1498,7 +1498,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld_d:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1531,7 +1531,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldb:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1561,7 +1561,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldb_d:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1594,7 +1594,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldh:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1624,7 +1624,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldh_d:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1657,7 +1657,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld_plus:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1688,7 +1688,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld24:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld24.f
UINT f_r1;
UINT f_uimm24;
@ -1716,7 +1716,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldi8:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r1;
INT f_simm8;
@ -1744,7 +1744,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldi16:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
INT f_simm16;
@ -1772,7 +1772,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lock:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1802,7 +1802,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_machi_a:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_machi_a.f
UINT f_r1;
UINT f_acc;
@ -1835,7 +1835,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mulhi_a:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_machi_a.f
UINT f_r1;
UINT f_acc;
@ -1868,7 +1868,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mv:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1898,7 +1898,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvfachi_a:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
UINT f_r1;
UINT f_accs;
@ -1926,7 +1926,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvfc:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1954,7 +1954,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvtachi_a:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
UINT f_r1;
UINT f_accs;
@ -1982,7 +1982,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvtc:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -2023,7 +2023,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_rac_dsi:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
UINT f_accd;
UINT f_accs;
@ -2065,7 +2065,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_seth:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_seth.f
UINT f_r1;
UINT f_hi16;
@ -2093,7 +2093,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sll3:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -2126,7 +2126,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slli:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_slli.f
UINT f_r1;
UINT f_uimm5;
@ -2155,7 +2155,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2185,7 +2185,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st_d:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -2218,7 +2218,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2248,7 +2248,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb_d:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -2281,7 +2281,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2311,7 +2311,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth_d:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -2344,7 +2344,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st_plus:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2375,7 +2375,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth_plus:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2406,7 +2406,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb_plus:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2437,7 +2437,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_trap:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_trap.f
UINT f_uimm4;
@ -2460,7 +2460,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_unlock:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2490,7 +2490,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_satb:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -2520,7 +2520,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sat:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -2563,7 +2563,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_macwu1:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2593,7 +2593,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_msblo:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2623,7 +2623,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mulwu1:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2666,7 +2666,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_clrpsw:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
@ -2683,7 +2683,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_setpsw:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
@ -2700,7 +2700,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bset:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;
@ -2731,7 +2731,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btst:
{
const IDESC *idesc = &m32r2f_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;

2
sim/m32r/decode2.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define M32R2F_DECODE_H
extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void m32r2f_init_idesc_table (SIM_CPU *);
extern void m32r2f_sem_init_idesc_table (SIM_CPU *);

138
sim/m32r/decodex.c
View File

@ -252,14 +252,14 @@ m32rxf_init_idesc_table (SIM_CPU *cpu)
const IDESC *
m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
M32RXF_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
@ -716,7 +716,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -747,7 +747,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add3:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -780,7 +780,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and3:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_and3.f
UINT f_r1;
UINT f_r2;
@ -813,7 +813,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_or3:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_and3.f
UINT f_r1;
UINT f_r2;
@ -846,7 +846,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r1;
INT f_simm8;
@ -875,7 +875,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addv:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -906,7 +906,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addv3:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -939,7 +939,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addx:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -970,7 +970,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bc8:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -993,7 +993,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bc24:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1016,7 +1016,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beq:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_r1;
UINT f_r2;
@ -1049,7 +1049,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beqz:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_r2;
SI f_disp16;
@ -1077,7 +1077,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bl8:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1101,7 +1101,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bl24:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1125,7 +1125,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcl8:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1149,7 +1149,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcl24:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1173,7 +1173,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bra8:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
@ -1196,7 +1196,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bra24:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
@ -1219,7 +1219,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -1249,7 +1249,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpi:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r2;
INT f_simm16;
@ -1277,7 +1277,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpz:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r2;
@ -1302,7 +1302,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_div:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_r1;
UINT f_r2;
@ -1333,7 +1333,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jc:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1358,7 +1358,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jl:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1384,7 +1384,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jmp:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_jl.f
UINT f_r2;
@ -1409,7 +1409,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1439,7 +1439,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld_d:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1472,7 +1472,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldb:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1502,7 +1502,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldb_d:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1535,7 +1535,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldh:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1565,7 +1565,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldh_d:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -1598,7 +1598,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld_plus:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1629,7 +1629,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ld24:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld24.f
UINT f_r1;
UINT f_uimm24;
@ -1657,7 +1657,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldi8:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_r1;
INT f_simm8;
@ -1685,7 +1685,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldi16:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
INT f_simm16;
@ -1713,7 +1713,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lock:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1743,7 +1743,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_machi_a:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_machi_a.f
UINT f_r1;
UINT f_acc;
@ -1776,7 +1776,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mulhi_a:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_machi_a.f
UINT f_r1;
UINT f_acc;
@ -1809,7 +1809,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mv:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1839,7 +1839,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvfachi_a:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
UINT f_r1;
UINT f_accs;
@ -1867,7 +1867,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvfc:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1895,7 +1895,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvtachi_a:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
UINT f_r1;
UINT f_accs;
@ -1923,7 +1923,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mvtc:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -1964,7 +1964,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_rac_dsi:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
UINT f_accd;
UINT f_accs;
@ -2006,7 +2006,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_seth:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_seth.f
UINT f_r1;
UINT f_hi16;
@ -2034,7 +2034,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sll3:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add3.f
UINT f_r1;
UINT f_r2;
@ -2067,7 +2067,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slli:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_slli.f
UINT f_r1;
UINT f_uimm5;
@ -2096,7 +2096,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2126,7 +2126,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st_d:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -2159,7 +2159,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2189,7 +2189,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb_d:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -2222,7 +2222,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2252,7 +2252,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth_d:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_d.f
UINT f_r1;
UINT f_r2;
@ -2285,7 +2285,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_st_plus:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2316,7 +2316,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sth_plus:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2347,7 +2347,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb_plus:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2378,7 +2378,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_trap:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_trap.f
UINT f_uimm4;
@ -2401,7 +2401,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_unlock:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2431,7 +2431,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_satb:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -2461,7 +2461,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sat:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
UINT f_r1;
UINT f_r2;
@ -2504,7 +2504,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_macwu1:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2534,7 +2534,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_msblo:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2564,7 +2564,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mulwu1:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
@ -2607,7 +2607,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_clrpsw:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
@ -2624,7 +2624,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_setpsw:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
@ -2641,7 +2641,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bset:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;
@ -2672,7 +2672,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btst:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;

2
sim/m32r/decodex.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define M32RXF_DECODE_H
extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void m32rxf_init_idesc_table (SIM_CPU *);
extern void m32rxf_sem_init_idesc_table (SIM_CPU *);

9
sim/sh64/ChangeLog
View File

@ -1,3 +1,12 @@
2009-11-22 Doug Evans <dje@sebabeach.org>
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode-compact.c: Regenerate.
* decode-compact.h: Regenerate.
* decode-media.c: Regenerate.
* decode-media.h: Regenerate.
2009-11-03 Doug Evans <dje@sebabeach.org>
* arch.c: Regenerate.

6
sim/sh64/cpu.h
View File

@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */

1
sim/sh64/cpuall.h
View File

@ -29,7 +29,6 @@ This file is part of the GNU simulators.
#ifdef WANT_CPU_SH64
#include "eng.h"
#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif

258
sim/sh64/decode-compact.c
View File

File diff suppressed because it is too large Load Diff

2
sim/sh64/decode-compact.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define SH64_COMPACT_DECODE_H
extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void sh64_compact_init_idesc_table (SIM_CPU *);
extern void sh64_compact_sem_init_idesc_table (SIM_CPU *);

158
sim/sh64/decode-media.c
View File

@ -320,14 +320,14 @@ sh64_media_init_idesc_table (SIM_CPU *cpu)
const IDESC *
sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
SH64_MEDIA_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 22) & (63 << 4)) | ((insn >> 16) & (15 << 0)));
@ -1548,7 +1548,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -1580,7 +1580,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_left;
INT f_disp10;
@ -1611,7 +1611,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_alloco:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
@ -1636,7 +1636,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_left;
UINT f_right;
@ -1668,7 +1668,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_beqi:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beqi.f
UINT f_left;
INT f_imm6;
@ -1699,7 +1699,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_blink:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_blink.f
UINT f_trb;
UINT f_dest;
@ -1746,7 +1746,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_byterev:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
UINT f_dest;
@ -1774,7 +1774,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmveq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -1806,7 +1806,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fabsd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fabsd.f
UINT f_left;
UINT f_right;
@ -1838,7 +1838,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fabss:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fabsd.f
UINT f_left;
UINT f_right;
@ -1870,7 +1870,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_faddd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -1902,7 +1902,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fadds:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -1934,7 +1934,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fcmpeqd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -1966,7 +1966,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fcmpeqs:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -1998,7 +1998,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fcnvds:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fabsd.f
UINT f_left;
UINT f_right;
@ -2030,7 +2030,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fcnvsd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fabsd.f
UINT f_left;
UINT f_right;
@ -2062,7 +2062,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fgetscr:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_shori.f
UINT f_dest;
@ -2086,7 +2086,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fiprs:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2120,7 +2120,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fldd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fldd.f
UINT f_left;
SI f_disp10x8;
@ -2151,7 +2151,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fldp:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fldd.f
UINT f_left;
SI f_disp10x8;
@ -2183,7 +2183,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_flds:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_flds.f
UINT f_left;
SI f_disp10x4;
@ -2214,7 +2214,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fldxd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2246,7 +2246,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fldxp:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2279,7 +2279,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fldxs:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2311,7 +2311,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fmacs:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2344,7 +2344,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fmovdq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fabsd.f
UINT f_left;
UINT f_right;
@ -2376,7 +2376,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fmovls:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
UINT f_dest;
@ -2404,7 +2404,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fmovqd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
UINT f_dest;
@ -2432,7 +2432,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fmovsl:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fabsd.f
UINT f_left;
UINT f_right;
@ -2464,7 +2464,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fputscr:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fabsd.f
UINT f_left;
UINT f_right;
@ -2492,7 +2492,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fstd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fldd.f
UINT f_left;
SI f_disp10x8;
@ -2523,7 +2523,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fsts:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_flds.f
UINT f_left;
SI f_disp10x4;
@ -2554,7 +2554,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fstxd:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2586,7 +2586,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fstxs:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2618,7 +2618,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ftrvs:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -2653,7 +2653,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_getcfg:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -2684,7 +2684,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_getcon:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
UINT f_dest;
@ -2711,7 +2711,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_gettr:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_blink.f
UINT f_trb;
UINT f_dest;
@ -2739,7 +2739,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldb:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_left;
INT f_disp10;
@ -2770,7 +2770,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldl:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_flds.f
UINT f_left;
SI f_disp10x4;
@ -2801,7 +2801,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fldd.f
UINT f_left;
SI f_disp10x8;
@ -2832,7 +2832,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lduw:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_lduw.f
UINT f_left;
SI f_disp10x2;
@ -2863,7 +2863,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldhil:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -2894,7 +2894,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldhiq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -2925,7 +2925,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldlol:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -2956,7 +2956,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldloq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -2987,7 +2987,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldxb:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3019,7 +3019,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldxl:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3051,7 +3051,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldxq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3083,7 +3083,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldxub:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3115,7 +3115,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldxuw:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3147,7 +3147,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldxw:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3179,7 +3179,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mcmv:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3212,7 +3212,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movi:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_movi.f
INT f_imm16;
UINT f_dest;
@ -3252,7 +3252,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ori:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ori.f
UINT f_left;
INT f_imm10;
@ -3283,7 +3283,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_pta:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_pta.f
DI f_disp16;
UINT f_tra;
@ -3310,7 +3310,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ptabs:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_right;
UINT f_tra;
@ -3338,7 +3338,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ptrel:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_beq.f
UINT f_right;
UINT f_tra;
@ -3366,7 +3366,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_putcfg:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -3397,7 +3397,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_putcon:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
UINT f_dest;
@ -3424,7 +3424,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_shari:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_shari.f
UINT f_left;
UINT f_uimm6;
@ -3455,7 +3455,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_shori:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_shori.f
UINT f_uimm16;
UINT f_dest;
@ -3483,7 +3483,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stb:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_left;
INT f_disp10;
@ -3514,7 +3514,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stl:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_flds.f
UINT f_left;
SI f_disp10x4;
@ -3545,7 +3545,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_fldd.f
UINT f_left;
SI f_disp10x8;
@ -3576,7 +3576,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stw:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_lduw.f
UINT f_left;
SI f_disp10x2;
@ -3607,7 +3607,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sthil:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -3638,7 +3638,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sthiq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -3669,7 +3669,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stlol:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -3700,7 +3700,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stloq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_getcfg.f
UINT f_left;
INT f_disp6;
@ -3731,7 +3731,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stxb:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3763,7 +3763,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stxl:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3795,7 +3795,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stxq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3827,7 +3827,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_stxw:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3859,7 +3859,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_swapq:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_add.f
UINT f_left;
UINT f_right;
@ -3892,7 +3892,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_trapa:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
@ -3916,7 +3916,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_xori:
{
const IDESC *idesc = &sh64_media_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_xori.f
UINT f_left;
INT f_imm6;

2
sim/sh64/decode-media.h
View File

@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define SH64_MEDIA_DECODE_H
extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void sh64_media_init_idesc_table (SIM_CPU *);
extern void sh64_media_sem_init_idesc_table (SIM_CPU *);