gas/testsuite/
2005-09-28 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d, gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New. * gas/i386/i386.exp: Run new tests. ld/testsuite/ 2005-09-28 Jan Beulich <jbeulich@novell.com> * ld-x86-64/tlspic.dd: Adjust. opcodes/ 2005-09-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (stack_v_mode): Renamed from branch_v_mode. (indirEv): Use it. (stackEv): New. (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions. (dis386): Document and use new 'V' meta character. Use it for single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov. (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark data prefix as used whenever DFLAG was examined. Handle 'V'. (intel_operand_size): Use stack_v_mode. (OP_E): Use stack_v_mode, but handle only the special case of 64-bit mode without operand size override here; fall through to v_mode case otherwise. (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode and no operand size override is present. (OP_J): Use get32s for obtaining the displacement also when rex64 is present.
This commit is contained in:
Jan Beulich
parent
e05278afa3
commit
1a114b1284
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@ -1,3 +1,9 @@
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2005-09-28 Jan Beulich <jbeulich@novell.com>
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* gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d,
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gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New.
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* gas/i386/i386.exp: Run new tests.
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2005-09-28 Jan Beulich <jbeulich@novell.com>
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* gas/i386/mixed-mode-reloc.s: Enable all insns.
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@ -131,6 +131,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-opcode"
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run_dump_test "x86-64-pcrel"
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run_dump_test "x86-64-rip"
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run_dump_test "x86-64-stack"
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run_dump_test "x86-64-stack-intel"
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run_dump_test "x86-64-stack-suffix"
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run_list_test "x86-64-inval" "-al"
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run_list_test "x86-64-segment" "-al"
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run_list_test "x86-64-inval-seg" "-al"
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@ -0,0 +1,40 @@
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#objdump: -dwMintel
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#name: x86-64 stack-related opcodes (Intel mode)
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#source: x86-64-stack.s
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.*: +file format elf64-x86-64
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[0-9a-f]+:[ ]+50[ ]+push[ ]+rax
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[ ]*[0-9a-f]+:[ ]+66 50[ ]+push[ ]+ax
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[ ]*[0-9a-f]+:[ ]+66 48 50[ ]+push[ ]+rax
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[ ]*[0-9a-f]+:[ ]+58[ ]+pop[ ]+rax
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[ ]*[0-9a-f]+:[ ]+66 58[ ]+pop[ ]+ax
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[ ]*[0-9a-f]+:[ ]+66 48 58[ ]+pop[ ]+rax
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[ ]*[0-9a-f]+:[ ]+8f c0[ ]+pop[ ]+rax
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[ ]*[0-9a-f]+:[ ]+66 8f c0[ ]+pop[ ]+ax
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[ ]*[0-9a-f]+:[ ]+66 48 8f c0[ ]+pop[ ]+rax
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[ ]*[0-9a-f]+:[ ]+8f 00[ ]+pop[ ]+QWORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 8f 00[ ]+pop[ ]+WORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 48 8f 00[ ]+pop[ ]+QWORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+ff d0[ ]+call[ ]+rax
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[ ]*[0-9a-f]+:[ ]+66 ff d0[ ]+call[ ]+ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff d0[ ]+call[ ]+rax
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[ ]*[0-9a-f]+:[ ]+ff 10[ ]+call[ ]+QWORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 ff 10[ ]+call[ ]+WORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 48 ff 10[ ]+call[ ]+QWORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+ff e0[ ]+jmp[ ]+rax
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[ ]*[0-9a-f]+:[ ]+66 ff e0[ ]+jmp[ ]+ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff e0[ ]+jmp[ ]+rax
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[ ]*[0-9a-f]+:[ ]+ff 20[ ]+jmp[ ]+QWORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 ff 20[ ]+jmp[ ]+WORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 48 ff 20[ ]+jmp[ ]+QWORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+ff f0[ ]+push[ ]+rax
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[ ]*[0-9a-f]+:[ ]+66 ff f0[ ]+push[ ]+ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff f0[ ]+push[ ]+rax
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[ ]*[0-9a-f]+:[ ]+ff 30[ ]+push[ ]+QWORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 ff 30[ ]+push[ ]+WORD PTR \[rax\]
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[ ]*[0-9a-f]+:[ ]+66 48 ff 30[ ]+push[ ]+QWORD PTR \[rax\]
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#pass
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@ -0,0 +1,40 @@
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#objdump: -dwMsuffix
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#name: x86-64 stack-related opcodes (with suffixes)
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#source: x86-64-stack.s
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.*: +file format elf64-x86-64
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[0-9a-f]+:[ ]+50[ ]+pushq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 50[ ]+pushw[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 50[ ]+pushq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+58[ ]+popq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 58[ ]+popw[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 58[ ]+popq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+8f c0[ ]+popq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 8f c0[ ]+popw[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 8f c0[ ]+popq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+8f 00[ ]+popq[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 8f 00[ ]+popw[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 8f 00[ ]+popq[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+ff d0[ ]+callq[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+66 ff d0[ ]+callw[ ]+\*%ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff d0[ ]+callq[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+ff 10[ ]+callq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 ff 10[ ]+callw[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 ff 10[ ]+callq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+ff e0[ ]+jmpq[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+66 ff e0[ ]+jmpw[ ]+\*%ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff e0[ ]+jmpq[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+ff 20[ ]+jmpq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 ff 20[ ]+jmpw[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 ff 20[ ]+jmpq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+ff f0[ ]+pushq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 ff f0[ ]+pushw[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff f0[ ]+pushq[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+ff 30[ ]+pushq[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 ff 30[ ]+pushw[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 ff 30[ ]+pushq[ ]+\(%rax\)
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#pass
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@ -0,0 +1,39 @@
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#objdump: -dw
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#name: x86-64 stack-related opcodes
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.*: +file format elf64-x86-64
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[0-9a-f]+:[ ]+50[ ]+pushq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 50[ ]+pushw?[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 50[ ]+pushq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+58[ ]+popq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 58[ ]+popw?[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 58[ ]+popq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+8f c0[ ]+popq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 8f c0[ ]+popw?[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 8f c0[ ]+popq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+8f 00[ ]+popq[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 8f 00[ ]+popw[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 8f 00[ ]+popq[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+ff d0[ ]+callq?[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+66 ff d0[ ]+callw?[ ]+\*%ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff d0[ ]+callq?[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+ff 10[ ]+callq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 ff 10[ ]+callw[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 ff 10[ ]+callq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+ff e0[ ]+jmpq?[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+66 ff e0[ ]+jmpw?[ ]+\*%ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff e0[ ]+jmpq?[ ]+\*%rax
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[ ]*[0-9a-f]+:[ ]+ff 20[ ]+jmpq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 ff 20[ ]+jmpw[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 ff 20[ ]+jmpq[ ]+\*\(%rax\)
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[ ]*[0-9a-f]+:[ ]+ff f0[ ]+pushq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+66 ff f0[ ]+pushw?[ ]+%ax
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[ ]*[0-9a-f]+:[ ]+66 48 ff f0[ ]+pushq?[ ]+%rax
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[ ]*[0-9a-f]+:[ ]+ff 30[ ]+pushq[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 ff 30[ ]+pushw[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+66 48 ff 30[ ]+pushq[ ]+\(%rax\)
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#pass
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@ -0,0 +1,23 @@
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.macro try bytes:vararg
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.byte \bytes
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.byte 0x66, \bytes
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.byte 0x66, 0x48, \bytes
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.endm
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.text
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_start:
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try 0x50
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try 0x58
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try 0x8f, 0xc0
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try 0x8f, 0x00
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try 0xff, 0xd0
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try 0xff, 0x10
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try 0xff, 0xe0
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try 0xff, 0x20
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try 0xff, 0xf0
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try 0xff, 0x30
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@ -1,3 +1,7 @@
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2005-09-28 Jan Beulich <jbeulich@novell.com>
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* ld-x86-64/tlspic.dd: Adjust.
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2005-09-01 Hans-Peter Nilsson <hp@axis.com>
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* ld-cris: Skip tests unsuitable for testing target
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@ -20,10 +20,9 @@ Disassembly of section .text:
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+1008: 66 48 8d 3d 80 03 10[ ]+lea 1049472\(%rip\),%rdi +# 101390 <.*>
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+100f: 00 *
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# -> R_X86_64_DTPMOD64 sg1
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+1010: 66[ ]+data16
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+1011: 66[ ]+data16
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+1012: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*>
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+1010: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*>
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# -> R_X86_64_JUMP_SLOT __tls_get_addr
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+1017: [0-9a-f ]+
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+1018: 90[ ]+nop *
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+1019: 90[ ]+nop *
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+101a: 90[ ]+nop *
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@ -41,10 +40,9 @@ Disassembly of section .text:
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+1030: 66 48 8d 3d 08 03 10[ ]+lea 1049352\(%rip\),%rdi +# 101340 <.*>
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+1037: 00 *
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# -> R_X86_64_DTPMOD64 [0 0x2000000000000000]
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+1038: 66[ ]+data16
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+1039: 66[ ]+data16
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+103a: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*>
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+1038: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*>
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# -> R_X86_64_JUMP_SLOT __tls_get_addr
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+103f: [0-9a-f ]+
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+1040: 90[ ]+nop *
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+1041: 90[ ]+nop *
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+1042: 90[ ]+nop *
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@ -62,10 +60,9 @@ Disassembly of section .text:
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+1058: 66 48 8d 3d 58 03 10[ ]+lea 1049432\(%rip\),%rdi +# 1013b8 <.*>
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+105f: 00 *
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# -> R_X86_64_DTPMOD64 [0 0x4000000000000000]
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+1060: 66[ ]+data16
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+1061: 66[ ]+data16
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+1062: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*>
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+1060: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*>
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# -> R_X86_64_JUMP_SLOT __tls_get_addr
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+1067: [0-9a-f ]+
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+1068: 90[ ]+nop *
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+1069: 90[ ]+nop *
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+106a: 90[ ]+nop *
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@ -83,10 +80,9 @@ Disassembly of section .text:
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+1080: 66 48 8d 3d e8 02 10[ ]+lea 1049320\(%rip\),%rdi +# 101370 <.*>
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+1087: 00 *
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# -> R_X86_64_DTPMOD64 [0 0x6000000000000000]
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+1088: 66[ ]+data16
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+1089: 66[ ]+data16
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+108a: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*>
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+1088: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*>
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# -> R_X86_64_JUMP_SLOT __tls_get_addr
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+108f: [0-9a-f ]+
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+1090: 90[ ]+nop *
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+1091: 90[ ]+nop *
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+1092: 90[ ]+nop *
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@ -1,3 +1,23 @@
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2005-09-28 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
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(indirEv): Use it.
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(stackEv): New.
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(Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
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(dis386): Document and use new 'V' meta character. Use it for
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single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
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opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
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(putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
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data prefix as used whenever DFLAG was examined. Handle 'V'.
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(intel_operand_size): Use stack_v_mode.
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(OP_E): Use stack_v_mode, but handle only the special case of
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64-bit mode without operand size override here; fall through to
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v_mode case otherwise.
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(OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
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and no operand size override is present.
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(OP_J): Use get32s for obtaining the displacement also when rex64
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is present.
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2005-09-08 Paul Brook <paul@codesourcery.com>
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* arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
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@ -200,8 +200,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Eq OP_E, q_mode
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#define Edq OP_E, dq_mode
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#define Edqw OP_E, dqw_mode
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#define indirEv OP_indirE, branch_v_mode
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#define indirEv OP_indirE, stack_v_mode
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#define indirEp OP_indirE, f_mode
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#define stackEv OP_E, stack_v_mode
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#define Em OP_E, m_mode
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#define Ew OP_E, w_mode
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#define Ma OP_E, v_mode
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@ -280,10 +281,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Sw OP_SEG, w_mode
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#define Ap OP_DIR, 0
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#define Ob OP_OFF, b_mode
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#define Ob64 OP_OFF64, b_mode
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#define Ov OP_OFF, v_mode
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#define Ov64 OP_OFF64, v_mode
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#define Ob OP_OFF64, b_mode
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#define Ov OP_OFF64, v_mode
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#define Xb OP_DSreg, eSI_reg
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#define Xv OP_DSreg, eSI_reg
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#define Yb OP_ESreg, eDI_reg
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@ -329,7 +328,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
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#define f_mode 13 /* 4- or 6-byte pointer operand */
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#define const_1_mode 14
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#define branch_v_mode 15 /* v_mode for branch. */
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#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
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#define es_reg 100
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#define cs_reg 101
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@ -479,6 +478,7 @@ struct dis386 {
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'S' => print 'w', 'l' or 'q' if suffix_always is true
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'T' => print 'q' in 64bit mode and behave as 'P' otherwise
|
||||
'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
|
||||
'V' => print 'q' in 64bit mode and behave as 'S' otherwise
|
||||
'W' => print 'b' or 'w' ("w" or "de" in intel mode)
|
||||
'X' => print 's', 'd' depending on data16 prefix (for XMM)
|
||||
'Y' => 'q' if instruction has an REX 64bit overwrite prefix
|
||||
|
|
@ -519,7 +519,7 @@ static const struct dis386 dis386[] = {
|
|||
{ "adcB", AL, Ib, XX },
|
||||
{ "adcS", eAX, Iv, XX },
|
||||
{ "push{T|}", ss, XX, XX },
|
||||
{ "popT|}", ss, XX, XX },
|
||||
{ "pop{T|}", ss, XX, XX },
|
||||
/* 18 */
|
||||
{ "sbbB", Eb, Gb, XX },
|
||||
{ "sbbS", Ev, Gv, XX },
|
||||
|
|
@ -584,23 +584,23 @@ static const struct dis386 dis386[] = {
|
|||
{ "dec{S|}", RMeSI, XX, XX },
|
||||
{ "dec{S|}", RMeDI, XX, XX },
|
||||
/* 50 */
|
||||
{ "pushS", RMrAX, XX, XX },
|
||||
{ "pushS", RMrCX, XX, XX },
|
||||
{ "pushS", RMrDX, XX, XX },
|
||||
{ "pushS", RMrBX, XX, XX },
|
||||
{ "pushS", RMrSP, XX, XX },
|
||||
{ "pushS", RMrBP, XX, XX },
|
||||
{ "pushS", RMrSI, XX, XX },
|
||||
{ "pushS", RMrDI, XX, XX },
|
||||
{ "pushV", RMrAX, XX, XX },
|
||||
{ "pushV", RMrCX, XX, XX },
|
||||
{ "pushV", RMrDX, XX, XX },
|
||||
{ "pushV", RMrBX, XX, XX },
|
||||
{ "pushV", RMrSP, XX, XX },
|
||||
{ "pushV", RMrBP, XX, XX },
|
||||
{ "pushV", RMrSI, XX, XX },
|
||||
{ "pushV", RMrDI, XX, XX },
|
||||
/* 58 */
|
||||
{ "popS", RMrAX, XX, XX },
|
||||
{ "popS", RMrCX, XX, XX },
|
||||
{ "popS", RMrDX, XX, XX },
|
||||
{ "popS", RMrBX, XX, XX },
|
||||
{ "popS", RMrSP, XX, XX },
|
||||
{ "popS", RMrBP, XX, XX },
|
||||
{ "popS", RMrSI, XX, XX },
|
||||
{ "popS", RMrDI, XX, XX },
|
||||
{ "popV", RMrAX, XX, XX },
|
||||
{ "popV", RMrCX, XX, XX },
|
||||
{ "popV", RMrDX, XX, XX },
|
||||
{ "popV", RMrBX, XX, XX },
|
||||
{ "popV", RMrSP, XX, XX },
|
||||
{ "popV", RMrBP, XX, XX },
|
||||
{ "popV", RMrSI, XX, XX },
|
||||
{ "popV", RMrDI, XX, XX },
|
||||
/* 60 */
|
||||
{ "pusha{P|}", XX, XX, XX },
|
||||
{ "popa{P|}", XX, XX, XX },
|
||||
|
|
@ -654,7 +654,7 @@ static const struct dis386 dis386[] = {
|
|||
{ "movQ", Sv, Sw, XX },
|
||||
{ "leaS", Gv, M, XX },
|
||||
{ "movQ", Sw, Sv, XX },
|
||||
{ "popU", Ev, XX, XX },
|
||||
{ "popU", stackEv, XX, XX },
|
||||
/* 90 */
|
||||
{ "nop", NOP_Fixup, 0, XX, XX },
|
||||
{ "xchgS", RMeCX, eAX, XX },
|
||||
|
|
@ -674,10 +674,10 @@ static const struct dis386 dis386[] = {
|
|||
{ "sahf{|}", XX, XX, XX },
|
||||
{ "lahf{|}", XX, XX, XX },
|
||||
/* a0 */
|
||||
{ "movB", AL, Ob64, XX },
|
||||
{ "movS", eAX, Ov64, XX },
|
||||
{ "movB", Ob64, AL, XX },
|
||||
{ "movS", Ov64, eAX, XX },
|
||||
{ "movB", AL, Ob, XX },
|
||||
{ "movS", eAX, Ov, XX },
|
||||
{ "movB", Ob, AL, XX },
|
||||
{ "movS", Ov, eAX, XX },
|
||||
{ "movs{b||b|}", Yb, Xb, XX },
|
||||
{ "movs{R||R|}", Yv, Xv, XX },
|
||||
{ "cmps{b||b|}", Xb, Yb, XX },
|
||||
|
|
@ -1361,7 +1361,7 @@ static const struct dis386 grps[][8] = {
|
|||
{ "JcallT", indirEp, XX, XX },
|
||||
{ "jmpT", indirEv, XX, XX },
|
||||
{ "JjmpT", indirEp, XX, XX },
|
||||
{ "pushU", Ev, XX, XX },
|
||||
{ "pushU", stackEv, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
},
|
||||
/* GRP6 */
|
||||
|
|
@ -2860,7 +2860,7 @@ putop (const char *template, int sizeflag)
|
|||
case 'T':
|
||||
if (intel_syntax)
|
||||
break;
|
||||
if (mode_64bit)
|
||||
if (mode_64bit && (sizeflag & DFLAG))
|
||||
{
|
||||
*obufp++ = 'q';
|
||||
break;
|
||||
|
|
@ -2882,16 +2882,17 @@ putop (const char *template, int sizeflag)
|
|||
*obufp++ = 'l';
|
||||
else
|
||||
*obufp++ = 'w';
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
}
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
}
|
||||
break;
|
||||
case 'U':
|
||||
if (intel_syntax)
|
||||
break;
|
||||
if (mode_64bit)
|
||||
if (mode_64bit && (sizeflag & DFLAG))
|
||||
{
|
||||
*obufp++ = 'q';
|
||||
if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
|
||||
*obufp++ = 'q';
|
||||
break;
|
||||
}
|
||||
/* Fall through. */
|
||||
|
|
@ -2909,8 +2910,8 @@ putop (const char *template, int sizeflag)
|
|||
*obufp++ = intel_syntax ? 'd' : 'l';
|
||||
else
|
||||
*obufp++ = 'w';
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
}
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
}
|
||||
break;
|
||||
case 'R':
|
||||
|
|
@ -2945,6 +2946,16 @@ putop (const char *template, int sizeflag)
|
|||
if (!(rex & REX_MODE64))
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
break;
|
||||
case 'V':
|
||||
if (intel_syntax)
|
||||
break;
|
||||
if (mode_64bit && (sizeflag & DFLAG))
|
||||
{
|
||||
if (sizeflag & SUFFIX_ALWAYS)
|
||||
*obufp++ = 'q';
|
||||
break;
|
||||
}
|
||||
/* Fall through. */
|
||||
case 'S':
|
||||
if (intel_syntax)
|
||||
break;
|
||||
|
|
@ -3134,7 +3145,7 @@ intel_operand_size (int bytemode, int sizeflag)
|
|||
case dqw_mode:
|
||||
oappend ("WORD PTR ");
|
||||
break;
|
||||
case branch_v_mode:
|
||||
case stack_v_mode:
|
||||
if (mode_64bit && (sizeflag & DFLAG))
|
||||
{
|
||||
oappend ("QWORD PTR ");
|
||||
|
|
@ -3223,18 +3234,15 @@ OP_E (int bytemode, int sizeflag)
|
|||
else
|
||||
oappend (names32[rm + add]);
|
||||
break;
|
||||
case branch_v_mode:
|
||||
if (mode_64bit)
|
||||
oappend (names64[rm + add]);
|
||||
else
|
||||
case stack_v_mode:
|
||||
if (mode_64bit && (sizeflag & DFLAG))
|
||||
{
|
||||
if ((sizeflag & DFLAG) || bytemode != branch_v_mode)
|
||||
oappend (names32[rm + add]);
|
||||
else
|
||||
oappend (names16[rm + add]);
|
||||
oappend (names64[rm + add]);
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
bytemode = v_mode;
|
||||
/* FALLTHRU */
|
||||
case v_mode:
|
||||
case dq_mode:
|
||||
case dqw_mode:
|
||||
|
|
@ -3630,7 +3638,7 @@ OP_REG (int code, int sizeflag)
|
|||
break;
|
||||
case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
|
||||
case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
|
||||
if (mode_64bit)
|
||||
if (mode_64bit && (sizeflag & DFLAG))
|
||||
{
|
||||
s = names64[code - rAX_reg + add];
|
||||
break;
|
||||
|
|
@ -3873,7 +3881,7 @@ OP_J (int bytemode, int sizeflag)
|
|||
disp -= 0x100;
|
||||
break;
|
||||
case v_mode:
|
||||
if (sizeflag & DFLAG)
|
||||
if ((sizeflag & DFLAG) || (rex & REX_MODE64))
|
||||
disp = get32s ();
|
||||
else
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue