From 1a3af0bfc3b53c392923b62275c9ca72bee46f7b Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 29 Mar 2011 01:41:49 +0000 Subject: [PATCH] sim: bfin: fix sign extension with 16bit acc add insns The current implementation attempts to handle the 16bit sign extension itself. Unfortunately, it gets it right in some cases. So rather than fix that logic, just drop it in favor of using 16bit signed casts. Now gcc will take care of getting the logic right. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- sim/bfin/ChangeLog | 7 +++++++ sim/bfin/bfin-sim.c | 11 ++--------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index a28da1a3f6..7a4aea71f4 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,10 @@ +2011-03-28 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Cast high 16bits of A0.W to bs16 + and add to casted low 16bits of A0.L and store in val0. Cast high + 16bits of A1.W to bs16 and add to casted low 16bits of A1.L and + store in val1. Delete bit checks of val0 and val1. + 2011-03-26 Robin Getz * bfin-sim.c (decode_dsp32alu_0): Set result to 0x7FFFFFFF when diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 1555dc2c3f..27112c6e99 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -4523,23 +4523,16 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) } else if (aop == 1 && aopcde == 12) { - bu32 val0 = ((AWREG (0) >> 16) + (AWREG (0) & 0xFFFF)) & 0xFFFF; - bu32 val1 = ((AWREG (1) >> 16) + (AWREG (1) & 0xFFFF)) & 0xFFFF; + bs32 val0 = (bs16)(AWREG (0) >> 16) + (bs16)AWREG (0); + bs32 val1 = (bs16)(AWREG (1) >> 16) + (bs16)AWREG (1); TRACE_INSN (cpu, "R%i = A1.L + A1.H, R%i = A0.L + A0.H;", dst1, dst0); if (dst0 == dst1) illegal_instruction_combination (cpu); - if (val0 & 0x8000) - val0 |= 0xFFFF0000; - - if (val1 & 0x8000) - val1 |= 0xFFFF0000; - SET_DREG (dst0, val0); SET_DREG (dst1, val1); - /* XXX: ASTAT ? */ } else if (aopcde == 1) {