x86: don't recognize bnd<N> as registers without CpuMPX

This is just like for all other extended/optional register sets.

gas/ChangeLog

@@ -1,3 +1,10 @@
+2018-04-26  Jan Beulich  <jbeulich@suse.com>
+
+	* config/tc-i386.c (parse_real_register): Check bnd<N>
+	registers.
+	* testsuite/gas/i386/bnd.s, testsuite/gas/i386/bnd.l: New.
+	* testsuite/gas/i386/i386.exp: Run new test.
+
 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 
 	* config/tc-i386.c (parse_real_register): Check FPU register

gas/config/tc-i386.c

@@ -10170,6 +10170,9 @@ parse_real_register (char *reg_string, char **end_op)
       && !cpu_arch_flags.bitfield.cpuregmask)
     return (const reg_entry *) NULL;
 
+  if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
+    return (const reg_entry *) NULL;
+
   /* Don't allow fake index register unless allow_index_reg isn't 0. */
   if (!allow_index_reg
       && (r->reg_num == RegEiz || r->reg_num == RegRiz))

gas/testsuite/gas/i386/bnd.l

@@ -0,0 +1,12 @@
+.*: Assembler messages:
+.*:6: Error: .*`bndmov'.*
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\.text
+[ 	]*2[ 	]+\.intel_syntax noprefix
+[ 	]*3[ 	]+\.arch generic32
+[ 	]*4[ 	]+bnd:
+[ 	]*5[ 	]+\?\?\?\? A1000000[ 	]+mov	eax, bnd0
+[ 	]*5[ 	]+00
+[ 	]*6[ 	]+bndmov	bnd0, bnd0

gas/testsuite/gas/i386/bnd.s

@@ -0,0 +1,6 @@
+	.text
+	.intel_syntax noprefix
+	.arch generic32
+bnd:
+	mov	eax, bnd0
+	bndmov	bnd0, bnd0

gas/testsuite/gas/i386/i386.exp

@@ -294,6 +294,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_list_test "mpx-inval-1" "-al"
     run_list_test "mpx-inval-2" "-al"
     run_dump_test "mpx-add-bnd-prefix"
+    run_list_test "bnd" "-al"
     run_dump_test "sha"
     run_dump_test "clflushopt"
     run_dump_test "clflushopt-intel"