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x86: fold RegXMM/RegYMM/RegZMM into RegSIMD 

... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
This commit is contained in:
Jan Beulich 2017-12-18 09:36:14 +01:00 committed by Jan Beulich
parent ca0d63fe07
commit 1b54b8d7e4
11 changed files with 49851 additions and 49821 deletions
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18
gas/ChangeLog
View File

@ -1,3 +1,21 @@
2017-12-18 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_simd_size): New.
(match_mem_size): Use it.
(operand_size_match): Likewise. Split .reg and .acc checks.
(pi, check_VecOperands, match_template, check_byte_reg,
check_long_reg, check_qword_reg, build_modrm_byte,
parse_real_register): Replace .regxmm, .regymm, and .regzmm
checks.
(md_assemble): Qualify .acc check with .xmmword one.
(bad_implicit_operand): Delete.
(process_operands): Replace .firstxmm0 checks with .acc plus
.xmmword ones. Drop now pointless assertions. Convert .acc to
.regsimd.
* config/tc-i386-intel.c (i386_intel_simplify_register): Replace
.regxmm, .regymm, and .regzmm checks.
* testsuite/gas/i386/x86-64-specific-reg.l: Adjust expectations.
2017-12-18 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_check): Extend comment.

6
gas/config/tc-i386-intel.c
View File

@ -286,9 +286,9 @@ i386_intel_simplify_register (expressionS *e)
i.op[this_operand].regs = i386_regtab + reg_num;
}
else if (!intel_state.index
&& (i386_regtab[reg_num].reg_type.bitfield.regxmm
|| i386_regtab[reg_num].reg_type.bitfield.regymm
|| i386_regtab[reg_num].reg_type.bitfield.regzmm
&& (i386_regtab[reg_num].reg_type.bitfield.xmmword
|| i386_regtab[reg_num].reg_type.bitfield.ymmword
|| i386_regtab[reg_num].reg_type.bitfield.zmmword
|| i386_regtab[reg_num].reg_num == RegRiz
|| i386_regtab[reg_num].reg_num == RegEiz))
intel_state.index = i386_regtab + reg_num;

157
gas/config/tc-i386.c
View File

@ -1825,6 +1825,20 @@ match_reg_size (const insn_template *t, unsigned int j)
&& !t->operand_types[j].bitfield.tbyte));
}
/* Return 1 if there is no conflict in SIMD register on
operand J for instruction template T. */
static INLINE int
match_simd_size (const insn_template *t, unsigned int j)
{
return !((i.types[j].bitfield.xmmword
&& !t->operand_types[j].bitfield.xmmword)
|| (i.types[j].bitfield.ymmword
&& !t->operand_types[j].bitfield.ymmword)
|| (i.types[j].bitfield.zmmword
&& !t->operand_types[j].bitfield.zmmword));
}
/* Return 1 if there is no conflict in any size on operand J for
instruction template T. */
@ -1837,12 +1851,17 @@ match_mem_size (const insn_template *t, unsigned int j)
&& !t->operand_types[j].bitfield.unspecified)
|| (i.types[j].bitfield.fword
&& !t->operand_types[j].bitfield.fword)
|| (i.types[j].bitfield.xmmword
&& !t->operand_types[j].bitfield.xmmword)
|| (i.types[j].bitfield.ymmword
&& !t->operand_types[j].bitfield.ymmword)
|| (i.types[j].bitfield.zmmword
&& !t->operand_types[j].bitfield.zmmword)));
/* For scalar opcode templates to allow register and memory
operands at the same time, some special casing is needed
here. */
|| ((t->operand_types[j].bitfield.regsimd
&& !t->opcode_modifier.broadcast
&& (t->operand_types[j].bitfield.dword
|| t->operand_types[j].bitfield.qword))
? (i.types[j].bitfield.xmmword
|| i.types[j].bitfield.ymmword
|| i.types[j].bitfield.zmmword)
: !match_simd_size(t, j))));
}
/* Return 1 if there is no size conflict on any operands for
@ -1864,17 +1883,31 @@ operand_size_match (const insn_template *t)
/* Check memory and accumulator operand size. */
for (j = 0; j < i.operands; j++)
{
if (!i.types[j].bitfield.reg && t->operand_types[j].bitfield.anysize)
if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
&& t->operand_types[j].bitfield.anysize)
continue;
if ((t->operand_types[j].bitfield.reg
|| t->operand_types[j].bitfield.acc)
if (t->operand_types[j].bitfield.reg
&& !match_reg_size (t, j))
{
match = 0;
break;
}
if (t->operand_types[j].bitfield.regsimd
&& !match_simd_size (t, j))
{
match = 0;
break;
}
if (t->operand_types[j].bitfield.acc
&& (!match_reg_size (t, j) || !match_simd_size (t, j)))
{
match = 0;
break;
}
if (i.types[j].bitfield.mem && !match_mem_size (t, j))
{
match = 0;
@ -2804,9 +2837,7 @@ pi (char *line, i386_insn *x)
fprintf (stdout, "\n");
if (x->types[j].bitfield.reg
|| x->types[j].bitfield.regmmx
|| x->types[j].bitfield.regxmm
|| x->types[j].bitfield.regymm
|| x->types[j].bitfield.regzmm
|| x->types[j].bitfield.regsimd
|| x->types[j].bitfield.sreg2
|| x->types[j].bitfield.sreg3
|| x->types[j].bitfield.control
@ -3768,7 +3799,7 @@ md_assemble (char *line)
for (j = 0; j < i.operands; j++)
if (i.types[j].bitfield.inoutportreg
|| i.types[j].bitfield.shiftcount
|| i.types[j].bitfield.acc)
|| (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
i.reg_operands--;
/* ImmExt should be processed after SSE2AVX. */
@ -4576,9 +4607,9 @@ check_VecOperands (const insn_template *t)
/* Without VSIB byte, we can't have a vector register for index. */
if (!t->opcode_modifier.vecsib
&& i.index_reg
&& (i.index_reg->reg_type.bitfield.regxmm
|| i.index_reg->reg_type.bitfield.regymm
|| i.index_reg->reg_type.bitfield.regzmm))
&& (i.index_reg->reg_type.bitfield.xmmword
|| i.index_reg->reg_type.bitfield.ymmword
|| i.index_reg->reg_type.bitfield.zmmword))
{
i.error = unsupported_vector_index_register;
return 1;
@ -4598,11 +4629,11 @@ check_VecOperands (const insn_template *t)
{
if (!i.index_reg
|| !((t->opcode_modifier.vecsib == VecSIB128
&& i.index_reg->reg_type.bitfield.regxmm)
&& i.index_reg->reg_type.bitfield.xmmword)
|| (t->opcode_modifier.vecsib == VecSIB256
&& i.index_reg->reg_type.bitfield.regymm)
&& i.index_reg->reg_type.bitfield.ymmword)
|| (t->opcode_modifier.vecsib == VecSIB512
&& i.index_reg->reg_type.bitfield.regzmm)))
&& i.index_reg->reg_type.bitfield.zmmword)))
{
i.error = invalid_vsib_address;
return 1;
@ -4611,10 +4642,12 @@ check_VecOperands (const insn_template *t)
gas_assert (i.reg_operands == 2 || i.mask);
if (i.reg_operands == 2 && !i.mask)
{
gas_assert (i.types[0].bitfield.regxmm
|| i.types[0].bitfield.regymm);
gas_assert (i.types[2].bitfield.regxmm
|| i.types[2].bitfield.regymm);
gas_assert (i.types[0].bitfield.regsimd);
gas_assert (i.types[0].bitfield.xmmword
|| i.types[0].bitfield.ymmword);
gas_assert (i.types[2].bitfield.regsimd);
gas_assert (i.types[2].bitfield.xmmword
|| i.types[2].bitfield.ymmword);
if (operand_check == check_none)
return 0;
if (register_number (i.op[0].regs)
@ -4633,9 +4666,10 @@ check_VecOperands (const insn_template *t)
}
else if (i.reg_operands == 1 && i.mask)
{
if ((i.types[1].bitfield.regxmm
|| i.types[1].bitfield.regymm
|| i.types[1].bitfield.regzmm)
if (i.types[1].bitfield.regsimd
&& (i.types[1].bitfield.xmmword
|| i.types[1].bitfield.ymmword
|| i.types[1].bitfield.zmmword)
&& (register_number (i.op[1].regs)
== register_number (i.index_reg)))
{
@ -4941,13 +4975,9 @@ match_template (char mnem_suffix)
&& !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2)
&& ((!operand_types[0].bitfield.regmmx
&& !operand_types[0].bitfield.regxmm
&& !operand_types[0].bitfield.regymm
&& !operand_types[0].bitfield.regzmm)
&& !operand_types[0].bitfield.regsimd)
|| (!operand_types[t->operands > 1].bitfield.regmmx
&& !operand_types[t->operands > 1].bitfield.regxmm
&& !operand_types[t->operands > 1].bitfield.regymm
&& !operand_types[t->operands > 1].bitfield.regzmm))
&& !operand_types[t->operands > 1].bitfield.regsimd))
&& (t->base_opcode != 0x0fc7
|| t->extension_opcode != 1 /* cmpxchg8b */))
continue;
@ -4960,9 +4990,9 @@ match_template (char mnem_suffix)
&& !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2)
&& ((!operand_types[0].bitfield.regmmx
&& !operand_types[0].bitfield.regxmm)
&& !operand_types[0].bitfield.regsimd)
|| (!operand_types[t->operands > 1].bitfield.regmmx
&& !operand_types[t->operands > 1].bitfield.regxmm)))
&& !operand_types[t->operands > 1].bitfield.regsimd)))
continue;
/* Do not verify operands when there are none. */
@ -5653,9 +5683,7 @@ check_byte_reg (void)
/* Any other register is bad. */
if (i.types[op].bitfield.reg
|| i.types[op].bitfield.regmmx
|| i.types[op].bitfield.regxmm
|| i.types[op].bitfield.regymm
|| i.types[op].bitfield.regzmm
|| i.types[op].bitfield.regsimd
|| i.types[op].bitfield.sreg2
|| i.types[op].bitfield.sreg3
|| i.types[op].bitfield.control
@ -5728,7 +5756,7 @@ check_long_reg (void)
{
if (intel_syntax
&& i.tm.opcode_modifier.toqword
&& !i.types[0].bitfield.regxmm)
&& !i.types[0].bitfield.regsimd)
{
/* Convert to QWORD. We want REX byte. */
i.suffix = QWORD_MNEM_SUFFIX;
@ -5779,7 +5807,7 @@ check_qword_reg (void)
lowering is more complicated. */
if (intel_syntax
&& i.tm.opcode_modifier.todword
&& !i.types[0].bitfield.regxmm)
&& !i.types[0].bitfield.regsimd)
{
/* Convert to DWORD. We don't want REX byte. */
i.suffix = LONG_MNEM_SUFFIX;
@ -5929,20 +5957,6 @@ finalize_imm (void)
return 1;
}
static int
bad_implicit_operand (int xmm)
{
const char *ireg = xmm ? "xmm0" : "ymm0";
if (intel_syntax)
as_bad (_("the last operand of `%s' must be `%s%s'"),
i.tm.name, register_prefix, ireg);
else
as_bad (_("the first operand of `%s' must be `%s%s'"),
i.tm.name, register_prefix, ireg);
return 0;
}
static int
process_operands (void)
{
@ -5962,17 +5976,15 @@ process_operands (void)
&& MAX_OPERANDS > dupl
&& operand_type_equal (&i.types[dest], &regxmm));
if (i.tm.opcode_modifier.firstxmm0)
if (i.tm.operand_types[0].bitfield.acc
&& i.tm.operand_types[0].bitfield.xmmword)
{
/* The first operand is implicit and must be xmm0. */
gas_assert (operand_type_equal (&i.types[0], &regxmm));
if (register_number (i.op[0].regs) != 0)
return bad_implicit_operand (1);
if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
{
/* Keep xmm0 for instructions with VEX prefix and 3
sources. */
i.tm.operand_types[0].bitfield.acc = 0;
i.tm.operand_types[0].bitfield.regsimd = 1;
goto duplicate;
}
else
@ -6032,18 +6044,11 @@ duplicate:
if (i.tm.opcode_modifier.immext)
process_immext ();
}
else if (i.tm.opcode_modifier.firstxmm0)
else if (i.tm.operand_types[0].bitfield.acc
&& i.tm.operand_types[0].bitfield.xmmword)
{
unsigned int j;
/* The first operand is implicit and must be xmm0/ymm0/zmm0. */
gas_assert (i.reg_operands
&& (operand_type_equal (&i.types[0], &regxmm)
|| operand_type_equal (&i.types[0], &regymm)
|| operand_type_equal (&i.types[0], &regzmm)));
if (register_number (i.op[0].regs) != 0)
return bad_implicit_operand (i.types[0].bitfield.regxmm);
for (j = 1; j < i.operands; j++)
{
i.op[j - 1] = i.op[j];
@ -6806,10 +6811,8 @@ build_modrm_byte (void)
for (op = 0; op < i.operands; op++)
if (i.types[op].bitfield.reg
|| i.types[op].bitfield.regmmx
|| i.types[op].bitfield.regxmm
|| i.types[op].bitfield.regymm
|| i.types[op].bitfield.regsimd
|| i.types[op].bitfield.regbnd
|| i.types[op].bitfield.regzmm
|| i.types[op].bitfield.regmask
|| i.types[op].bitfield.sreg2
|| i.types[op].bitfield.sreg3
@ -8725,9 +8728,9 @@ bad_address:
|| (i.base_reg->reg_num
!= (addr_mode == CODE_64BIT ? RegRip : RegEip))))
|| (i.index_reg
&& !i.index_reg->reg_type.bitfield.regxmm
&& !i.index_reg->reg_type.bitfield.regymm
&& !i.index_reg->reg_type.bitfield.regzmm
&& !i.index_reg->reg_type.bitfield.xmmword
&& !i.index_reg->reg_type.bitfield.ymmword
&& !i.index_reg->reg_type.bitfield.zmmword
&& ((addr_mode == CODE_64BIT
? !(i.index_reg->reg_type.bitfield.qword
|| i.index_reg->reg_num == RegRiz)
@ -9780,13 +9783,13 @@ parse_real_register (char *reg_string, char **end_op)
if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
return (const reg_entry *) NULL;
if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
return (const reg_entry *) NULL;
if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
return (const reg_entry *) NULL;
if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
return (const reg_entry *) NULL;
if (r->reg_type.bitfield.regmask

90
gas/testsuite/gas/i386/x86-64-specific-reg.l
View File

@ -315,62 +315,62 @@
.*:[0-9]*: Error: .*r15.* 2 .*invlpga.*
.*:[0-9]*: Error: .*r15.* 1 .*skinit.*
# xmm1
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm2
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm3
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm4
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm5
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm6
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm7
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm8
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm9
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm10
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm11
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm12
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm13
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm14
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*
# xmm15
.*:[0-9]*: Error: .*blendvpd.*xmm0.*
.*:[0-9]*: Error: .*blendvps.*xmm0.*
.*:[0-9]*: Error: .*pblendv.*xmm0.*
.*:[0-9]*: Error: .*blendvpd.*
.*:[0-9]*: Error: .*blendvps.*
.*:[0-9]*: Error: .*pblendv.*

18
opcodes/ChangeLog
View File

@ -1,3 +1,21 @@
2017-12-18 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_shorthands): Add RegXMM, RegYMM, and
RegZMM.
(opcode_modifiers): Drop FirstXmm0.
(operand_types): Replace RegXMM, RegYMM, and RegZMM with just
RegSIMD.
* i386-opc.h (enum of opcode modifiers): Drop FirstXmm0.
(struct i386_opcode_modifier): Drop firstxmm0.
(enum of operand types): Replace RegXMM, RegYMM, and RegZMM with
just RegSIMD. Extend comment.
(union i386_operand_type): Replace regxmm, regymm, and regzmm
with just regsimd.
* i386-opc.tbl (blendvpd, blendvps, pblendvb, sha256rnds2): Use
Acc|Xmmword.
* i386-reg.tbl (xmm0): Add Acc.
* i386-init.h, i386-tbl.h: Re-generate.
2017-12-18 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_shorthands): Add FloatAcc and

8
opcodes/i386-gen.c
View File

@ -343,6 +343,9 @@ static const initializer operand_type_shorthands[] =
{ "Reg64", "Reg|Qword" },
{ "FloatAcc", "Acc|Tbyte" },
{ "FloatReg", "Reg|Tbyte" },
{ "RegXMM", "RegSIMD|Xmmword" },
{ "RegYMM", "RegSIMD|Ymmword" },
{ "RegZMM", "RegSIMD|Zmmword" },
};
static initializer operand_type_init[] =
@ -601,7 +604,6 @@ static bitfield opcode_modifiers[] =
BITFIELD (NoTrackPrefixOk),
BITFIELD (IsLockable),
BITFIELD (RegKludge),
BITFIELD (FirstXmm0),
BITFIELD (Implicit1stXmm0),
BITFIELD (RepPrefixOk),
BITFIELD (HLEPrefixOk),
@ -643,9 +645,7 @@ static bitfield operand_types[] =
{
BITFIELD (Reg),
BITFIELD (RegMMX),
BITFIELD (RegXMM),
BITFIELD (RegYMM),
BITFIELD (RegZMM),
BITFIELD (RegSIMD),
BITFIELD (RegMask),
BITFIELD (Imm1),
BITFIELD (Imm8),

216
opcodes/i386-init.h
View File

@ -1174,254 +1174,254 @@
#define OPERAND_TYPE_NONE \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_REG8 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REG16 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REG32 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REG64 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_IMM1 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM8 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM8S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM16 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_BASEINDEX \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_DISP8 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_DISP16 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_DISP32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_INOUTPORTREG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_SHIFTCOUNT \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_CONTROL \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_TEST \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_DEBUG \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_FLOATREG \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_FLOATACC \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_SREG2 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_SREG3 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_ACC \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_JUMPABSOLUTE \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REGMMX \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_REGXMM \
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REGYMM \
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REGZMM \
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REGMASK \
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_ESSEG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_ACC32 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_ACC64 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_INOUTPORTREG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_REG16_INOUTPORTREG \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_DISP16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_ANYDISP \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32_32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM32_64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_IMM64_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
#define OPERAND_TYPE_VEC_IMM4 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0 } }
1, 0, 0 } }
#define OPERAND_TYPE_REGBND \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0 } }
0, 1, 0 } }

17
opcodes/i386-opc.h
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@ -430,8 +430,6 @@ enum
/* fake an extra reg operand for clr, imul and special register
processing for some instructions. */
RegKludge,
/* The first operand must be xmm0 */
FirstXmm0,
/* An implicit xmm0 as the first operand */
Implicit1stXmm0,
/* The HLE prefix is OK:
@ -643,7 +641,6 @@ typedef struct i386_opcode_modifier
unsigned int notrackprefixok:1;
unsigned int islockable:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;
unsigned int implicit1stxmm0:1;
unsigned int hleprefixok:2;
unsigned int repprefixok:1;
@ -689,12 +686,8 @@ enum
Reg = 0,
/* MMX register */
RegMMX,
/* SSE register */
RegXMM,
/* AVX registers */
RegYMM,
/* AVX512 registers */
RegZMM,
/* Vector registers */
RegSIMD,
/* Vector Mask registers */
RegMask,
/* Control register */
@ -738,7 +731,7 @@ enum
Disp32S,
/* 64 bit displacement */
Disp64,
/* Accumulator %al/%ax/%eax/%rax/%st(0) */
/* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
Acc,
/* Register which can be used for base or index in memory operand. */
BaseIndex,
@ -806,9 +799,7 @@ typedef union i386_operand_type
{
unsigned int reg:1;
unsigned int regmmx:1;
unsigned int regxmm:1;
unsigned int regymm:1;
unsigned int regzmm:1;
unsigned int regsimd:1;
unsigned int regmask:1;
unsigned int control:1;
unsigned int debug:1;

14
opcodes/i386-opc.tbl
View File

@ -1649,13 +1649,13 @@ blendpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|Igno
blendpd, 3, 0x660f3a0d, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendps, 3, 0x660f3a0c, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvpd, 3, 0x664b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvpd, 3, 0x664b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt|SSE2AVX, { Acc|Xmmword, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvpd, 2, 0x664b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvpd, 3, 0x660f3815, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvpd, 3, 0x660f3815, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvpd, 2, 0x660f3815, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvps, 3, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvps, 3, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt|SSE2AVX, { Acc|Xmmword, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvps, 2, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvps, 3, 0x660f3814, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvps, 3, 0x660f3814, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
blendvps, 2, 0x660f3814, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
dppd, 3, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
dppd, 3, 0x660f3a41, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
@ -1673,9 +1673,9 @@ mpsadbw, 3, 0x6642, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|Igno
mpsadbw, 3, 0x660f3a42, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
packusdw, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
packusdw, 2, 0x660f382b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendvb, 3, 0x664c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendvb, 3, 0x664c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt|SSE2AVX, { Acc|Xmmword, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendvb, 2, 0x664c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendvb, 3, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendvb, 3, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendvb, 2, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendw, 3, 0x660e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pblendw, 3, 0x660f3a0e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
@ -3134,7 +3134,7 @@ sha1rnds4, 3, 0xf3acc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf
sha1nexte, 2, 0xf38c8, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha1msg1, 2, 0xf38c9, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha1msg2, 2, 0xf38ca, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha256rnds2, 3, 0xf38cb, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha256rnds2, 3, 0xf38cb, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha256rnds2, 2, 0xf38cb, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha256msg1, 2, 0xf38cc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha256msg2, 2, 0xf38cd, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }

2
opcodes/i386-reg.tbl
View File

@ -180,7 +180,7 @@ mm4, RegMMX, 0, 4, 33, 45
mm5, RegMMX, 0, 5, 34, 46
mm6, RegMMX, 0, 6, 35, 47
mm7, RegMMX, 0, 7, 36, 48
xmm0, RegXMM, 0, 0, 21, 17
xmm0, RegXMM|Acc, 0, 0, 21, 17
xmm1, RegXMM, 0, 1, 22, 18
xmm2, RegXMM, 0, 2, 23, 19
xmm3, RegXMM, 0, 3, 24, 20

99126
opcodes/i386-tbl.h
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