gas/
2009-01-09 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add .rdtscp. (md_show_usage): Display rdtscp. * doc/c-i386.texi: Document rdtscp. gas/testsuite/ 2009-01-09 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.s: Add rdtscp. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2009-01-09 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS. (cpu_flags): Add CpuRdtscp. (set_bitfield): Remove CpuSledgehammer check. * i386-opc.h (CpuRdtscp): New. (CpuLM): Updated. (i386_cpu_flags): Add cpurdtscp. * i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
1cb0a76746
commit
1b7f3fb0dd
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@ -1,3 +1,10 @@
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2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Add .rdtscp.
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(md_show_usage): Display rdtscp.
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* doc/c-i386.texi: Document rdtscp.
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2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
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* config/tc-ppc.c (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test.
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@ -650,6 +650,8 @@ static const arch_entry cpu_arch[] =
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CPU_MOVBE_FLAGS },
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{ ".ept", PROCESSOR_UNKNOWN,
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CPU_EPT_FLAGS },
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{ ".rdtscp", PROCESSOR_UNKNOWN,
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CPU_RDTSCP_FLAGS },
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{ ".3dnow", PROCESSOR_UNKNOWN,
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CPU_3DNOW_FLAGS },
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{ ".3dnowa", PROCESSOR_UNKNOWN,
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@ -8235,7 +8237,8 @@ md_show_usage (stream)
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EXTENSION is combination of:\n\
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mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
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avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
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3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
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rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme, abm,\n\
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padlock\n"));
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fprintf (stream, _("\
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-mtune=CPU optimize for CPU, CPU is one of:\n\
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i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
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@ -130,6 +130,7 @@ accept various extension mnemonics. For example,
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@code{fma},
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@code{movbe},
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@code{ept},
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@code{rdtscp},
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@code{3dnow},
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@code{3dnowa},
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@code{sse4a},
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@ -879,7 +880,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
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@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
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@item @samp{.ept}
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@item @samp{.ept} @tab @samp{.rdtscp}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.svme} @tab @samp{.abm}
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@item @samp{.padlock}
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@ -1,3 +1,15 @@
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2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/arch-10.s: Add rdtscp.
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* gas/i386/x86-64-arch-2.s: Likewise.
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* gas/i386/arch-10.d: Updated.
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* gas/i386/arch-10-1.l: Likewise.
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* gas/i386/arch-10-2.l: Likewise.
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* gas/i386/arch-10-3.l: Likewise.
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* gas/i386/arch-10-4.l: Likewise.
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* gas/i386/x86-64-arch-2.d: Likewise.
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2009-01-06 Chao-ying Fu <fu@mips.com>
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* gas/mips/jalr.s, gas/mips/jalr.l: Add more tests for jalr
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@ -24,6 +24,7 @@
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.*:48: Error: .*
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.*:50: Error: .*
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.*:52: Error: .*
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.*:54: Error: .*
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GAS LISTING .*
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@ -66,17 +67,19 @@ GAS LISTING .*
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[ ]*36[ ]+movbe \(%ecx\),%ebx
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[ ]*37[ ]+\# EPT
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[ ]*38[ ]+invept \(%ecx\),%ebx
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[ ]*39[ ]+\# 3DNow
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[ ]*40[ ]+pmulhrw %mm4,%mm3
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[ ]*41[ ]+\# 3DNow Extensions
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[ ]*42[ ]+pswapd %mm4,%mm3
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[ ]*43[ ]+\# SSE4a
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[ ]*44[ ]+insertq %xmm2,%xmm1
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[ ]*45[ ]+\# SVME
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[ ]*46[ ]+vmload
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[ ]*47[ ]+\# ABM
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[ ]*48[ ]+lzcnt %ecx,%ebx
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[ ]*49[ ]+\# SSE5
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[ ]*50[ ]+frczss %xmm2, %xmm1
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[ ]*51[ ]+\# PadLock
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[ ]*52[ ]+xstorerng
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[ ]*39[ ]+\# RDTSCP
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[ ]*40[ ]+rdtscp
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[ ]*41[ ]+\# 3DNow
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[ ]*42[ ]+pmulhrw %mm4,%mm3
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[ ]*43[ ]+\# 3DNow Extensions
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[ ]*44[ ]+pswapd %mm4,%mm3
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[ ]*45[ ]+\# SSE4a
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[ ]*46[ ]+insertq %xmm2,%xmm1
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[ ]*47[ ]+\# SVME
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[ ]*48[ ]+vmload
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[ ]*49[ ]+\# ABM
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[ ]*50[ ]+lzcnt %ecx,%ebx
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[ ]*51[ ]+\# SSE5
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[ ]*52[ ]+frczss %xmm2, %xmm1
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[ ]*53[ ]+\# PadLock
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[ ]*54[ ]+xstorerng
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@ -23,6 +23,7 @@
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.*:48: Error: .*
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.*:50: Error: .*
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.*:52: Error: .*
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.*:54: Error: .*
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GAS LISTING .*
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@ -65,17 +66,19 @@ GAS LISTING .*
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[ ]*36[ ]+movbe \(%ecx\),%ebx
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[ ]*37[ ]+\# EPT
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[ ]*38[ ]+invept \(%ecx\),%ebx
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[ ]*39[ ]+\# 3DNow
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[ ]*40[ ]+pmulhrw %mm4,%mm3
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[ ]*41[ ]+\# 3DNow Extensions
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[ ]*42[ ]+pswapd %mm4,%mm3
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[ ]*43[ ]+\# SSE4a
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[ ]*44[ ]+insertq %xmm2,%xmm1
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[ ]*45[ ]+\# SVME
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[ ]*46[ ]+vmload
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[ ]*47[ ]+\# ABM
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[ ]*48[ ]+lzcnt %ecx,%ebx
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[ ]*49[ ]+\# SSE5
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[ ]*50[ ]+frczss %xmm2, %xmm1
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[ ]*51[ ]+\# PadLock
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[ ]*52[ ]+xstorerng
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[ ]*39[ ]+\# RDTSCP
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[ ]*40[ ]+rdtscp
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[ ]*41[ ]+\# 3DNow
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[ ]*42[ ]+pmulhrw %mm4,%mm3
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[ ]*43[ ]+\# 3DNow Extensions
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[ ]*44[ ]+pswapd %mm4,%mm3
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[ ]*45[ ]+\# SSE4a
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[ ]*46[ ]+insertq %xmm2,%xmm1
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[ ]*47[ ]+\# SVME
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[ ]*48[ ]+vmload
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[ ]*49[ ]+\# ABM
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[ ]*50[ ]+lzcnt %ecx,%ebx
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[ ]*51[ ]+\# SSE5
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[ ]*52[ ]+frczss %xmm2, %xmm1
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[ ]*53[ ]+\# PadLock
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[ ]*54[ ]+xstorerng
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@ -16,6 +16,7 @@
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.*:48: Error: .*
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.*:50: Error: .*
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.*:52: Error: .*
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.*:54: Error: .*
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GAS LISTING .*
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@ -61,17 +62,22 @@ GAS LISTING .*
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[ ]*36[ ]+movbe \(%ecx\),%ebx
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[ ]*37[ ]+\# EPT
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[ ]*38[ ]+invept \(%ecx\),%ebx
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[ ]*39[ ]+\# 3DNow
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[ ]*40[ ]+pmulhrw %mm4,%mm3
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[ ]*41[ ]+\# 3DNow Extensions
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[ ]*42[ ]+pswapd %mm4,%mm3
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[ ]*43[ ]+\# SSE4a
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[ ]*44[ ]+insertq %xmm2,%xmm1
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[ ]*45[ ]+\# SVME
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[ ]*46[ ]+vmload
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[ ]*47[ ]+\# ABM
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[ ]*48[ ]+lzcnt %ecx,%ebx
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[ ]*49[ ]+\# SSE5
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[ ]*50[ ]+frczss %xmm2, %xmm1
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[ ]*51[ ]+\# PadLock
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[ ]*52[ ]+xstorerng
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[ ]*39[ ]+\# RDTSCP
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[ ]*40[ ]+rdtscp
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[ ]*41[ ]+\# 3DNow
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[ ]*42[ ]+pmulhrw %mm4,%mm3
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[ ]*43[ ]+\# 3DNow Extensions
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[ ]*44[ ]+pswapd %mm4,%mm3
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[ ]*45[ ]+\# SSE4a
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[ ]*46[ ]+insertq %xmm2,%xmm1
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[ ]*47[ ]+\# SVME
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[ ]*48[ ]+vmload
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[ ]*49[ ]+\# ABM
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[ ]*50[ ]+lzcnt %ecx,%ebx
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[ ]*51[ ]+\# SSE5
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[ ]*52[ ]+frczss %xmm2, %xmm1
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[ ]*53[ ]+\# PadLock
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GAS LISTING .*
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[ ]*54[ ]+xstorerng
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@ -14,6 +14,7 @@
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.*:48: Error: .*
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.*:50: Error: .*
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.*:52: Error: .*
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.*:54: Error: .*
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GAS LISTING .*
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@ -59,17 +60,22 @@ GAS LISTING .*
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[ ]*36[ ]+movbe \(%ecx\),%ebx
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[ ]*37[ ]+\# EPT
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[ ]*38[ ]+invept \(%ecx\),%ebx
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[ ]*39[ ]+\# 3DNow
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[ ]*40[ ]+pmulhrw %mm4,%mm3
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[ ]*41[ ]+\# 3DNow Extensions
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[ ]*42[ ]+pswapd %mm4,%mm3
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[ ]*43[ ]+\# SSE4a
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[ ]*44[ ]+insertq %xmm2,%xmm1
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[ ]*45[ ]+\# SVME
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[ ]*46[ ]+vmload
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[ ]*47[ ]+\# ABM
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[ ]*48[ ]+lzcnt %ecx,%ebx
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[ ]*49[ ]+\# SSE5
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[ ]*50[ ]+frczss %xmm2, %xmm1
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[ ]*51[ ]+\# PadLock
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[ ]*52[ ]+xstorerng
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[ ]*39[ ]+\# RDTSCP
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[ ]*40[ ]+rdtscp
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[ ]*41[ ]+\# 3DNow
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[ ]*42[ ]+pmulhrw %mm4,%mm3
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[ ]*43[ ]+\# 3DNow Extensions
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[ ]*44[ ]+pswapd %mm4,%mm3
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[ ]*45[ ]+\# SSE4a
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[ ]*46[ ]+insertq %xmm2,%xmm1
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[ ]*47[ ]+\# SVME
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[ ]*48[ ]+vmload
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[ ]*49[ ]+\# ABM
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[ ]*50[ ]+lzcnt %ecx,%ebx
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[ ]*51[ ]+\# SSE5
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[ ]*52[ ]+frczss %xmm2, %xmm1
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[ ]*53[ ]+\# PadLock
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GAS LISTING .*
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[ ]*54[ ]+xstorerng
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@ -1,4 +1,4 @@
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#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+sse5+3dnowa+svme+padlock
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#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+rdtscp+sse5+3dnowa+svme+padlock
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#objdump: -dw
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#name: i386 arch 10
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@ -25,6 +25,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
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[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
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[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
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[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
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[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
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@ -36,6 +36,8 @@ vfmadd132pd %xmm4,%xmm6,%xmm2
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movbe (%ecx),%ebx
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# EPT
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invept (%ecx),%ebx
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# RDTSCP
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rdtscp
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# 3DNow
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pmulhrw %mm4,%mm3
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# 3DNow Extensions
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@ -1,4 +1,4 @@
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#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+sse5+3dnowa+svme+padlock
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#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+rdtscp+sse5+3dnowa+svme+padlock
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#objdump: -dw
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#name: x86-64 arch 2
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@ -25,6 +25,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
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[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
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[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
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[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
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[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
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[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
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[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
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@ -36,6 +36,8 @@ vfmadd132pd %xmm4,%xmm6,%xmm2
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movbe (%rcx),%ebx
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# EPT
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invept (%rcx),%rbx
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# RDTSCP
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rdtscp
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# 3DNow
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pmulhrw %mm4,%mm3
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# 3DNow Extensions
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@ -1,3 +1,18 @@
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2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
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and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS.
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(cpu_flags): Add CpuRdtscp.
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(set_bitfield): Remove CpuSledgehammer check.
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* i386-opc.h (CpuRdtscp): New.
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(CpuLM): Updated.
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(i386_cpu_flags): Add cpurdtscp.
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* i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (PPCNONE): Define.
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@ -81,9 +81,9 @@ static initializer cpu_flag_init [] =
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{ "CPU_ATHLON_FLAGS",
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuMMX|Cpu3dnow|Cpu3dnowA" },
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{ "CPU_K8_FLAGS",
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuRdtscp|CpuLM" },
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{ "CPU_AMDFAM10_FLAGS",
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuRdtscp|CpuLM" },
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{ "CPU_MMX_FLAGS",
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"CpuMMX" },
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{ "CPU_SSE_FLAGS",
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@ -112,6 +112,8 @@ static initializer cpu_flag_init [] =
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
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{ "CPU_MOVBE_FLAGS",
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"CpuMovbe" },
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{ "CPU_RDTSCP_FLAGS",
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"CpuRdtscp" },
|
||||
{ "CPU_EPT_FLAGS",
|
||||
"CpuEPT" },
|
||||
{ "CPU_3DNOW_FLAGS",
|
||||
|
|
@ -274,6 +276,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuLM),
|
||||
BITFIELD (CpuMovbe),
|
||||
BITFIELD (CpuEPT),
|
||||
BITFIELD (CpuRdtscp),
|
||||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
#ifdef CpuUnused
|
||||
|
|
@ -500,9 +503,7 @@ set_bitfield (const char *f, bitfield *array, unsigned int size)
|
|||
{
|
||||
unsigned int i;
|
||||
|
||||
if (strcmp (f, "CpuSledgehammer") == 0)
|
||||
f= "CpuK8";
|
||||
else if (strcmp (f, "Mmword") == 0)
|
||||
if (strcmp (f, "Mmword") == 0)
|
||||
f= "Qword";
|
||||
else if (strcmp (f, "Oword") == 0)
|
||||
f= "Xmmword";
|
||||
|
|
|
|||
|
|
@ -21,179 +21,183 @@
|
|||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE5_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -94,8 +94,10 @@
|
|||
#define CpuMovbe (CpuFMA + 1)
|
||||
/* EPT Instructions required */
|
||||
#define CpuEPT (CpuMovbe + 1)
|
||||
/* RDTSCP Instuction support required */
|
||||
#define CpuRdtscp (CpuEPT + 1)
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
#define CpuLM (CpuEPT + 1)
|
||||
#define CpuLM (CpuRdtscp + 1)
|
||||
/* 64bit support required */
|
||||
#define Cpu64 (CpuLM + 1)
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -150,6 +152,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpufma:1;
|
||||
unsigned int cpumovbe:1;
|
||||
unsigned int cpuept:1;
|
||||
unsigned int cpurdtscp:1;
|
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unsigned int cpulm:1;
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unsigned int cpu64:1;
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unsigned int cpuno64:1;
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|
@ -2493,7 +2493,7 @@ syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
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sysret, 0, 0xf07, None, 2, CpuK6, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
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sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
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swapgs, 0, 0xf01, 0xf8, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
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rdtscp, 0, 0xf01, 0xf9, 2, CpuSledgehammer, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
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rdtscp, 0, 0xf01, 0xf9, 2, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
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||||
// AMD Pacifica additions.
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||||
clgi, 0, 0xf01, 0xdd, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
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||||
|
|
|
|||
4950
opcodes/i386-tbl.h
4950
opcodes/i386-tbl.h
File diff suppressed because it is too large
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Reference in New Issue