x86-64: Display eiz for address with the addr32 prefix
In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers. For mov -0xccddef(,%eiz,), %rax disassembler now displays: 67 48 8b 04 25 11 22 33 ff mov -0xccddef(,%eiz,1),%rax instead of 67 48 8b 04 25 11 22 33 ff addr32 mov 0xffffffffff332211,%rax gas/ * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests. opcodes/ * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers.
This commit is contained in:
H.J. Lu
parent
26fb3983d7
commit
1bc60e5624
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@ -1,3 +1,12 @@
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2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/evex-no-scale-64.d: Updated.
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* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
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* testsuite/gas/i386/x86-64-addr32.d: Likewise.
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* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
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* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.
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* testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests.
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2018-08-14 Robert Yang <liezhi.yang@windriver.com>
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* as.c (main): Improve check for input file matching output file.
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@ -10,5 +10,5 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 f1 7c 48 28 04 05 40 00 00 00 vmovaps 0x40\(,%rax,1\),%zmm0
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+[a-f0-9]+: 62 f1 7c 48 28 04 25 40 00 00 00 vmovaps 0x40,%zmm0
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+[a-f0-9]+: 67 62 f1 7c 48 28 04 05 40 00 00 00 vmovaps 0x40\(,%eax,1\),%zmm0
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+[a-f0-9]+: 67 62 f1 7c 48 28 04 25 40 00 00 00 addr32 vmovaps 0x40,%zmm0
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+[a-f0-9]+: 67 62 f1 7c 48 28 04 25 40 00 00 00 vmovaps 0x40\(,%eiz,1\),%zmm0
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+[a-f0-9]+: 62 f1 7c 48 28 04 25 40 00 00 00 vmovaps 0x40,%zmm0
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@ -11,17 +11,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[eax\+0x0\].*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[r8d\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+rax,\[eip\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00 addr32 lea rax,ds:0x0.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00 lea[ ]+rax,\[eiz\*1\+0x0\].*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov al,ds:0x600898
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov ax,ds:0x600898
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov eax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov rax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov rax,ds:0x800898
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 addr32 mov rbx,QWORD PTR ds:0x800898
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+rbx,QWORD PTR \[eiz\*1\+0x800898\]
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov ds:0x600898,al
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov ds:0x600898,ax
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov ds:0x600898,eax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov ds:0x600898,rax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov ds:0x800898,rax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 addr32 mov QWORD PTR ds:0x800898,rbx
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+QWORD PTR \[eiz\*1\+0x800898\],rbx
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*1-0xccddef\],eax
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*2-0xccddef\],eax
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#pass
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@ -11,17 +11,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%eax\),%rax.*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%r8d\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%eip\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00[ ]+addr32 lea[ ]+0x0,%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,%eiz,1\),%rax.*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov 0x600898,%al
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov 0x600898,%ax
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov 0x600898,%eax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov 0x600898,%rax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov 0x800898,%rax
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 addr32 mov 0x800898,%rbx
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+0x800898\(,%eiz,1\),%rbx
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov %al,0x600898
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov %ax,0x600898
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov %eax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov %rax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov %rax,0x800898
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 addr32 mov %rbx,0x800898
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+%rbx,0x800898\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,2\)
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#pass
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@ -11,17 +11,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[eax\+0x0\].*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[r8d\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+rax,\[eip\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00 addr32 lea rax,ds:0x0.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00 lea[ ]+rax,\[eiz\*1\+0x0\].*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov al,ds:0x600898
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov ax,ds:0x600898
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov eax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov rax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov rax,ds:0x800898
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 addr32 mov rbx,QWORD PTR ds:0x800898
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+rbx,QWORD PTR \[eiz\*1\+0x800898\]
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov ds:0x600898,al
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov ds:0x600898,ax
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov ds:0x600898,eax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov ds:0x600898,rax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov ds:0x800898,rax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 addr32 mov QWORD PTR ds:0x800898,rbx
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+QWORD PTR \[eiz\*1\+0x800898\],rbx
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*1-0xccddef\],eax
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*2-0xccddef\],eax
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#pass
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@ -10,17 +10,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%eax\),%rax.*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%r8d\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%eip\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00[ ]+addr32 lea[ ]+0x0,%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,%eiz,1\),%rax.*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov 0x600898,%al
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov 0x600898,%ax
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov 0x600898,%eax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov 0x600898,%rax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov 0x800898,%rax
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 addr32 mov 0x800898,%rbx
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+0x800898\(,%eiz,1\),%rbx
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov %al,0x600898
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov %ax,0x600898
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov %eax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov %rax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov %rax,0x800898
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 addr32 mov %rbx,0x800898
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+%rbx,0x800898\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,2\)
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#pass
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@ -1,4 +1,5 @@
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.text
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.text
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.allow_index_reg
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lea symbol(%eax), %rax
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lea symbol(%r8d), %rax
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lea symbol(%eip), %rax
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@ -15,3 +16,5 @@
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addr32 mov %rax,0x600898
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addr32 mov %rax,0x800898
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addr32 mov %rbx,0x800898
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mov %eax, -0xccddef(,%eiz,)
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mov %eax, -0xccddef(,%eiz,2)
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@ -1,3 +1,9 @@
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2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
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address with the addr32 prefix and without base nor index
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registers.
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2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
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@ -15337,6 +15337,7 @@ OP_E_memory (int bytemode, int sizeflag)
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int havebase;
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int haveindex;
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int needindex;
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int needaddr32;
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int base, rbase;
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int vindex = 0;
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int scale = 0;
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@ -15433,12 +15434,27 @@ OP_E_memory (int bytemode, int sizeflag)
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break;
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}
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/* In 32bit mode, we need index register to tell [offset] from
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[eiz*1 + offset]. */
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needindex = (havesib
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&& !havebase
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&& !haveindex
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&& address_mode == mode_32bit);
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needindex = 0;
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needaddr32 = 0;
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if (havesib
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&& !havebase
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&& !haveindex
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&& address_mode != mode_16bit)
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{
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if (address_mode == mode_64bit)
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{
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/* Display eiz instead of addr32. */
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needindex = addr32flag;
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needaddr32 = 1;
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}
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else
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{
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/* In 32-bit mode, we need index register to tell [offset]
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from [eiz*1 + offset]. */
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needindex = 1;
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}
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}
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havedisp = (havebase
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|| needindex
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|| (havesib && (haveindex || scale != 0)));
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@ -15458,7 +15474,7 @@ OP_E_memory (int bytemode, int sizeflag)
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}
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}
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if ((havebase || haveindex || riprel)
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if ((havebase || haveindex || needaddr32 || riprel)
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&& (bytemode != v_bnd_mode)
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&& (bytemode != bnd_mode)
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&& (bytemode != bnd_swap_mode))
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