Rename emit_load_store to aarch64_emit_load_store
Likewise, this patch renames emit_load_store to aarch64_emit_load_store. gdb: 2015-10-12 Yao Qi <yao.qi@linaro.org> * arch/aarch64-insn.c (emit_load_store): Rename to ... (aarch64_emit_load_store): ... it. All callers updated. gdb/gdbserver: 2015-10-12 Yao Qi <yao.qi@linaro.org> * linux-aarch64-low.c: Update all callers as emit_load_store is renamed to aarch64_emit_load_store.
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@ -1,3 +1,8 @@
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2015-10-12 Yao Qi <yao.qi@linaro.org>
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* arch/aarch64-insn.c (emit_load_store): Rename to ...
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(aarch64_emit_load_store): ... it. All callers updated.
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2015-10-12 Yao Qi <yao.qi@linaro.org>
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* arch/aarch64-insn.c (emit_insn): Rename to ...
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@ -342,11 +342,11 @@ aarch64_emit_insn (uint32_t *buf, uint32_t insn)
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/* Helper function emitting a load or store instruction. */
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int
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emit_load_store (uint32_t *buf, uint32_t size,
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enum aarch64_opcodes opcode,
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struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand)
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aarch64_emit_load_store (uint32_t *buf, uint32_t size,
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enum aarch64_opcodes opcode,
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struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand)
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{
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uint32_t op;
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@ -269,7 +269,7 @@ void aarch64_relocate_instruction (uint32_t insn,
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0 .. 32760 range (12 bits << 3). */
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#define emit_ldr(buf, rt, rn, operand) \
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emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)
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aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)
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/* Write a LDRSW instruction into *BUF. The register size is 64-bit.
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@ -283,7 +283,7 @@ void aarch64_relocate_instruction (uint32_t insn,
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0 .. 16380 range (12 bits << 2). */
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#define emit_ldrsw(buf, rt, rn, operand) \
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emit_load_store (buf, 3, LDRSW, rt, rn, operand)
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aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand)
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/* Write a TBZ or TBNZ instruction into *BUF.
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@ -312,10 +312,10 @@ void aarch64_relocate_instruction (uint32_t insn,
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int aarch64_emit_insn (uint32_t *buf, uint32_t insn);
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int emit_load_store (uint32_t *buf, uint32_t size,
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enum aarch64_opcodes opcode,
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struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand);
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int aarch64_emit_load_store (uint32_t *buf, uint32_t size,
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enum aarch64_opcodes opcode,
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struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand);
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#endif
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@ -1,3 +1,8 @@
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2015-10-12 Yao Qi <yao.qi@linaro.org>
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* linux-aarch64-low.c: Update all callers as emit_load_store
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is renamed to aarch64_emit_load_store.
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2015-10-12 Yao Qi <yao.qi@linaro.org>
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* linux-aarch64-low.c: Update all callers of function renaming
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@ -902,7 +902,7 @@ emit_ldrh (uint32_t *buf, struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand)
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{
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return emit_load_store (buf, 1, LDR, rt, rn, operand);
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return aarch64_emit_load_store (buf, 1, LDR, rt, rn, operand);
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}
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/* Write a LDRB instruction into *BUF.
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@ -921,7 +921,7 @@ emit_ldrb (uint32_t *buf, struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand)
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{
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return emit_load_store (buf, 0, LDR, rt, rn, operand);
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return aarch64_emit_load_store (buf, 0, LDR, rt, rn, operand);
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}
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@ -942,7 +942,7 @@ emit_str (uint32_t *buf, struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand)
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{
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return emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
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return aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
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}
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/* Helper function emitting an exclusive load or store instruction. */
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