[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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@ -1,3 +1,13 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
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* libbfd.h: Regenerated.
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* bfd-in2.h: Regenerated.
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* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
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(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
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and R_ARM_THM_BF18 together.
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(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
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@ -3570,6 +3570,9 @@ field in the instruction. */
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/* ARM 17-bit pc-relative branch for Branch Future instructions. */
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BFD_RELOC_ARM_THUMB_BF17,
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/* ARM 19-bit pc-relative branch for Branch Future Link instruction. */
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BFD_RELOC_ARM_THUMB_BF19,
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/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
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The lowest bit must be zero and is not stored in the instruction.
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Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
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@ -1756,6 +1756,20 @@ static reloc_howto_type elf32_arm_howto_table_1[] =
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0x001f0ffe, /* src_mask. */
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0x001f0ffe, /* dst_mask. */
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TRUE), /* pcrel_offset. */
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EMPTY_HOWTO (137),
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HOWTO (R_ARM_THM_BF18, /* type. */
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0, /* rightshift. */
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1, /* size (0 = byte, 1 = short, 2 = long). */
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18, /* bitsize. */
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TRUE, /* pc_relative. */
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0, /* bitpos. */
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complain_overflow_dont,/* do not complain_on_overflow. */
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bfd_elf_generic_reloc, /* special_function. */
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"R_ARM_THM_BF18", /* name. */
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FALSE, /* partial_inplace. */
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0x007f0ffe, /* src_mask. */
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0x007f0ffe, /* dst_mask. */
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TRUE), /* pcrel_offset. */
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};
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/* 160 onwards: */
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@ -2068,7 +2082,8 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
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{BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
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{BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
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{BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
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{BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16}
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{BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
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{BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
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};
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static reloc_howto_type *
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@ -12969,6 +12984,51 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
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return bfd_reloc_ok;
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}
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case R_ARM_THM_BF18:
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{
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bfd_vma relocation;
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bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
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bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
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if (globals->use_rel)
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{
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bfd_vma immA = (upper_insn & 0x007f);
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bfd_vma immB = (lower_insn & 0x07fe) >> 1;
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bfd_vma immC = (lower_insn & 0x0800) >> 11;
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addend = (immA << 12);
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addend |= (immB << 2);
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addend |= (immC << 1);
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addend |= 1;
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/* Sign extend. */
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addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
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}
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value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
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info, input_bfd, rel, sym_name, st_type,
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globals, unresolved_reloc_p);
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relocation = value + addend;
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relocation -= (input_section->output_section->vma
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+ input_section->output_offset
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+ rel->r_offset);
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/* Put RELOCATION back into the insn. */
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{
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bfd_vma immA = (relocation & 0x0007f000) >> 12;
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bfd_vma immB = (relocation & 0x00000ffc) >> 2;
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bfd_vma immC = (relocation & 0x00000002) >> 1;
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upper_insn = (upper_insn & 0xff80) | immA;
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lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
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}
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/* Put the relocated value back in the object file: */
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bfd_put_16 (input_bfd, upper_insn, hit_data);
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bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
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return bfd_reloc_ok;
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}
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default:
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return bfd_reloc_notsupported;
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}
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@ -1531,6 +1531,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
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"BFD_RELOC_ARM_PCREL_JUMP",
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"BFD_RELOC_THUMB_PCREL_BRANCH5",
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"BFD_RELOC_ARM_THUMB_BF17",
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"BFD_RELOC_ARM_THUMB_BF19",
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"BFD_RELOC_THUMB_PCREL_BRANCH7",
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"BFD_RELOC_THUMB_PCREL_BRANCH9",
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"BFD_RELOC_THUMB_PCREL_BRANCH12",
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@ -3024,6 +3024,11 @@ ENUM
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ENUMDOC
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ARM 17-bit pc-relative branch for Branch Future instructions.
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ENUM
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BFD_RELOC_ARM_THUMB_BF19
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ENUMDOC
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ARM 19-bit pc-relative branch for Branch Future Link instruction.
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ENUM
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BFD_RELOC_THUMB_PCREL_BRANCH7
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ENUMX
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@ -1,3 +1,7 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm.h (R_ARM_THM_BF18): New relocation code.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm.h (R_ARM_THM_BF16): New relocation code.
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@ -197,6 +197,7 @@ enum
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// 131 - 135 Unallocated
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// Relocations for Armv8.1-M Mainline (BF/BFL)
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R_ARM_THM_BF16 = 136, // Static Thumb32 ((S + A) | T) – P
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R_ARM_THM_BF18 = 138, // Static Thumb32 ((S + A) | T) – P
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// 139 Unallocated
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// 140 - 159 Dynamic Reserved for future allocation
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R_ARM_IRELATIVE = 160, // Dynamic
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@ -1,3 +1,10 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (md_pcrel_from_section): New switch case for
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BFD_RELOC_ARM_THUMB_BF19.
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(md_appdy_fix): Likewise.
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(tc_gen_reloc): Likewise.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
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@ -22924,6 +22924,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
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case BFD_RELOC_THUMB_PCREL_BRANCH20:
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case BFD_RELOC_THUMB_PCREL_BRANCH25:
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case BFD_RELOC_ARM_THUMB_BF17:
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case BFD_RELOC_ARM_THUMB_BF19:
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return base + 4;
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case BFD_RELOC_THUMB_PCREL_BRANCH23:
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@ -24854,6 +24855,39 @@ md_apply_fix (fixS * fixP,
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}
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break;
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case BFD_RELOC_ARM_THUMB_BF19:
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if (fixP->fx_addsy
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&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
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&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
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&& ARM_IS_FUNC (fixP->fx_addsy)
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&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
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{
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/* Force a relocation for a branch 19 bits wide. */
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fixP->fx_done = 0;
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}
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if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
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as_bad_where (fixP->fx_file, fixP->fx_line,
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BAD_BRANCH_OFF);
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if (fixP->fx_done || !seg->use_rela_p)
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{
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offsetT newval2;
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addressT immA, immB, immC;
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immA = (value & 0x0007f000) >> 12;
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immB = (value & 0x00000ffc) >> 2;
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immC = (value & 0x00000002) >> 1;
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newval = md_chars_to_number (buf, THUMB_SIZE);
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newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
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newval |= immA;
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newval2 |= (immC << 11) | (immB << 1);
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md_number_to_chars (buf, newval, THUMB_SIZE);
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md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
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}
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break;
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case BFD_RELOC_ARM_V4BX:
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/* This will need to go in the object file. */
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fixP->fx_done = 0;
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case BFD_RELOC_ARM_GOTOFFFUNCDESC:
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case BFD_RELOC_ARM_FUNCDESC:
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case BFD_RELOC_ARM_THUMB_BF17:
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case BFD_RELOC_ARM_THUMB_BF19:
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code = fixp->fx_r_type;
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break;
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@ -1,3 +1,7 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
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@ -242,6 +242,7 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
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RELOC_NUMBER (R_ARM_THM_ALU_ABS_G2_NC,134)
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RELOC_NUMBER (R_ARM_THM_ALU_ABS_G3_NC,135)
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RELOC_NUMBER (R_ARM_THM_BF16, 136)
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RELOC_NUMBER (R_ARM_THM_BF18, 138)
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RELOC_NUMBER (R_ARM_IRELATIVE, 160)
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RELOC_NUMBER (R_ARM_GOTFUNCDESC, 161)
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@ -1,3 +1,7 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
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@ -2715,6 +2715,7 @@ static const struct opcode16 thumb_opcodes[] =
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%F print the lsb and width fields of a sbfx/ubfx instruction
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%G print a fallback offset for Branch Future instructions
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%W print an offset for BF instruction
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%Y print an offset for BFL instruction
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%b print a conditional branch offset
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%B print an unconditional branch offset
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%s print the shift field of an SSAT instruction
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@ -5898,6 +5899,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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}
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break;
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case 'Y':
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{
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unsigned int immA = (given & 0x007f0000u) >> 16;
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unsigned int immB = (given & 0x000007feu) >> 1;
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unsigned int immC = (given & 0x00000800u) >> 11;
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bfd_vma offset = 0;
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offset |= immA << 12;
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offset |= immB << 2;
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offset |= immC << 1;
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/* Sign extend. */
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offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
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info->print_address_func (pc + 4 + offset, info);
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}
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break;
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case 'b':
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{
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unsigned int S = (given & 0x04000000u) >> 26;
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