(hppa_fix_adjustable): Don't reduce certain symbols to section syms.
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@ -1,3 +1,10 @@
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2000-07-15 Alan Modra <alan@linuxcare.com.au>
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* config/tc-hppa.c (hppa_fix_adjustable): Use the same checks for
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ELF as are used for SOM (except the 32-bit reloc one) to decide
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whether a symbol can be reduced to a section symbol. Expand on
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the comment for symbols involved in LR% and RR% expressions.
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2000-07-14 Nick Clifton <nickc@cygnus.com>
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2000-07-14 Nick Clifton <nickc@cygnus.com>
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* config/tc-mips.c (mips_disable_float_construction): New
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* config/tc-mips.c (mips_disable_float_construction): New
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@ -4431,7 +4431,7 @@ md_apply_fix (fixP, valp)
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}
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}
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#endif
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#endif
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insn = bfd_get_32 (stdoutput, (unsigned char *)buf);
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insn = bfd_get_32 (stdoutput, (unsigned char *) buf);
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/* There should have been an HPPA specific fixup associated
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/* There should have been an HPPA specific fixup associated
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with the GAS fixup. */
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with the GAS fixup. */
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if (hppa_fixP)
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if (hppa_fixP)
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@ -8342,6 +8342,7 @@ hppa_fix_adjustable (fixp)
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/* Reject reductions of symbols in 32bit relocs. */
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/* Reject reductions of symbols in 32bit relocs. */
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if (fixp->fx_r_type == R_HPPA && hppa_fix->fx_r_format == 32)
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if (fixp->fx_r_type == R_HPPA && hppa_fix->fx_r_format == 32)
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return 0;
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return 0;
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#endif
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/* Reject reductions of symbols in sym1-sym2 expressions when
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/* Reject reductions of symbols in sym1-sym2 expressions when
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the fixup will occur in a CODE subspace.
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the fixup will occur in a CODE subspace.
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@ -8359,12 +8360,38 @@ hppa_fix_adjustable (fixp)
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}
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}
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/* We can't adjust any relocs that use LR% and RR% field selectors.
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/* We can't adjust any relocs that use LR% and RR% field selectors.
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That confuses the HP linker. */
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If a symbol is reduced to a section symbol, the assembler will
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adjust the addend unless the symbol happens to reside right at
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the start of the section. Additionally, the linker has no choice
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but to manipulate the addends when coalescing input sections for
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"ld -r". Since an LR% field selector is defined to round the
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addend, we can't change the addend without risking that a LR% and
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it's corresponding (possible multiple) RR% field will no longer
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sum to the right value.
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eg. Suppose we have
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. ldil LR%foo+0,%r21
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. ldw RR%foo+0(%r21),%r26
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. ldw RR%foo+10(%r21),%r25
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If foo is at address 4090 (decimal) in section `sect', then after
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reducing to the section symbol, we get
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. LR%sect+4090 == L%sect+0
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. RR%sect+4090 == R%sect+4090
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. RR%sect+4100 == R%sect-4092 (4100 - 8192)
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and the last address loses.
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Obviously, in cases where the LR% expression is identical to the
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RR% one we will never have a problem, but is so happens that gcc
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rounds addends involved in LR% field selectors to work around a
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HP linker bug. ie. We often have addresses like the last case
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above where the LR% expression is offset from the RR% one. */
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if (hppa_fix->fx_r_field == e_lrsel
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if (hppa_fix->fx_r_field == e_lrsel
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|| hppa_fix->fx_r_field == e_rrsel
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|| hppa_fix->fx_r_field == e_rrsel
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|| hppa_fix->fx_r_field == e_nlrsel)
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|| hppa_fix->fx_r_field == e_nlrsel)
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return 0;
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return 0;
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#endif
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/* Reject reductions of symbols in DLT relative relocs,
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/* Reject reductions of symbols in DLT relative relocs,
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relocations with plabels. */
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relocations with plabels. */
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