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Fix invalid left shift of negative value 

Fix occurrences of left-shifting negative constants in C code.

sim/arm/ChangeLog:

	* thumbemu.c (handle_T2_insn): Fix left shift of negative value.
	* armemu.c (handle_v6_insn): Likewise.

sim/avr/ChangeLog:

	* interp.c (sign_ext): Fix left shift of negative value.

sim/mips/ChangeLog:

	* micromips.igen (process_isa_mode): Fix left shift of negative
	value.

sim/msp430/ChangeLog:

	* msp430-sim.c (get_op, put_op): Fix left shift of negative value.

sim/v850/ChangeLog:

	* simops.c (v850_bins): Fix left shift of negative value.
This commit is contained in:
Dominik Vogt 2015-12-15 14:09:14 +01:00 committed by Andreas Arnez
parent 08832196ac
commit 1d19cae752
11 changed files with 55 additions and 33 deletions
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5
sim/arm/ChangeLog
View File

@ -1,3 +1,8 @@
2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
* thumbemu.c (handle_T2_insn): Fix left shift of negative value.
* armemu.c (handle_v6_insn): Likewise.
2015-11-14 Mike Frysinger <vapier@gentoo.org> 2015-11-14 Mike Frysinger <vapier@gentoo.org>
* wrapper.c (sim_close): Delete. * wrapper.c (sim_close): Delete.

40
sim/arm/armemu.c
View File

@ -351,11 +351,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{ {
n = (val1 >> i) & 0xFFFF; n = (val1 >> i) & 0xFFFF;
if (n & 0x8000) if (n & 0x8000)
n |= -1 << 16; n |= -(1 << 16);
m = (val2 >> i) & 0xFFFF; m = (val2 >> i) & 0xFFFF;
if (m & 0x8000) if (m & 0x8000)
m |= -1 << 16; m |= -(1 << 16);
r = n + m; r = n + m;
@ -371,11 +371,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */ case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
n = val1 & 0xFFFF; n = val1 & 0xFFFF;
if (n & 0x8000) if (n & 0x8000)
n |= -1 << 16; n |= -(1 << 16);
m = (val2 >> 16) & 0xFFFF; m = (val2 >> 16) & 0xFFFF;
if (m & 0x8000) if (m & 0x8000)
m |= -1 << 16; m |= -(1 << 16);
r = n - m; r = n - m;
@ -388,11 +388,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
n = (val1 >> 16) & 0xFFFF; n = (val1 >> 16) & 0xFFFF;
if (n & 0x8000) if (n & 0x8000)
n |= -1 << 16; n |= -(1 << 16);
m = val2 & 0xFFFF; m = val2 & 0xFFFF;
if (m & 0x8000) if (m & 0x8000)
m |= -1 << 16; m |= -(1 << 16);
r = n + m; r = n + m;
@ -407,11 +407,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */ case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
n = val1 & 0xFFFF; n = val1 & 0xFFFF;
if (n & 0x8000) if (n & 0x8000)
n |= -1 << 16; n |= -(1 << 16);
m = (val2 >> 16) & 0xFFFF; m = (val2 >> 16) & 0xFFFF;
if (m & 0x8000) if (m & 0x8000)
m |= -1 << 16; m |= -(1 << 16);
r = n + m; r = n + m;
@ -424,11 +424,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
n = (val1 >> 16) & 0xFFFF; n = (val1 >> 16) & 0xFFFF;
if (n & 0x8000) if (n & 0x8000)
n |= -1 << 16; n |= -(1 << 16);
m = val2 & 0xFFFF; m = val2 & 0xFFFF;
if (m & 0x8000) if (m & 0x8000)
m |= -1 << 16; m |= -(1 << 16);
r = n - m; r = n - m;
@ -447,11 +447,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{ {
n = (val1 >> i) & 0xFFFF; n = (val1 >> i) & 0xFFFF;
if (n & 0x8000) if (n & 0x8000)
n |= -1 << 16; n |= -(1 << 16);
m = (val2 >> i) & 0xFFFF; m = (val2 >> i) & 0xFFFF;
if (m & 0x8000) if (m & 0x8000)
m |= -1 << 16; m |= -(1 << 16);
r = n - m; r = n - m;
@ -471,11 +471,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{ {
n = (val1 >> i) & 0xFF; n = (val1 >> i) & 0xFF;
if (n & 0x80) if (n & 0x80)
n |= -1 << 8; n |= - (1 << 8);
m = (val2 >> i) & 0xFF; m = (val2 >> i) & 0xFF;
if (m & 0x80) if (m & 0x80)
m |= -1 << 8; m |= - (1 << 8);
r = n + m; r = n + m;
@ -495,11 +495,11 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
{ {
n = (val1 >> i) & 0xFF; n = (val1 >> i) & 0xFF;
if (n & 0x80) if (n & 0x80)
n |= -1 << 8; n |= - (1 << 8);
m = (val2 >> i) & 0xFF; m = (val2 >> i) & 0xFF;
if (m & 0x80) if (m & 0x80)
m |= -1 << 8; m |= - (1 << 8);
r = n - m; r = n - m;
@ -951,14 +951,14 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
state->Emulate = FALSE; state->Emulate = FALSE;
} }
mask = -1 << lsb; mask = -(1 << lsb);
mask &= ~(-1 << (msb + 1)); mask &= ~(-(1 << (msb + 1)));
state->Reg[Rd] &= ~ mask; state->Reg[Rd] &= ~ mask;
Rn = BITS (0, 3); Rn = BITS (0, 3);
if (Rn != 0xF) if (Rn != 0xF)
{ {
ARMword val = state->Reg[Rn] & ~(-1 << ((msb + 1) - lsb)); ARMword val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
state->Reg[Rd] |= val << lsb; state->Reg[Rd] |= val << lsb;
} }
return 1; return 1;
@ -1036,7 +1036,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
val = state->Reg[Rn]; val = state->Reg[Rn];
val >>= lsb; val >>= lsb;
val &= ~(-1 << (widthm1 + 1)); val &= ~(-(1 << (widthm1 + 1)));
state->Reg[Rd] = val; state->Reg[Rd] = val;

16
sim/arm/thumbemu.c
View File

@ -204,7 +204,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (J1 << 19) | (J2 << 18) | (imm6 << 12) | (imm11 << 1); simm32 = (J1 << 19) | (J2 << 18) | (imm6 << 12) | (imm11 << 1);
if (S) if (S)
simm32 |= (-1 << 20); simm32 |= -(1 << 20);
break; break;
} }
@ -217,7 +217,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
if (S) if (S)
simm32 |= (-1 << 24); simm32 |= -(1 << 24);
break; break;
} }
@ -230,7 +230,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (I1 << 23) | (I2 << 22) | (imm10h << 12) | (imm10l << 2); simm32 = (I1 << 23) | (I2 << 22) | (imm10h << 12) | (imm10l << 2);
if (S) if (S)
simm32 |= (-1 << 24); simm32 |= -(1 << 24);
CLEART; CLEART;
state->Reg[14] = (pc + 4) | 1; state->Reg[14] = (pc + 4) | 1;
@ -246,7 +246,7 @@ handle_T2_insn (ARMul_State * state,
simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
if (S) if (S)
simm32 |= (-1 << 24); simm32 |= -(1 << 24);
state->Reg[14] = (pc + 4) | 1; state->Reg[14] = (pc + 4) | 1;
break; break;
} }
@ -1078,7 +1078,7 @@ handle_T2_insn (ARMul_State * state,
ARMword Rn = tBITS (0, 3); ARMword Rn = tBITS (0, 3);
ARMword msbit = ntBITS (0, 5); ARMword msbit = ntBITS (0, 5);
ARMword lsbit = (ntBITS (12, 14) << 2) | ntBITS (6, 7); ARMword lsbit = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
ARMword mask = -1 << lsbit; ARMword mask = -(1 << lsbit);
tASSERT (tBIT (4) == 0); tASSERT (tBIT (4) == 0);
tASSERT (ntBIT (15) == 0); tASSERT (ntBIT (15) == 0);
@ -1489,7 +1489,7 @@ handle_T2_insn (ARMul_State * state,
state->Reg[Rt] = ARMul_LoadByte (state, address); state->Reg[Rt] = ARMul_LoadByte (state, address);
if (state->Reg[Rt] & 0x80) if (state->Reg[Rt] & 0x80)
state->Reg[Rt] |= -1 << 8; state->Reg[Rt] |= -(1 << 8);
* pvalid = t_resolved; * pvalid = t_resolved;
break; break;
@ -1542,7 +1542,7 @@ handle_T2_insn (ARMul_State * state,
state->Reg[Rt] = ARMul_LoadHalfWord (state, address); state->Reg[Rt] = ARMul_LoadHalfWord (state, address);
if (state->Reg[Rt] & 0x8000) if (state->Reg[Rt] & 0x8000)
state->Reg[Rt] |= -1 << 16; state->Reg[Rt] |= -(1 << 16);
* pvalid = t_branch; * pvalid = t_branch;
break; break;
@ -1564,7 +1564,7 @@ handle_T2_insn (ARMul_State * state,
val = state->Reg[Rm]; val = state->Reg[Rm];
val = (val >> ror) | (val << (32 - ror)); val = (val >> ror) | (val << (32 - ror));
if (val & 0x8000) if (val & 0x8000)
val |= -1 << 16; val |= -(1 << 16);
state->Reg[Rd] = val; state->Reg[Rd] = val;
} }
else else

4
sim/avr/ChangeLog
View File

@ -1,3 +1,7 @@
2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
* interp.c (sign_ext): Fix left shift of negative value.
2015-11-21 Mike Frysinger <vapier@gentoo.org> 2015-11-21 Mike Frysinger <vapier@gentoo.org>
* interp.c (pc, cycles, avr_pc22): Delete. * interp.c (pc, cycles, avr_pc22): Delete.

2
sim/avr/interp.c
View File

@ -222,7 +222,7 @@ static byte sram[MAX_AVR_SRAM];
static int sign_ext (word val, int nb_bits) static int sign_ext (word val, int nb_bits)
{ {
if (val & (1 << (nb_bits - 1))) if (val & (1 << (nb_bits - 1)))
return val | (-1 << nb_bits); return val | -(1 << nb_bits);
return val; return val;
} }

5
sim/mips/ChangeLog
View File

@ -1,3 +1,8 @@
2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
* micromips.igen (process_isa_mode): Fix left shift of negative
value.
2015-11-17 Mike Frysinger <vapier@gentoo.org> 2015-11-17 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (WITH_MODULO_MEMORY): Delete. * sim-main.h (WITH_MODULO_MEMORY): Delete.

2
sim/mips/micromips.igen
View File

@ -54,7 +54,7 @@
:function:::address_word:process_isa_mode:address_word target :function:::address_word:process_isa_mode:address_word target
{ {
SD->isa_mode = target & 0x1; SD->isa_mode = target & 0x1;
return (target & (-1 << 1)); return (target & (-(1 << 1)));
} }
:function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size

4
sim/msp430/ChangeLog
View File

@ -1,3 +1,7 @@
2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
* msp430-sim.c (get_op, put_op): Fix left shift of negative value.
2015-12-07 Nick Clifton <nickc@redhat.com> 2015-12-07 Nick Clifton <nickc@redhat.com>
* msp430-sim.c (sim_open): Check for needed memory at address * msp430-sim.c (sim_open): Check for needed memory at address

4
sim/msp430/msp430-sim.c
View File

@ -364,7 +364,7 @@ get_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n)
/* Index values are signed. */ /* Index values are signed. */
if (addr & (1 << (sign - 1))) if (addr & (1 << (sign - 1)))
addr |= -1 << sign; addr |= -(1 << sign);
addr += reg; addr += reg;
@ -565,7 +565,7 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
/* Index values are signed. */ /* Index values are signed. */
if (addr & (1 << (sign - 1))) if (addr & (1 << (sign - 1)))
addr |= -1 << sign; addr |= -(1 << sign);
addr += reg; addr += reg;

4
sim/v850/ChangeLog
View File

@ -1,3 +1,7 @@
2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
* simops.c (v850_bins): Fix left shift of negative value.
2015-11-17 Mike Frysinger <vapier@gentoo.org> 2015-11-17 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (WITH_CORE): Delete. * sim-main.h (WITH_CORE): Delete.

2
sim/v850/simops.c
View File

@ -3317,7 +3317,7 @@ v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb,
pos = lsb; pos = lsb;
width = (msb - lsb) + 1; width = (msb - lsb) + 1;
mask = ~ (-1 << width); mask = ~ (-(1 << width));
source &= mask; source &= mask;
mask <<= pos; mask <<= pos;
result = (* dest) & ~ mask; result = (* dest) & ~ mask;