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* Initial Device Support 

*
*Modified Files:
*    .Sanitize ChangeLog
*Added Files:
*    Makefile.in README.Cygnus config.in configure configure.in
*    device.c device.h dma.c dma.h engine-sky.c gencode.c gpuif.c
*    gpuif.h hardware.c hardware.h interp.c m16.igen mdmx.igen
*    mips.dc mips.igen pke0.c pke0.h pke1.c pke1.h r5900.igen
*    sim-main.h tconfig.in vr5400.igen vu0.c vu0.h vu1.c vu1.h
This commit is contained in:
Ian Carmichael 1998-01-16 19:27:02 +00:00
parent 8e12359329
commit 1e1e3b618f
34 changed files with 24805 additions and 0 deletions
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32
sim/txvu/.Sanitize
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@ -25,6 +25,38 @@ Do-first:
Things-to-keep:
ChangeLog
interp.c
configure.in
Makefile.in
config.in
tconfig.in
README.Cygnus
configure
gencode.c
m16.igen
mdmx.igen
mips.dc
mips.igen
r5900.igen
sim-main.h
vr5400.igen
engine-sky.c
gpuif.h
dma.h
device.c
gpuif.c
device.h
dma.c
vu0.h
pke0.h
vu1.h
pke1.h
vu1.c
vu0.c
pke0.c
pke1.c
hardware.c
hardware.h
Things-to-lose:

4
sim/txvu/ChangeLog
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@ -1,3 +1,7 @@
Fri Jan 16 14:25:54 1998 Ian Carmichael <iancarm@cygnus.com>
* Initial Device Support
Thu Jan 15 10:25:54 1998 Ian Carmichael <iancarm@cygnus.com>
* ChangeLog created

260
sim/txvu/Makefile.in Normal file
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# template for Configure for the MIPS simulator.
# Written by Cygnus Support.
## COMMON_PRE_CONFIG_FRAG
srcdir=@srcdir@
srcroot=$(srcdir)/../../
SIM_NO_OBJ =
SIM_IGEN_OBJ = \
support.o \
itable.o \
semantics.o \
idecode.o \
icache.o \
irun.o
SIM_M16_OBJ = \
$(SIM_IGEN_OBJ) = \
m16_support.o \
m16_itable.o \
m16_semantics.o \
m16_idecode.o \
m16_icache.o \
m16_engine.o \
m16_irun.o
SIM_OBJS = \
$(SIM_@sim_gen@_OBJ) \
$(SIM_NEW_COMMON_OBJS) \
engine-sky.o \
interp.o \
hardware.o \
device.o \
gpuif.o \
dma.o \
vu0.o \
vu1.o \
pke0.o \
pke1.o \
sim-hload.o \
sim-engine.o \
sim-stop.o \
sim-resume.o \
sim-reason.o
# List of flags to always pass to $(CC).
SIM_SUBTARGET=@SIM_SUBTARGET@
SIM_NO_CFLAGS = -DWITH_IGEN=0
SIM_IGEN_CFLAGS = -DWITH_IGEN=1
SIM_M16_CFLAGS = -DWITH_IGEN=1
# FIXME: Hack to find syscall.h? Better support for syscall.h
# is in progress.
SIM_EXTRA_CFLAGS = \
$(SIM_SUBTARGET) \
-I$(srcdir)/../../newlib/libc/sys/idt \
$(SIM_@sim_gen@_CFLAGS)
SIM_EXTRA_CLEAN = clean-igen clean-m16 clean-extra
SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o
## COMMON_POST_CONFIG_FRAG
interp.o: $(srcdir)/interp.c config.h sim-main.h oengine.c
oengine.c: gencode
./gencode @SIMCONF@ > tmp-oengine
mv tmp-oengine oengine.c
gencode: gencode.o getopt.o getopt1.o
$(CC_FOR_BUILD) -o $@ gencode.o getopt.o getopt1.o
gencode.o: $(srcdir)/gencode.c
$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/gencode.c
getopt.o: $(srcdir)/../../libiberty/getopt.c
$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt.c
getopt1.o: $(srcdir)/../../libiberty/getopt1.c
$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt1.c
../igen/igen:
cd ../igen && $(MAKE)
IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
IGEN_INSN=$(srcdir)/mips.igen
IGEN_DC=$(srcdir)/mips.dc
IGEN_INCLUDE=\
$(start-sanitize-r5900) \
$(srcdir)/r5900.igen \
$(end-sanitize-r5900) \
$(start-sanitize-vr5400) \
$(srcdir)/vr5400.igen \
$(srcdir)/mdmx.igen \
$(end-sanitize-vr5400) \
$(srcdir)/m16.igen
SIM_IGEN_ALL = tmp-igen
BUILT_SRC_FROM_IGEN = \
icache.h \
icache.c \
idecode.h \
idecode.c \
semantics.h \
semantics.c \
model.h \
model.c \
support.h \
support.c \
itable.h \
itable.c \
engine.h \
engine.c \
irun.c
$(BUILT_SRC_FROM_IGEN): tmp-igen
.PHONY: clean-igen
clean-igen:
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f tmp-igen
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_igen_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-x \
-n icache.h -hc tmp-icache.h \
-n icache.c -c tmp-icache.c \
-n semantics.h -hs tmp-semantics.h \
-n semantics.c -s tmp-semantics.c \
-n idecode.h -hd tmp-idecode.h \
-n idecode.c -d tmp-idecode.c \
-n model.h -hm tmp-model.h \
-n model.c -m tmp-model.c \
-n support.h -hf tmp-support.h \
-n support.c -f tmp-support.c \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
-n engine.h -he tmp-engine.h \
-n engine.c -e tmp-engine.c \
-n irun.c -r tmp-irun.c
$(srcdir)/../../move-if-change tmp-icache.h icache.h
$(srcdir)/../../move-if-change tmp-icache.c icache.c
$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
$(srcdir)/../../move-if-change tmp-model.h model.h
$(srcdir)/../../move-if-change tmp-model.c model.c
$(srcdir)/../../move-if-change tmp-support.h support.h
$(srcdir)/../../move-if-change tmp-support.c support.c
$(srcdir)/../../move-if-change tmp-itable.h itable.h
$(srcdir)/../../move-if-change tmp-itable.c itable.c
$(srcdir)/../../move-if-change tmp-engine.h engine.h
$(srcdir)/../../move-if-change tmp-engine.c engine.c
$(srcdir)/../../move-if-change tmp-irun.c irun.c
touch tmp-igen
semantics.o: sim-main.h $(SIM_EXTRA_DEPS)
engine.o: sim-main.h $(SIM_EXTRA_DEPS)
support.o: sim-main.h $(SIM_EXTRA_DEPS)
idecode.o: sim-main.h $(SIM_EXTRA_DEPS)
itable.o: sim-main.h $(SIM_EXTRA_DEPS)
SIM_M16_ALL = tmp-igen $(SIM_M16_ALL)
BUILT_SRC_FROM_M16 = \
m16_icache.h \
m16_icache.c \
m16_idecode.h \
m16_idecode.c \
m16_semantics.h \
m16_semantics.c \
m16_model.h \
m16_model.c \
m16_support.h \
m16_support.c \
m16_itable.h \
m16_itable.c \
m16_engine.h \
m16_engine.c \
m16_irun.c
$(BUILT_SRC_FROM_M16): tmp-m16
.PHONY: clean-m16
clean-m16:
rm -f $(BUILT_SRC_FROM_M16)
rm -f tmp-m16
tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
-F 16 \
-M mips16 \
-G gen-direct-access \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-x \
-n m16_icache.h -hc tmp-icache.h \
-n m16_icache.c -c tmp-icache.c \
-n m16_semantics.h -hs tmp-semantics.h \
-n m16_semantics.c -s tmp-semantics.c \
-n m16_idecode.h -hd tmp-idecode.h \
-n m16_idecode.c -d tmp-idecode.c \
-n m16_model.h -hm tmp-model.h \
-n m16_model.c -m tmp-model.c \
-n m16_support.h -hf tmp-support.h \
-n m16_support.c -f tmp-support.c \
-n m16_itable.h -ht tmp-itable.h \
-n m16_itable.c -t tmp-itable.c \
-n m16_engine.h -he tmp-engine.h \
-n m16_engine.c -e tmp-engine.c \
-n m16_irun.c -r tmp-irun.c
$(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
$(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
$(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
$(srcdir)/../../move-if-change tmp-model.h m16_model.h
$(srcdir)/../../move-if-change tmp-model.c m16_model.c
$(srcdir)/../../move-if-change tmp-support.h m16_support.h
$(srcdir)/../../move-if-change tmp-support.c m16_support.c
$(srcdir)/../../move-if-change tmp-itable.h m16_itable.h
$(srcdir)/../../move-if-change tmp-itable.c m16_itable.c
$(srcdir)/../../move-if-change tmp-engine.h m16_engine.h
$(srcdir)/../../move-if-change tmp-engine.c m16_engine.c
$(srcdir)/../../move-if-change tmp-irun.c m16_irun.c
touch tmp-m16
clean-extra:
rm -f gencode oengine.c tmp.igen

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> README.Cygnus
-------------------------------------------------------------------------------
The following are the main reasons for constructing the simulator as a
generator:
1) Avoid large fixed decode source file, with lots of #ifs controlling
the compilation. i.e. keep the source cleaner, smaller and easier
to parse.
2) Allow optimum code to be created, without run-time checks on
instruction types. Ensure that the simulator engine only includes
code for the architecture being targetted. e.g. This avoids
run-time checks on ISA conformance, aswell as increasing
throughput.
3) Allow updates to the instruction sets to be added quickly. Having a
table means that the information is together, and is easier to
manipulate. Having the table generate the engine, rather than the
run-time parse the table gives higher performance at simulation
time.
4) Keep all the similar simulation code together. i.e. have a single
place where, for example, the addition code is held. This ensures that
updates to the simulation are not spread over a large flat source
file maintained by the developer.
-------------------------------------------------------------------------------
To keep the simulator simple (and to avoid the slight chance of
mis-matched files) the manifests describing an engine, and the
simulator engine itself, are held in the same source file.
This means that the engine must be included twice, with the first pass
controlled by the SIM_MANIFESTS definition.
-------------------------------------------------------------------------------
> EOF README.Cygnus

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/* config.in. Generated automatically from configure.in by autoheader. */
/* Define as the return type of signal handlers (int or void). */
#undef RETSIGTYPE
/* Define if your processor stores words with the most significant
byte first (like Motorola and SPARC, unlike Intel and VAX). */
#undef WORDS_BIGENDIAN
/* Define if you have the aint function. */
#undef HAVE_AINT
/* Define if you have the anint function. */
#undef HAVE_ANINT
/* Define if you have the getrusage function. */
#undef HAVE_GETRUSAGE
/* Define if you have the sigaction function. */
#undef HAVE_SIGACTION
/* Define if you have the sqrt function. */
#undef HAVE_SQRT
/* Define if you have the time function. */
#undef HAVE_TIME
/* Define if you have the <stdlib.h> header file. */
#undef HAVE_STDLIB_H
/* Define if you have the <string.h> header file. */
#undef HAVE_STRING_H
/* Define if you have the <strings.h> header file. */
#undef HAVE_STRINGS_H
/* Define if you have the <sys/resource.h> header file. */
#undef HAVE_SYS_RESOURCE_H
/* Define if you have the <sys/time.h> header file. */
#undef HAVE_SYS_TIME_H
/* Define if you have the <time.h> header file. */
#undef HAVE_TIME_H
/* Define if you have the <unistd.h> header file. */
#undef HAVE_UNISTD_H
/* Define if you have the m library (-lm). */
#undef HAVE_LIBM

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dnl Process this file with autoconf to produce a configure script.
sinclude(../common/aclocal.m4)
AC_PREREQ(2.5)dnl
AC_INIT(Makefile.in)
SIM_AC_COMMON
dnl Options available in this module
SIM_AC_OPTION_INLINE(0)
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
SIM_AC_OPTION_HOSTENDIAN
SIM_AC_OPTION_WARNINGS
# Ensure a reasonable default simulator is constructed:
case "${target}" in
# start-sanitize-tx19
mipstx19*-*-*) SIMCONF="-mips1 -mcpu=r1900 -mno-fp --warnings";;
# end-sanitize-tx19
# start-sanitize-tx49
mips64tx49*-*-*) SIMCONF="-mips3 --warnings -mcpu=r4900";;
# end-sanitize-tx49
# start-sanitize-r5900
mips64r59*-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";;
# end-sanitize-r5900
# start-sanitize-sky
txvu-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";;
# end-sanitize-sky
mips64*-*-*) SIMCONF="-mips0 --warnings";;
mips16*-*-*) SIMCONF="-mips0 --warnings";;
mips*-*-*) SIMCONF="-mips2 --warnings";;
*) SIMCONF="-mips0 --warnings";;
esac
AC_SUBST(SIMCONF)
case "${target}" in
# start-sanitize-tx19
mipstx19*-*-*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
# end-sanitize-tx19
*) SIM_SUBTARGET="";;
esac
AC_SUBST(SIM_SUBTARGET)
#
# Select the byte order of the target
#
case "${target}" in
# start-sanitize-tx19
mipstx19*-*-*) mips_endian=0 ;;
# end-sanitize-tx19
# start-sanitize-r5900
mips64r59*-*-*) mips_endian=LITTLE_ENDIAN ;;
# end-sanitize-r5900
# start-sanitize-sky
txvu-*-*) mips_endian=LITTLE_ENDIAN ;;
# end-sanitize-sky
mips64*-*-*) mips_endian=0 ;;
mips16*-*-*) mips_endian=0 ;;
mips*-*-*) mips_endian=0 ;;
*) mips_endian=0 ;;
esac
SIM_AC_OPTION_ENDIAN($mips_endian)
#
# Select the bitsize of the target
#
case "${target}" in
# start-sanitize-tx19
mipstx19*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
# end-sanitize-tx19
# start-sanitize-r5900
mips64r59*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
# end-sanitize-r5900
# start-sanitize-sky
txvu-*-*) mips_bitsize=64 ; mips_msb=63 ;;
# end-sanitize-sky
mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
*) mips_bitsize=64 ; mips_msb=63 ;;
esac
SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb)
#
# Select the floating hardware support of the target
#
mips_fpu=HARDWARE_FLOATING_POINT
case "${target}" in
# start-sanitize-tx19
mipstx19*-*-*) mips_fpu=SOFT_FLOATING_POINT ;;
# end-sanitize-tx19
# start-sanitize-r5900
mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
# end-sanitize-r5900
# start-sanitize-sky
txvu-*-*) mips_fpu=HARD_FLOATING_POINT ;;
# end-sanitize-sky
mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mips*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
*) mips_fpu=HARD_FLOATING_POINT ;;
esac
SIM_AC_OPTION_FLOAT($mips_fpu)
#
# Select the IGEN architecture
#
sim_use_gen=NO
sim_igen_machine="-M mipsIV"
sim_m16_machine="-M mips16"
sim_igen_filter="32,64,f"
sim_m16_filter="16"
case "${target}" in
# start-sanitize-tx19
mipstx19*-*-*) sim_default_gen=M16
sim_igen_machine="-M tx19"
sim_m16_machine="-M tx19"
sim_igen_filter="32"
sim_m16_filter="16"
;;
# end-sanitize-tx19
# start-sanitize-r5900
mips64r59*-*-*) sim_default_gen=IGEN
sim_igen_machine="-M r5900"
;;
# end-sanitize-r5900
# start-sanitize-sky
txvu-*-*) sim_default_gen=IGEN
sim_igen_machine="-M r5900"
;;
# end-sanitize-sky
# start-sanitize-vr5400
mips64vr54*-*-*) sim_default_gen=IGEN
sim_use_gen=IGEN
sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5400"
;;
# end-sanitize-vr5400
mips64vr5*-*-*) sim_default_gen=IGEN
sim_use_gen=IGEN
sim_igen_machine="-M vr5000"
# start-sanitize-vr5400
sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5000"
# end-sanitize-vr5400
;;
mips16*-*-*) sim_default_gen=M16
;;
mips32*-*-*) sim_default_gen=IGEN
sim_igen_filter="32,f"
;;
*) sim_default_gen=IGEN
;;
esac
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine}"
AC_SUBST(sim_igen_flags)
AC_SUBST(sim_m16_flags)
#
# Enable igen
#
AC_ARG_ENABLE(sim-igen,
[ --enable-sim-igen=opts Enable IGEN simulator],
[case "${enableval}" in
yes) sim_gen="${sim_default_gen}";;
no) sim_gen=NO;;
16) sim_gen=M16;;
*) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-stdio"); sim_gen="";;
esac
if test x"$silent" != x"yes" && test x"$sim_gen" != x""; then
echo "Setting sim_igen = $sim_gen" 6>&1
fi],[sim_gen="${sim_use_gen}"])dnl
AC_SUBST(sim_gen)
AC_CHECK_HEADERS(string.h strings.h stdlib.h stdlib.h)
AC_CHECK_LIB(m, fabs)
AC_CHECK_FUNCS(aint anint sqrt)
SIM_AC_OUTPUT

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/* Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1998, Cygnus Solutions
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "sim-main.h"
#include "device.h"
void
device_error (device *me, char* message)
{
fprintf(stderr, "device_error: %s: %s", me->name, message);
}
int
device_io_read_buffer(device *me,
void *dest,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
if (me->io_read_buffer_callback == NULL)
device_error(me, "no io_read_buffer_callback method");
return me->io_read_buffer_callback(me, dest, space,
addr, nr_bytes,
processor, cia);
}
int
device_io_write_buffer(device *me,
const void *source,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
if (me->io_write_buffer_callback == NULL)
device_error(me, "no io_write_buffer_callback method");
return me->io_write_buffer_callback(me, source, space,
addr, nr_bytes,
processor, cia);
}

24
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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef DEVICE_H_
#define DEVICE_H_
#include "sim-main.h"
typedef int io_read_buffer_callback_type (device *, void *, int,
address_word, unsigned ,
sim_cpu *, sim_cia);
typedef int io_write_buffer_callback_type (device *, const void *, int,
address_word, unsigned ,
sim_cpu *, sim_cia);
struct _device {
char *name;
io_read_buffer_callback_type *io_read_buffer_callback;
io_write_buffer_callback_type *io_write_buffer_callback;
};
#endif

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/* Copyright (C) 1998, Cygnus Solutions
*/
#include "sim-main.h"
#include "device.h"
#include "dma.h"
int
dma_io_read_buffer(device *me,
void *dest,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Read!\n", me->name);
return nr_bytes;
}
static sim_event_handler do_the_dma_thing_handler;
int
dma_io_write_buffer(device *me,
const void *source,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Write!\n", me->name);
/* Do an event before the next instruction! */
sim_events_schedule (CPU_STATE(processor),
0 /*time*/,
do_the_dma_thing_handler,
CPU_STATE(processor) /*data*/);
return nr_bytes;
}
device dma_device =
{
"Dma Controller",
&dma_io_read_buffer,
&dma_io_write_buffer
};
void
dma_attach(SIM_DESC sd)
{
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
DMA_REGISTER_WINDOW_START,
DMA_REGISTER_WINDOW_SIZE /*nr_bytes*/,
0 /*modulo*/,
&dma_device,
NULL /*buffer*/);
}
static void
do_the_dma_thing_handler(SIM_DESC sd, void *data)
{
printf("Dma Event!!!\n");
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef DMA_H_
#define DMA_H_
#include "sim-main.h"
void dma_attach(SIM_DESC sd);
#define DMA_REGISTER_WINDOW_START 0x10001000
#define DMA_D0_CHCR_ADDR 0x10001000
#define DMA_D0_MADR_ADDR 0x10001010
#define DMA_D0_QWC_ADDR 0x10001020
#define DMA_D0_TADR_ADDR 0x10001030
#define DMA_D0_ASR0_ADDR 0x10001040
#define DMA_D0_ASR1_ADDR 0x10001050
#define DMA_D1_CHCR_ADDR 0x10001100
#define DMA_D1_MADR_ADDR 0x10001110
#define DMA_D1_QWC_ADDR 0x10001120
#define DMA_D1_TADR_ADDR 0x10001130
#define DMA_D1_ASR0_ADDR 0x10001140
#define DMA_D1_ASR1_ADDR 0x10001150
#define DMA_D2_CHCR_ADDR 0x10001200
#define DMA_D2_MADR_ADDR 0x10001210
#define DMA_D2_QWC_ADDR 0x10001220
#define DMA_D2_TADR_ADDR 0x10001230
#define DMA_D2_ASR0_ADDR 0x10001240
#define DMA_D2_ASR1_ADDR 0x10001250
#define DMA_D_CTRL 0x10001c00
#define DMA_D_STAT 0x10001c10
#define DMA_D_PCR 0x10001c20
#define DMA_D_SQWC 0x10001c30
#define DMA_D_RBSR 0x10001c40
#define DMA_D_RBOR 0x10001c50
#define DMA_D_STADR 0x10001c60
#define DMA_REGISTER_WINDOW_END 0x10001c70
#define DMA_REGISTER_WINDOW_SIZE (DMA_REGISTER_WINDOW_END - DMA_REGISTER_WINDOW_START)
#endif

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/* Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1998, Cygnus Solutions
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ENGINE_C_
#define _ENGINE_C_
#include "sim-inline.c"
#include "sim-main.h"
#include "itable.h"
#include "idecode.h"
#include "semantics.h"
#include "icache.h"
#include "engine.h"
#include "support.h"
#include "sim-assert.h"
enum {
/* greater or equal to zero => table */
function_entry = -1,
boolean_entry = -2,
};
typedef struct _idecode_table_entry {
int shift;
unsigned32 mask;
unsigned32 value;
void *function_or_table;
} idecode_table_entry;
INLINE_ENGINE\
(void) engine_run
(SIM_DESC sd,
int next_cpu_nr,
int siggnal)
{
sim_cpu *processor = NULL;
instruction_address cia;
int current_cpu = next_cpu_nr;
/* Hard coded main loop. Not pretty, but should work. */
SIM_ASSERT (current_cpu == 0);
processor = STATE_CPU (sd, current_cpu);
cia = CPU_CIA (processor);
while (1)
{
instruction_address nia;
instruction_word instruction_0 = IMEM (cia);
#if defined (ENGINE_ISSUE_PREFIX_HOOK)
ENGINE_ISSUE_PREFIX_HOOK();
#endif
nia = idecode_issue(sd, instruction_0, cia);
#if defined (ENGINE_ISSUE_POSTFIX_HOOK)
ENGINE_ISSUE_POSTFIX_HOOK();
#endif
/* Update the instruction address */
cia = nia;
/* process any events */
if (sim_events_tick (sd))
{
CPU_CIA (processor) = cia;
sim_events_process (sd);
}
}
}
#endif /* _ENGINE_C_*/

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/* Copyright (C) 1998, Cygnus Solutions
*/
#include "sim-main.h"
#include "device.h"
#include "gpuif.h"
int
gpuif_io_read_buffer(device *me,
void *dest,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Read!\n", me->name);
return nr_bytes;
}
int
gpuif_io_write_buffer(device *me,
const void *source,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Write!\n", me->name);
return nr_bytes;
}
device gpuif_device =
{
"Gpuif deivce",
&gpuif_io_read_buffer,
&gpuif_io_write_buffer
};
void
gpuif_attach(SIM_DESC sd)
{
sim_core_attach (sd, NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
GPUIF_REGISTER_WINDOW_START,
GPUIF_REGISTER_WINDOW_SIZE /*nr_bytes*/,
0 /*modulo*/,
&gpuif_device,
NULL /*buffer*/);
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef GPUIF_H_
#define GPUIF_H_
#include "sim-main.h"
void gpuif_attach(SIM_DESC sd);
#define GPUIF_REGISTER_WINDOW_START 0x10000700
#define GPUIF_CTRL_ADDR 0x10000700
#define GPUIF_REGISTER_WINDOW_END 0x10000790
#define GPUIF_REGISTER_WINDOW_SIZE (GPUIF_REGISTER_WINDOW_END - GPUIF_REGISTER_WINDOW_START)
#endif

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/* Copyright (C) 1998, Cygnus Solutions
*/
#include "gpuif.h"
#include "dma.h"
#include "pke0.h"
#include "pke1.h"
#include "vu0.h"
#include "vu1.h"
#include "hardware.h"
void
register_devices(SIM_DESC sd)
{
/* Attach a bunch of devices... */
gpuif_attach(sd);
dma_attach(sd);
pke0_attach(sd);
vu0_attach(sd);
vu1_attach(sd);
pke1_attach(sd);
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef _HARDWARE_H_
#define _HARDWARE_H_
#include "sim-main.h"
void create_devices(SIM_DESC sd);
#endif

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# most instructions
# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ...
# { : mask : value : word }
# Top level - create a very big switch statement.
padded-switch,combine : 31 : 26 : : : : : :
switch,combine : 5 : 0 : : : : : :
switch,combine : 20 : 16 : : : : : :
switch,combine : 25 : 21 : : : : : :
switch,combine : 10 : 6 : : : : : :

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/* Copyright (C) 1998, Cygnus Solutions
*/
#include "sim-main.h"
#include "device.h"
#include "pke0.h"
int
pke0_io_read_buffer(device *me,
void *dest,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Read!\n", me->name);
return nr_bytes;
}
int
pke0_io_write_buffer(device *me,
const void *source,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Write!\n", me->name);
return nr_bytes;
}
device pke0_device =
{
"pke0",
&pke0_io_read_buffer,
&pke0_io_write_buffer
};
void
pke0_attach(SIM_DESC sd)
{
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
PKE0_REGISTER_WINDOW_START,
PKE0_REGISTER_WINDOW_SIZE /*nr_bytes*/,
0 /*modulo*/,
&pke0_device,
NULL /*buffer*/);
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef PKE0_H_
#define PKE0_H_
#include "sim-main.h"
void pke0_attach(SIM_DESC sd);
#define PKE0_REGISTER_WINDOW_START 0x10000800
#define PKE0_REGISTER_WINDOW_END 0x10000980
#define PKE0_REGISTER_WINDOW_SIZE (PKE0_REGISTER_WINDOW_END - PKE0_REGISTER_WINDOW_START)
#endif

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/* Copyright (C) 1998, Cygnus Solutions
*/
#include "sim-main.h"
#include "device.h"
#include "pke1.h"
int
pke1_io_read_buffer(device *me,
void *dest,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Read!\n", me->name);
return nr_bytes;
}
int
pke1_io_write_buffer(device *me,
const void *source,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Write!\n", me->name);
return nr_bytes;
}
device pke1_device =
{
"pke1",
&pke1_io_read_buffer,
&pke1_io_write_buffer
};
void
pke1_attach(SIM_DESC sd)
{
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
PKE1_REGISTER_WINDOW_START,
PKE1_REGISTER_WINDOW_SIZE /*nr_bytes*/,
0 /*modulo*/,
&pke1_device,
NULL /*buffer*/);
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef PKE1_H_
#define PKE1_H_
#include "sim-main.h"
void pke1_attach(SIM_DESC sd);
#define PKE1_REGISTER_WINDOW_START 0x10000a00
#define PKE1_REGISTER_WINDOW_END 0x10000b80
#define PKE1_REGISTER_WINDOW_SIZE (PKE1_REGISTER_WINDOW_END - PKE1_REGISTER_WINDOW_START)
#endif

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/* MIPS Simulator definition.
Copyright (C) 1997 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
/* This simulator doesn't cache the Current Instruction Address */
/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
#define SIM_HAVE_BIENDIAN
/* hobble some common features for moment */
#define WITH_WATCHPOINTS 1
#define WITH_MODULO_MEMORY 1
/* For device support. FIXME: revisit. */
#define WITH_DEVICES 1
#include "sim-basics.h"
typedef address_word sim_cia;
#if (WITH_IGEN)
/* Get the number of instructions. FIXME: must be a more elegant way
of doing this. */
#include "itable.h"
#define MAX_INSNS (nr_itable_entries)
#define INSN_NAME(i) itable[(i)].name
#endif
#include "sim-base.h"
/* Depreciated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
typedef signed64 word64;
typedef unsigned64 uword64;
#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
#define SET64HI(t) (((uword64)(t))<<32)
#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
/* Sign-extend the given value (e) as a value (b) bits long. We cannot
assume the HI32bits of the operand are zero, so we must perform a
mask to ensure we can use the simple subtraction to sign-extend. */
#define SIGNEXTEND(e,b) \
((unsigned_word) \
(((e) & ((uword64) 1 << ((b) - 1))) \
? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
: ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
/* Check if a value will fit within a halfword: */
#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
/* Floating-point operations: */
#include "sim-fpu.h"
/* FPU registers must be one of the following types. All other values
are reserved (and undefined). */
typedef enum {
fmt_single = 0,
fmt_double = 1,
fmt_word = 4,
fmt_long = 5,
/* The following are well outside the normal acceptable format
range, and are used in the register status vector. */
fmt_unknown = 0x10000000,
fmt_uninterpreted = 0x20000000,
fmt_uninterpreted_32 = 0x40000000,
fmt_uninterpreted_64 = 0x80000000,
} FP_formats;
unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
#define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
#define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
int NaN PARAMS ((unsigned64 op, FP_formats fmt));
int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
#define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
/* Macro to update FPSR condition-code field. This is complicated by
the fact that there is a hole in the index range of the bits within
the FCSR register. Also, the number of bits visible depends on the
MIPS ISA version being supported. */
#define SETFCC(cc,v) {\
int bit = ((cc == 0) ? 23 : (24 + (cc)));\
FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
}
#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
/* This should be the COC1 value at the start of the preceding
instruction: */
#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
#if 1
#define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
#else
/* They depend on the CPU being simulated */
#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
#endif
/* Standard FCRS bits: */
#define IR (0) /* Inexact Result */
#define UF (1) /* UnderFlow */
#define OF (2) /* OverFlow */
#define DZ (3) /* Division by Zero */
#define IO (4) /* Invalid Operation */
#define UO (5) /* Unimplemented Operation */
/* Get masks for individual flags: */
#if 1 /* SAFE version */
#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
#else
#define FP_FLAGS(b) (1 << ((b) + 2))
#define FP_ENABLE(b) (1 << ((b) + 7))
#define FP_CAUSE(b) (1 << ((b) + 12))
#endif
#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
#define FP_MASK_RM (0x3)
#define FP_SH_RM (0)
#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
/* Integer ALU operations: */
#include "sim-alu.h"
#define ALU32_END(ANS) \
if (ALU32_HAD_OVERFLOW) \
SignalExceptionIntegerOverflow (); \
(ANS) = ALU32_OVERFLOW_RESULT
#define ALU64_END(ANS) \
if (ALU64_HAD_OVERFLOW) \
SignalExceptionIntegerOverflow (); \
(ANS) = ALU64_OVERFLOW_RESULT;
/* start-sanitize-r5900 */
#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
T - type of the sub part
TC - # of T's in the mips part of the "register"
I - index (from 0) of desired sub part
A - low part of "register"
A1 - high part of register
*/
#define SUB_REG_FETCH(T,TC,A,A1,I) \
(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
+ (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
? ((TC) - 1 - (I) % (TC)) \
: ((I) % (TC)) \
) \
) \
)
/*
GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
where <type> has two letters:
1 is S=signed or U=unsigned
2 is B=byte H=halfword W=word D=doubleword
*/
#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
#define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
#define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
#define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
#define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
#define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
#define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
#define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
#define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
/* end-sanitize-r5900 */
struct _sim_cpu {
/* The following are internal simulator state variables: */
#define CPU_CIA(CPU) (PC)
address_word dspc; /* delay-slot PC */
#define DSPC ((STATE_CPU (sd,0))->dspc)
/* Issue a delay slot instruction immediatly by re-calling
idecode_issue */
#define DELAY_SLOT(TARGET) \
do { \
address_word target = (TARGET); \
instruction_word delay_insn; \
sim_events_slip (sd, 1); \
CIA = CIA + 4; \
STATE |= simDELAYSLOT; \
delay_insn = IMEM (CIA); \
idecode_issue (sd, delay_insn, (CIA)); \
STATE &= ~simDELAYSLOT; \
NIA = target; \
} while (0)
#define NULLIFY_NEXT_INSTRUCTION() \
do { \
sim_events_slip (sd, 1); \
dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
NIA = CIA + 8; \
} while (0)
/* State of the simulator */
unsigned int state;
unsigned int dsstate;
#define STATE ((STATE_CPU (sd,0))->state)
#define DSSTATE ((STATE_CPU (sd,0))->dsstate)
/* Flags in the "state" variable: */
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
#define simPCOC0 (1 << 17) /* COC[1] from current */
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#define ENGINE_ISSUE_PREFIX_HOOK() \
{ \
/* Set previous flag, depending on current: */ \
if (STATE & simPCOC0) \
STATE |= simPCOC1; \
else \
STATE &= ~simPCOC1; \
/* and update the current value: */ \
if (GETFCC(0)) \
STATE |= simPCOC0; \
else \
STATE &= ~simPCOC0; \
}
/* This is nasty, since we have to rely on matching the register
numbers used by GDB. Unfortunately, depending on the MIPS target
GDB uses different register numbers. We cannot just include the
relevant "gdb/tm.h" link, since GDB may not be configured before
the sim world, and also the GDB header file requires too much other
state. */
#ifndef TM_MIPS_H
#define LAST_EMBED_REGNUM (89)
#define NUM_REGS (LAST_EMBED_REGNUM + 1)
/* start-sanitize-r5900 */
#undef NUM_REGS
#define NUM_REGS (128)
/* end-sanitize-r5900 */
#endif
/* To keep this default simulator simple, and fast, we use a direct
vector of registers. The internal simulator engine then uses
manifests to access the correct slot. */
unsigned_word registers[LAST_EMBED_REGNUM + 1];
int register_widths[NUM_REGS];
#define REGISTERS ((STATE_CPU (sd,0))->registers)
#define GPR (&REGISTERS[0])
#define FGRIDX (38)
#define FGR (&REGISTERS[FGRIDX])
#define LO (REGISTERS[33])
#define HI (REGISTERS[34])
#define PC (REGISTERS[37])
#define CAUSE (REGISTERS[36])
#define SRIDX (32)
#define SR (REGISTERS[SRIDX]) /* CPU status register */
#define FCR0IDX (71)
#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
#define FCR31IDX (70)
#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
#define FCSR (FCR31)
#define Debug (REGISTERS[86])
#define DEPC (REGISTERS[87])
#define EPC (REGISTERS[88])
#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
unsigned_word c0_config_reg;
#define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
/* The following are pseudonyms for standard registers */
#define ZERO (REGISTERS[0])
#define V0 (REGISTERS[2])
#define A0 (REGISTERS[4])
#define A1 (REGISTERS[5])
#define A2 (REGISTERS[6])
#define A3 (REGISTERS[7])
#define SP (REGISTERS[29])
#define RA (REGISTERS[31])
/* Keep the current format state for each register: */
FP_formats fpr_state[32];
#define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
/* Slots for delayed register updates. For the moment we just have a
fixed number of slots (rather than a more generic, dynamic
system). This keeps the simulator fast. However, we only allow
for the register update to be delayed for a single instruction
cycle. */
#define PSLOTS (5) /* Maximum number of instruction cycles */
int pending_in;
int pending_out;
int pending_total;
int pending_slot_count[PSLOTS];
int pending_slot_reg[PSLOTS];
unsigned_word pending_slot_value[PSLOTS];
#define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
#define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
#define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
#define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
#define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
#define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
#if 0
/* The following are not used for MIPS IV onwards: */
#define PENDING_FILL(r,v) {\
/* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
PENDING_SLOT_COUNT[PENDING_IN] = 2;\
PENDING_SLOT_REG[PENDING_IN] = (r);\
PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
/*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
PENDING_TOTAL++;\
PENDING_IN++;\
if (PENDING_IN == PSLOTS)\
PENDING_IN = 0;\
/*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
}
#endif
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
read-write instructions. It is set when a linked load occurs. It
is tested and cleared by the conditional store. It is cleared
(during other CPU operations) when a store to the location would
no longer be atomic. In particular, it is cleared by exception
return instructions. */
int llbit;
#define LLBIT ((STATE_CPU (sd, 0))->llbit)
/* The HIACCESS and LOACCESS counts are used to ensure that
corruptions caused by using the HI or LO register to close to a
following operation are spotted. */
int hiaccess;
int loaccess;
#define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
#define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
/* start-sanitize-r5900 */
int hi1access;
int lo1access;
#define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
#define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
/* end-sanitize-r5900 */
#if 1
/* The 4300 and a few other processors have interlocks on hi/lo
register reads, and hence do not have this problem. To avoid
spurious warnings, we just disable this always. */
#define CHECKHILO(s)
#else
unsigned_word HLPC;
/* If either of the preceding two instructions have accessed the HI
or LO registers, then the values they see should be
undefined. However, to keep the simulator world simple, we just
let them use the value read and raise a warning to notify the
user: */
#define CHECKHILO(s) {\
if ((HIACCESS != 0) || (LOACCESS != 0)) \
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
}
/* start-sanitize-r5900 */
#undef CHECKHILO
#define CHECKHILO(s) {\
if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
}
/* end-sanitize-r5900 */
#endif
/* start-sanitize-r5900 */
/* The R5900 has 128 bit registers, but the hi 64 bits are only
touched by multimedia (MMI) instructions. The normal mips
instructions just use the lower 64 bits. To avoid changing the
older parts of the simulator to handle this weirdness, the high
64 bits of each register are kept in a separate array
(registers1). The high 64 bits of any register are by convention
refered by adding a '1' to the end of the normal register's name.
So LO still refers to the low 64 bits of the LO register, LO1
refers to the high 64 bits of that same register. */
signed_word registers1[LAST_EMBED_REGNUM + 1];
#define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
#define GPR1 (&REGISTERS1[0])
#define LO1 (REGISTERS1[32])
#define HI1 (REGISTERS1[33])
#define REGISTER_SA (124)
unsigned_word sa; /* the shift amount register */
#define SA ((STATE_CPU (sd, 0))->sa)
/* end-sanitize-r5900 */
/* start-sanitize-vr5400 */
/* The MDMX ISA has a very very large accumulator */
unsigned8 acc[3 * 8];
/* end-sanitize-vr5400 */
sim_cpu_base base;
};
/* MIPS specific simulator watch config */
void watch_options_install PARAMS ((SIM_DESC sd));
struct swatch {
sim_event *pc;
sim_event *clock;
sim_event *cycles;
};
/* FIXME: At present much of the simulator is still static */
struct sim_state {
struct swatch watch;
sim_cpu cpu[1];
#if (WITH_SMP)
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
#else
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
#endif
sim_state_base base;
};
/* Status information: */
/* TODO : these should be the bitmasks for these bits within the
status register. At the moment the following are VR4300
bit-positions: */
#define status_KSU_mask (0x3) /* mask for KSU bits */
#define status_KSU_shift (3) /* shift for field */
#define ksu_kernel (0x0)
#define ksu_supervisor (0x1)
#define ksu_user (0x2)
#define ksu_unknown (0x3)
#define status_IE (1 << 0) /* Interrupt enable */
#define status_EXL (1 << 1) /* Exception level */
#define status_RE (1 << 25) /* Reverse Endian in user mode */
#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
#define status_SR (1 << 20) /* soft reset or NMI */
#define status_BEV (1 << 22) /* Location of general exception vectors */
#define status_TS (1 << 21) /* TLB shutdown has occurred */
#define status_ERL (1 << 2) /* Error level */
#define status_RP (1 << 27) /* Reduced Power mode */
#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
/* NOTE: We keep the following status flags as bit values (1 for true,
0 for false). This allows them to be used in binary boolean
operations without worrying about what exactly the non-zero true
value is. */
/* UserMode */
#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
/* BigEndianMem */
/* Hardware configuration. Affects endianness of LoadMemory and
StoreMemory and the endianness of Kernel and Supervisor mode
execution. The value is 0 for little-endian; 1 for big-endian. */
#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
/*(state & simBE) ? 1 : 0)*/
/* ReverseEndian */
/* This mode is selected if in User mode with the RE bit being set in
SR (Status Register). It reverses the endianness of load and store
instructions. */
#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
/* BigEndianCPU */
/* The endianness for load and store instructions (0=little;1=big). In
User mode this endianness may be switched by setting the state_RE
bit in the SR register. Thus, BigEndianCPU may be computed as
(BigEndianMem EOR ReverseEndian). */
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
/* Exceptions: */
/* NOTE: These numbers depend on the processor architecture being
simulated: */
#define Interrupt (0)
#define TLBModification (1)
#define TLBLoad (2)
#define TLBStore (3)
#define AddressLoad (4)
#define AddressStore (5)
#define InstructionFetch (6)
#define DataReference (7)
#define SystemCall (8)
#define BreakPoint (9)
#define ReservedInstruction (10)
#define CoProcessorUnusable (11)
#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
#define Trap (13)
#define FPE (15)
#define DebugBreakPoint (16)
#define Watch (23)
/* The following exception code is actually private to the simulator
world. It is *NOT* a processor feature, and is used to signal
run-time errors in the simulator. */
#define SimulatorFault (0xFFFFFFFF)
void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
#define SignalException(exc,instruction) signal_exception (sd, cia, (exc), (instruction))
#define SignalExceptionInterrupt() signal_exception (sd, NULL_CIA, Interrupt)
#define SignalExceptionInstructionFetch() signal_exception (sd, cia, InstructionFetch)
#define SignalExceptionAddressStore() signal_exception (sd, cia, AddressStore)
#define SignalExceptionAddressLoad() signal_exception (sd, cia, AddressLoad)
#define SignalExceptionSimulatorFault(buf) signal_exception (sd, cia, SimulatorFault, buf)
#define SignalExceptionFPE() signal_exception (sd, cia, FPE)
#define SignalExceptionIntegerOverflow() signal_exception (sd, cia, IntegerOverflow)
#define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
/* Co-processor accesses */
void cop_lw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
void cop_ld PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
#define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
#define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
#define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
/* Memory accesses */
/* The following are generic to all versions of the MIPS architecture
to date: */
/* Memory Access Types (for CCA): */
#define Uncached (0)
#define CachedNoncoherent (1)
#define CachedCoherent (2)
#define Cached (3)
#define isINSTRUCTION (1 == 0) /* FALSE */
#define isDATA (1 == 1) /* TRUE */
#define isLOAD (1 == 0) /* FALSE */
#define isSTORE (1 == 1) /* TRUE */
#define isREAL (1 == 0) /* FALSE */
#define isRAW (1 == 1) /* TRUE */
/* The parameter HOST (isTARGET / isHOST) is ignored */
#define isTARGET (1 == 0) /* FALSE */
/* #define isHOST (1 == 1) TRUE */
/* The "AccessLength" specifications for Loads and Stores. NOTE: This
is the number of bytes minus 1. */
#define AccessLength_BYTE (0)
#define AccessLength_HALFWORD (1)
#define AccessLength_TRIPLEBYTE (2)
#define AccessLength_WORD (3)
#define AccessLength_QUINTIBYTE (4)
#define AccessLength_SEXTIBYTE (5)
#define AccessLength_SEPTIBYTE (6)
#define AccessLength_DOUBLEWORD (7)
#define AccessLength_QUADWORD (15)
int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
#define SyncOperation(stype) sync_operation (sd, cia, (stype))
void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
#define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
FILE *tracefh;
#endif

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sim/txvu/tconfig.in Normal file
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/* mips target configuration file. */
/* Define this if the simulator supports profiling.
See the mips simulator for an example.
This enables the `-p foo' and `-s bar' options.
The target is required to provide sim_set_profile{,_size}. */
#define SIM_HAVE_PROFILE
/* Define this if the simulator uses an instruction cache.
See the h8/300 simulator for an example.
This enables the `-c size' option to set the size of the cache.
The target is required to provide sim_set_simcache_size. */
/* #define SIM_HAVE_SIMCACHE */
/* Define this if the target cpu is bi-endian
and the simulator supports it. */
#define SIM_HAVE_BIENDIAN

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sim/txvu/vr5400.igen Normal file
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// Integer Instructions
// --------------------
//
// MulAcc is the Multiply Accumulator.
// This register is mapped on the the HI and LO registers.
// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
:function:::unsigned64:MulAcc:
{
unsigned64 result = U8_4 (HI, LO);
return result;
}
:function:::void:SET_MulAcc:unsigned64 value
{
*AL4_8 (&HI) = VH4_8 (value);
*AL4_8 (&LO) = VL4_8 (value);
}
:function:::signed64:SignedMultiply:signed32 l, signed32 r
{
signed64 result = (signed64) l * (signed64) r;
return result;
}
:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
{
unsigned64 result = (unsigned64) l * (unsigned64) r;
return result;
}
:function:::unsigned64:Low32Bits:unsigned64 value
{
unsigned64 result = (signed64) (signed32) VL4_8 (value);
return result;
}
:function:::unsigned64:High32Bits:unsigned64 value
{
unsigned64 result = (signed64) (signed32) VH4_8 (value);
return result;
}
// Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00001,011000::::MUL
"mul r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00001,011001::::MULU
"mulu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
"mulhi r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
"mulhiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Multiply, Negate and Move LO.
000000,5.RS,5.RT,5.RD,00011,011000::::MULS
"muls r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply, Negate and Move LO.
000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
"mulsu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Multiply, Negate and Move HI.
000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
"mulshi r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply, Negate and Move HI.
000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
"mulshiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Multiply, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00101,011000::::MACC
"macc r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
"maccu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Multiply, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
"macchi r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
"macchiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Multiply, Negate, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
"msac r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply, Negate, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
"msacu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Multiply, Negate, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
"msachi r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply, Negate, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
"msachiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Rotate Right.
000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
"ror r<RD>, r<RT>, <SHIFT>"
*vr5400:
{
int s = SHIFT;
GPR[RD] = ROTR32 (GPR[RT], s);
}
// Rotate Right Variable.
000000,5.RS,5.RT,5.RD,00001,000110::::RORV
"rorv r<RD>, r<RT>, <RS>"
*vr5400:
{
int s = MASKED (GPR[RS], 4, 0);
GPR[RD] = ROTR32 (GPR[RT], s);
}
// Double Rotate Right.
000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
"dror r<RD>, r<RT>, <SHIFT>"
*vr5400:
{
int s = SHIFT;
GPR[RD] = ROTR64 (GPR[RT], s);
}
// Double Rotate Right Plus 32.
000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
"dror32 r<RD>, r<RT>, <SHIFT>"
*vr5400:
{
int s = SHIFT + 32;
GPR[RD] = ROTR64 (GPR[RT], s);
}
// Double Rotate Right Variable.
000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
"drorv r<RD>, r<RT>, <RS>"
*vr5400:
{
int s = MASKED (GPR[RS], 5, 0);
GPR[RD] = ROTR64 (GPR[RT], s);
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#include "sim-main.h"
#include "device.h"
#include "vu0.h"
static char vu0_mem0_buffer[VU0_MEM0_SIZE];
static char vu0_mem1_buffer[VU0_MEM1_SIZE];
int
vu0_io_read_buffer(device *me,
void *dest,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Read!\n", me->name);
return nr_bytes;
}
int
vu0_io_write_buffer(device *me,
const void *source,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Write!\n", me->name);
return nr_bytes;
}
device vu0_device =
{
"vu0",
&vu0_io_read_buffer,
&vu0_io_write_buffer
};
void
vu0_attach(SIM_DESC sd)
{
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
VU0_REGISTER_WINDOW_START,
VU0_REGISTER_WINDOW_SIZE /*nr_bytes*/,
0 /*modulo*/,
&vu0_device,
NULL /*buffer*/);
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
VU0_MEM0_WINDOW_START,
VU0_MEM0_SIZE /*nr_bytes*/,
0 /*modulo*/,
0 /*device*/,
&vu0_mem0_buffer /*buffer*/);
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
VU0_MEM1_WINDOW_START,
VU0_MEM1_SIZE /*nr_bytes*/,
0 /*modulo*/,
0 /*device*/,
&vu0_mem1_buffer /*buffer*/);
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef VU0_H_
#define VU0_H_
#include "sim-main.h"
void vu0_attach(SIM_DESC sd);
#define VU0_MEM0_WINDOW_START 0x11000000
#define VU0_MEM0_SIZE 0x1000 /* 4K = 4096 */
#define VU0_MEM1_WINDOW_START 0x11004000
#define VU0_MEM1_SIZE 0x1000 /* 4K = 4096 */
#define VU0_REGISTER_WINDOW_START 0x10000c00
#define VU0_VF00 0x10000c00
/* ... */
#define VU0_VF31 0x10000df0
#define VU0_VI00 0x10000e00
/* ... */
#define VU0_VI15 0x10000ef0
/* ... */
#define VPE0_STAT 0x10000fd0
#define VU0_REGISTER_WINDOW_END 0x10000fe0
#define VU0_REGISTER_WINDOW_SIZE (VU0_REGISTER_WINDOW_END - VU0_REGISTER_WINDOW_START)
#endif

85
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/* Copyright (C) 1998, Cygnus Solutions
*/
#include "sim-main.h"
#include "device.h"
#include "vu1.h"
static char vu1_mem0_buffer[VU1_MEM0_SIZE];
static char vu1_mem1_buffer[VU1_MEM1_SIZE];
int
vu1_io_read_buffer(device *me,
void *dest,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Read!\n", me->name);
printf(" vu1_mem0[0] = %d\n", *(int*)&vu1_mem0_buffer[0]);
printf(" vu1_mem1[0] = %d\n", *(int*)&vu1_mem1_buffer[0]);
return nr_bytes;
}
int
vu1_io_write_buffer(device *me,
const void *source,
int space,
address_word addr,
unsigned nr_bytes,
sim_cpu *processor,
sim_cia cia)
{
printf("%s: Write!\n", me->name);
return nr_bytes;
}
device vu1_device =
{
"vu1",
&vu1_io_read_buffer,
&vu1_io_write_buffer
};
void
vu1_attach(SIM_DESC sd)
{
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
VU1_REGISTER_WINDOW_START,
VU1_REGISTER_WINDOW_SIZE /*nr_bytes*/,
0 /*modulo*/,
&vu1_device,
NULL /*buffer*/);
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
VU1_MEM0_WINDOW_START,
VU1_MEM0_SIZE /*nr_bytes*/,
0 /*modulo*/,
0 /*device*/,
&vu1_mem0_buffer /*buffer*/);
sim_core_attach (sd,
NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
VU1_MEM1_WINDOW_START,
VU1_MEM1_SIZE /*nr_bytes*/,
0 /*modulo*/,
0 /*device*/,
&vu1_mem1_buffer /*buffer*/);
}

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/* Copyright (C) 1998, Cygnus Solutions
*/
#ifndef VU1_H_
#define VU1_H_
#include "sim-main.h"
void vu1_attach(SIM_DESC sd);
#define VU1_MEM0_WINDOW_START 0x11008000
#define VU1_MEM0_SIZE 0x4000 /* 16K = 16384 */
#define VU1_MEM1_WINDOW_START 0x1100c000
#define VU1_MEM1_SIZE 0x4000 /* 16K = 16384 */
#define VU1_REGISTER_WINDOW_START 0x11007000
#define VU1_VF00 0x11007000
/* ... */
#define VU1_VF31 0x110071f0
#define VU1_VI00 0x11007200
/* ... */
#define VU1_VI15 0x110072f0
/* ... */
#define VPE1_STAT 0x11007370
#define VU1_REGISTER_WINDOW_END 0x11007380
#define VU1_REGISTER_WINDOW_SIZE (VU1_REGISTER_WINDOW_END - VU1_REGISTER_WINDOW_START)
#endif