gas/
2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (set_intel_mnemonic): New. (intel_mnemonic): Likewise. (old_gcc): Likewise. (OPTION_MMNEMONIC): Likewise. (OPTION_MSYNTAX): Likewise. (OPTION_MINDEX_REG): Likewise. (OPTION_MNAKED_REG): Likewise. (OPTION_MOLD_GCC): Likewise. (md_pseudo_table): Add .intel_mnemonic and .att_mnemonic. (match_template): Don't allow AT&T/Intel mnemonic if Intel/AT&T mnemonic is specified. Don't allow old gcc support if old_gcc is 0. (md_longopts): Add -mmnemonic, -msyntax, -mindex-reg, -mmnaked-reg and -mold-gcc. (md_parse_option): Handle OPTION_MMNEMONIC, OPTION_MSYNTAX, OPTION_MINDEX_REG, OPTION_MNAKED_REG and OPTION_MOLD_GCC. * doc/c-i386.texi: Docoument -mmnemonic, -msyntax, --mnaked-reg and AT&T mnemonic vs. Intel mnemonic. gas/testsuite/ 2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/compat-intel.d: Pass -mmnemonic=att to assembler. * gas/i386/compat.d: Likewise. * gas/i386/i386.exp: Pass -mmnemonic=att to assembler for "float". Pass -mold-gcc to assembler for "general". opcodes/ 2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add OldGcc, ATTMnemonic and IntelMnemonic. * i386-opc.h (OldGcc): New. (ATTMnemonic): Likewise. (IntelMnemonic): Likewise. (Opcode_Modifier_Max): Updated. (i386_opcode_modifier): Add oldgcc, attmnemonic and intelmnemonic. * i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul, fsub, fsubp, fsubr and fsubrp with OldGcc, ATTMnemonic and IntelMnemonic. * i386-tbl.h: Regeneratd.
This commit is contained in:
parent
896c3b60e9
commit
1efbbeb461
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@ -1,3 +1,25 @@
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2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (set_intel_mnemonic): New.
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(intel_mnemonic): Likewise.
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(old_gcc): Likewise.
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(OPTION_MMNEMONIC): Likewise.
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(OPTION_MSYNTAX): Likewise.
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(OPTION_MINDEX_REG): Likewise.
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(OPTION_MNAKED_REG): Likewise.
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(OPTION_MOLD_GCC): Likewise.
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(md_pseudo_table): Add .intel_mnemonic and .att_mnemonic.
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(match_template): Don't allow AT&T/Intel mnemonic if Intel/AT&T
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mnemonic is specified. Don't allow old gcc support if old_gcc
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is 0.
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(md_longopts): Add -mmnemonic, -msyntax, -mindex-reg,
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-mmnaked-reg and -mold-gcc.
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(md_parse_option): Handle OPTION_MMNEMONIC, OPTION_MSYNTAX,
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OPTION_MINDEX_REG, OPTION_MNAKED_REG and OPTION_MOLD_GCC.
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* doc/c-i386.texi: Docoument -mmnemonic, -msyntax, --mnaked-reg
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and AT&T mnemonic vs. Intel mnemonic.
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2007-12-20 Bob Wilson <bob.wilson@acm.org>
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2007-12-20 Bob Wilson <bob.wilson@acm.org>
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* config/tc-xtensa.c (xtensa_elf_cons): Set frag flags for
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* config/tc-xtensa.c (xtensa_elf_cons): Set frag flags for
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@ -58,6 +58,7 @@
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static void set_code_flag (int);
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static void set_code_flag (int);
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static void set_16bit_gcc_code_flag (int);
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static void set_16bit_gcc_code_flag (int);
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static void set_intel_syntax (int);
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static void set_intel_syntax (int);
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static void set_intel_mnemonic (int);
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static void set_allow_index_reg (int);
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static void set_allow_index_reg (int);
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static void set_cpu_arch (int);
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static void set_cpu_arch (int);
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#ifdef TE_PE
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#ifdef TE_PE
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@ -283,6 +284,13 @@ static const char *flag_code_names[] =
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0 if att syntax. */
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0 if att syntax. */
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static int intel_syntax = 0;
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static int intel_syntax = 0;
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/* 1 for intel mnemonic,
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0 if att mnemonic. */
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static int intel_mnemonic = !SYSV386_COMPAT;
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/* 1 ti support old (<= 2.8.1) versions of gcc. */
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static int old_gcc = OLDGCC_COMPAT;
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/* 1 if register prefix % not required. */
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/* 1 if register prefix % not required. */
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static int allow_naked_reg = 0;
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static int allow_naked_reg = 0;
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@ -534,6 +542,8 @@ const pseudo_typeS md_pseudo_table[] =
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{"code64", set_code_flag, CODE_64BIT},
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{"code64", set_code_flag, CODE_64BIT},
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{"intel_syntax", set_intel_syntax, 1},
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{"intel_syntax", set_intel_syntax, 1},
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{"att_syntax", set_intel_syntax, 0},
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{"att_syntax", set_intel_syntax, 0},
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{"intel_mnemonic", set_intel_mnemonic, 1},
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{"att_mnemonic", set_intel_mnemonic, 0},
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{"allow_index_reg", set_allow_index_reg, 1},
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{"allow_index_reg", set_allow_index_reg, 1},
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{"disallow_index_reg", set_allow_index_reg, 0},
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{"disallow_index_reg", set_allow_index_reg, 0},
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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@ -1504,6 +1514,42 @@ set_intel_syntax (int syntax_flag)
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register_prefix = allow_naked_reg ? "" : "%";
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register_prefix = allow_naked_reg ? "" : "%";
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}
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}
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static void
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set_intel_mnemonic (int mnemonic_flag)
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{
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/* Find out if register prefixing is specified. */
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int ask_naked_reg = 0;
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SKIP_WHITESPACE ();
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if (!is_end_of_line[(unsigned char) *input_line_pointer])
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{
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char *string = input_line_pointer;
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int e = get_symbol_end ();
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if (strcmp (string, "prefix") == 0)
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ask_naked_reg = 1;
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else if (strcmp (string, "noprefix") == 0)
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ask_naked_reg = -1;
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else
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as_bad (_("bad argument to syntax directive."));
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*input_line_pointer = e;
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}
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demand_empty_rest_of_line ();
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/* intel_mnemonic implies intel_syntax. */
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intel_mnemonic = intel_syntax = mnemonic_flag;
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if (ask_naked_reg == 0)
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allow_naked_reg = (intel_mnemonic
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&& (bfd_get_symbol_leading_char (stdoutput) != '\0'));
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else
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allow_naked_reg = (ask_naked_reg < 0);
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identifier_chars['%'] = intel_mnemonic && allow_naked_reg ? '%' : 0;
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identifier_chars['$'] = intel_mnemonic ? '$' : 0;
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register_prefix = allow_naked_reg ? "" : "%";
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}
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static void
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static void
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set_allow_index_reg (int flag)
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set_allow_index_reg (int flag)
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{
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{
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@ -3010,6 +3056,17 @@ match_template (void)
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if (i.operands != t->operands)
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if (i.operands != t->operands)
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continue;
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continue;
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/* Check AT&T mnemonic and old gcc support. */
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if (t->opcode_modifier.attmnemonic
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&& (intel_mnemonic
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|| (!old_gcc
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&& t->opcode_modifier.oldgcc)))
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continue;
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/* Check Intel mnemonic. */
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if (!intel_mnemonic && t->opcode_modifier.intelmnemonic)
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continue;
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/* Check the suffix, except for some instructions in intel mode. */
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/* Check the suffix, except for some instructions in intel mode. */
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if ((!intel_syntax || !t->opcode_modifier.ignoresize)
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if ((!intel_syntax || !t->opcode_modifier.ignoresize)
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&& ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
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&& ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
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@ -6911,6 +6968,11 @@ const char *md_shortopts = "qn";
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#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
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#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
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#define OPTION_MARCH (OPTION_MD_BASE + 3)
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#define OPTION_MARCH (OPTION_MD_BASE + 3)
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#define OPTION_MTUNE (OPTION_MD_BASE + 4)
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#define OPTION_MTUNE (OPTION_MD_BASE + 4)
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#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
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#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
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#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
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#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
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#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
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struct option md_longopts[] =
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struct option md_longopts[] =
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{
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{
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@ -6921,6 +6983,11 @@ struct option md_longopts[] =
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{"divide", no_argument, NULL, OPTION_DIVIDE},
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{"divide", no_argument, NULL, OPTION_DIVIDE},
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{"march", required_argument, NULL, OPTION_MARCH},
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{"march", required_argument, NULL, OPTION_MARCH},
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{"mtune", required_argument, NULL, OPTION_MTUNE},
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{"mtune", required_argument, NULL, OPTION_MTUNE},
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{"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
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{"msyntax", required_argument, NULL, OPTION_MSYNTAX},
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{"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
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{"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
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{"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
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{NULL, no_argument, NULL, 0}
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{NULL, no_argument, NULL, 0}
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};
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};
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size_t md_longopts_size = sizeof (md_longopts);
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size_t md_longopts_size = sizeof (md_longopts);
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@ -7041,6 +7108,37 @@ md_parse_option (int c, char *arg)
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as_fatal (_("Invalid -mtune= option: `%s'"), arg);
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as_fatal (_("Invalid -mtune= option: `%s'"), arg);
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break;
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break;
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case OPTION_MMNEMONIC:
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if (strcasecmp (arg, "att") == 0)
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intel_mnemonic = 0;
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else if (strcasecmp (arg, "intel") == 0)
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intel_mnemonic = 1;
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else
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as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
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break;
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case OPTION_MSYNTAX:
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if (strcasecmp (arg, "att") == 0)
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intel_syntax = 0;
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else if (strcasecmp (arg, "intel") == 0)
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intel_syntax = 1;
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else
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as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
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break;
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case OPTION_MINDEX_REG:
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allow_index_reg = 1;
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break;
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case OPTION_MNAKED_REG:
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allow_naked_reg = 1;
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break;
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case OPTION_MOLD_GCC:
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old_gcc = 1;
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intel_mnemonic = 0;
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break;
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default:
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default:
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return 0;
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return 0;
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}
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}
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@ -119,6 +119,29 @@ generated.
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Valid @var{CPU} values are identical to @option{-march=@var{CPU}}.
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Valid @var{CPU} values are identical to @option{-march=@var{CPU}}.
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@cindex @samp{-mmnemonic=} option, i386
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@cindex @samp{-mmnemonic=} option, x86-64
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@item -mmnemonic=@var{att}
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@item -mmnemonic=@var{intel}
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This option specifies instruction mnemonic for matching instructions.
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The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
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take precedent.
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@cindex @samp{-msyntax=} option, i386
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@cindex @samp{-msyntax=} option, x86-64
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@item -msyntax=@var{att}
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@item -msyntax=@var{intel}
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This option specifies instruction syntax when processing instructions.
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The @code{.att_syntax} and @code{.intel_syntax} directives will
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take precedent.
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@cindex @samp{-mnaked-reg} option, i386
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@cindex @samp{-mnaked-reg} option, x86-64
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@item -mnaked-reg
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This opetion specifies that registers don't require a @samp{%} prefix.
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The @code{.att_mnemonic}, @code{.intel_mnemonic}, @code{.att_syntax} and
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@code{.intel_syntax} directives will take precedent.
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@end table
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@end table
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@node i386-Syntax
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@node i386-Syntax
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@ -297,6 +320,23 @@ Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
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AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
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AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
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convention.
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convention.
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@section AT&T Mnemonic versus Intel Mnemonic
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@cindex i386 mnemonic compatibility
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@cindex mnemonic compatibility, i386
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@code{@value{AS}} supports assembly using Intel mnemonic.
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@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
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@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
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syntax for compatibility with the output of @code{@value{GCC}}.
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Either of these directives may have an optional argument, @code{prefix},
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or @code{noprefix} specifying whether registers require a @samp{%} prefix.
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Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
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@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
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@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
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assembler with different mnemonics from those in Intel IA32 specification.
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@code{@value{GCC}} generates those instructions with AT&T mnemonic.
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@node i386-Regs
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@node i386-Regs
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@section Register Naming
|
@section Register Naming
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|
@ -1,3 +1,11 @@
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|
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
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|
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* gas/i386/compat-intel.d: Pass -mmnemonic=att to assembler.
|
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|
* gas/i386/compat.d: Likewise.
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|
* gas/i386/i386.exp: Pass -mmnemonic=att to assembler for
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|
"float". Pass -mold-gcc to assembler for "general".
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|
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2007-12-22 H.J. Lu <hongjiu.lu@intel.com>
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2007-12-22 H.J. Lu <hongjiu.lu@intel.com>
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|
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* gas/i386/compat-intel.d: New file.
|
* gas/i386/compat-intel.d: New file.
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|
|
|
@ -1,3 +1,4 @@
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|
#as: -mmnemonic=att
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#objdump: -d -Mintel-mnemonic
|
#objdump: -d -Mintel-mnemonic
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#name: i386 float Intel mnemonic
|
#name: i386 float Intel mnemonic
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#source: compat.s
|
#source: compat.s
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|
|
|
@ -1,3 +1,4 @@
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|
#as: -mmnemonic=att
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#objdump: -d -Matt-mnemonic
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#objdump: -d -Matt-mnemonic
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#name: i386 float AT&T mnemonic
|
#name: i386 float AT&T mnemonic
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|
|
||||||
|
|
|
@ -23,8 +23,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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set old_ASFLAGS "$ASFLAGS"
|
set old_ASFLAGS "$ASFLAGS"
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set ASFLAGS "$ASFLAGS --32"
|
set ASFLAGS "$ASFLAGS --32"
|
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|
|
||||||
run_list_test "float" "-al"
|
run_list_test "float" "-al -mmnemonic=att"
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run_list_test "general" "-al --listing-lhs-width=2"
|
run_list_test "general" "-al --listing-lhs-width=2 -mold-gcc"
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run_list_test "inval" "-al"
|
run_list_test "inval" "-al"
|
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run_list_test "segment" "-al"
|
run_list_test "segment" "-al"
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run_list_test "inval-seg" "-al"
|
run_list_test "inval-seg" "-al"
|
||||||
|
|
|
@ -1,3 +1,20 @@
|
||||||
|
2007-12-23 H.J. Lu <hongjiu.lu@intel.com>
|
||||||
|
|
||||||
|
* i386-gen.c (opcode_modifiers): Add OldGcc, ATTMnemonic and
|
||||||
|
IntelMnemonic.
|
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|
|
||||||
|
* i386-opc.h (OldGcc): New.
|
||||||
|
(ATTMnemonic): Likewise.
|
||||||
|
(IntelMnemonic): Likewise.
|
||||||
|
(Opcode_Modifier_Max): Updated.
|
||||||
|
(i386_opcode_modifier): Add oldgcc, attmnemonic and
|
||||||
|
intelmnemonic.
|
||||||
|
|
||||||
|
* i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul,
|
||||||
|
fsub, fsubp, fsubr and fsubrp with OldGcc, ATTMnemonic and
|
||||||
|
IntelMnemonic.
|
||||||
|
* i386-tbl.h: Regeneratd.
|
||||||
|
|
||||||
2007-12-22 H.J. Lu <hongjiu.lu@intel.com>
|
2007-12-22 H.J. Lu <hongjiu.lu@intel.com>
|
||||||
|
|
||||||
* i386-dis.c (intel_mnemonic): New.
|
* i386-dis.c (intel_mnemonic): New.
|
||||||
|
|
|
@ -289,6 +289,9 @@ static bitfield opcode_modifiers[] =
|
||||||
BITFIELD (Drex),
|
BITFIELD (Drex),
|
||||||
BITFIELD (Drexv),
|
BITFIELD (Drexv),
|
||||||
BITFIELD (Drexc),
|
BITFIELD (Drexc),
|
||||||
|
BITFIELD (OldGcc),
|
||||||
|
BITFIELD (ATTMnemonic),
|
||||||
|
BITFIELD (IntelMnemonic),
|
||||||
};
|
};
|
||||||
|
|
||||||
static bitfield operand_types[] =
|
static bitfield operand_types[] =
|
||||||
|
|
|
@ -220,8 +220,14 @@ typedef union i386_cpu_flags
|
||||||
#define Drexv (Drex + 1)
|
#define Drexv (Drex + 1)
|
||||||
/* special DREX for comparisons */
|
/* special DREX for comparisons */
|
||||||
#define Drexc (Drexv + 1)
|
#define Drexc (Drexv + 1)
|
||||||
|
/* Compatible with old (<= 2.8.1) versions of gcc */
|
||||||
|
#define OldGcc (Drexc + 1)
|
||||||
|
/* AT&T mnemonic. */
|
||||||
|
#define ATTMnemonic (OldGcc + 1)
|
||||||
|
/* Intel mnemonic. */
|
||||||
|
#define IntelMnemonic (ATTMnemonic + 1)
|
||||||
/* The last bitfield in i386_opcode_modifier. */
|
/* The last bitfield in i386_opcode_modifier. */
|
||||||
#define Opcode_Modifier_Max Drexc
|
#define Opcode_Modifier_Max IntelMnemonic
|
||||||
|
|
||||||
typedef struct i386_opcode_modifier
|
typedef struct i386_opcode_modifier
|
||||||
{
|
{
|
||||||
|
@ -263,6 +269,9 @@ typedef struct i386_opcode_modifier
|
||||||
unsigned int drex:1;
|
unsigned int drex:1;
|
||||||
unsigned int drexv:1;
|
unsigned int drexv:1;
|
||||||
unsigned int drexc:1;
|
unsigned int drexc:1;
|
||||||
|
unsigned int oldgcc:1;
|
||||||
|
unsigned int attmnemonic:1;
|
||||||
|
unsigned int intelmnemonic:1;
|
||||||
} i386_opcode_modifier;
|
} i386_opcode_modifier;
|
||||||
|
|
||||||
/* Position of operand_type bits. */
|
/* Position of operand_type bits. */
|
||||||
|
|
|
@ -600,10 +600,8 @@ fldz, 0, 0xd9ee, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
|
||||||
fadd, 2, 0xd8c0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
fadd, 2, 0xd8c0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
||||||
// alias for fadd %st(i), %st
|
// alias for fadd %st(i), %st
|
||||||
fadd, 1, 0xd8c0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fadd, 1, 0xd8c0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
||||||
#if SYSV386_COMPAT
|
|
||||||
// alias for faddp
|
// alias for faddp
|
||||||
fadd, 0, 0xdec1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { 0 }
|
fadd, 0, 0xdec1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
|
||||||
#endif
|
|
||||||
fadd, 1, 0xd8, 0x0, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fadd, 1, 0xd8, 0x0, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
fiadd, 1, 0xde, 0x0, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fiadd, 1, 0xde, 0x0, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
|
|
||||||
|
@ -615,61 +613,43 @@ faddp, 2, 0xdec0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
|
||||||
|
|
||||||
// subtract
|
// subtract
|
||||||
fsub, 1, 0xd8e0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fsub, 1, 0xd8e0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
||||||
#if SYSV386_COMPAT
|
fsub, 2, 0xd8e0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
|
||||||
fsub, 2, 0xd8e0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
|
||||||
// alias for fsubp
|
// alias for fsubp
|
||||||
fsub, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { 0 }
|
fsub, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
|
||||||
#else
|
fsub, 2, 0xd8e0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
|
||||||
fsub, 2, 0xd8e0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
|
|
||||||
#endif
|
|
||||||
fsub, 1, 0xd8, 0x4, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fsub, 1, 0xd8, 0x4, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
fisub, 1, 0xde, 0x4, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fisub, 1, 0xde, 0x4, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
|
|
||||||
#if SYSV386_COMPAT
|
fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
|
||||||
fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg }
|
fsubp, 1, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
|
||||||
fsubp, 1, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fsubp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
|
||||||
fsubp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||||
#if OLDGCC_COMPAT
|
fsubp, 2, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
|
||||||
fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc }
|
fsubp, 1, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
|
||||||
#endif
|
fsubp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic, { 0 }
|
||||||
#else
|
|
||||||
fsubp, 2, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
|
||||||
fsubp, 1, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
|
||||||
fsubp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// subtract reverse
|
// subtract reverse
|
||||||
fsubr, 1, 0xd8e8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fsubr, 1, 0xd8e8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
||||||
#if SYSV386_COMPAT
|
fsubr, 2, 0xd8e8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
|
||||||
fsubr, 2, 0xd8e8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
|
||||||
// alias for fsubrp
|
// alias for fsubrp
|
||||||
fsubr, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { 0 }
|
fsubr, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
|
||||||
#else
|
fsubr, 2, 0xd8e8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
|
||||||
fsubr, 2, 0xd8e8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
|
|
||||||
#endif
|
|
||||||
fsubr, 1, 0xd8, 0x5, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fsubr, 1, 0xd8, 0x5, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
fisubr, 1, 0xde, 0x5, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fisubr, 1, 0xde, 0x5, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
|
|
||||||
#if SYSV386_COMPAT
|
fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
|
||||||
fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg }
|
fsubrp, 1, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
|
||||||
fsubrp, 1, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fsubrp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
|
||||||
fsubrp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||||
#if OLDGCC_COMPAT
|
fsubrp, 2, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
|
||||||
fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc }
|
fsubrp, 1, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
|
||||||
#endif
|
fsubrp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic, { 0 }
|
||||||
#else
|
|
||||||
fsubrp, 2, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
|
||||||
fsubrp, 1, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
|
||||||
fsubrp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// multiply
|
// multiply
|
||||||
fmul, 2, 0xd8c8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
fmul, 2, 0xd8c8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
||||||
fmul, 1, 0xd8c8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fmul, 1, 0xd8c8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
||||||
#if SYSV386_COMPAT
|
|
||||||
// alias for fmulp
|
// alias for fmulp
|
||||||
fmul, 0, 0xdec9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { 0 }
|
fmul, 0, 0xdec9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
|
||||||
#endif
|
|
||||||
fmul, 1, 0xd8, 0x1, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fmul, 1, 0xd8, 0x1, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
fimul, 1, 0xde, 0x1, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fimul, 1, 0xde, 0x1, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
|
|
||||||
|
@ -680,53 +660,37 @@ fmulp, 2, 0xdec8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
|
||||||
|
|
||||||
// divide
|
// divide
|
||||||
fdiv, 1, 0xd8f0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fdiv, 1, 0xd8f0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
||||||
#if SYSV386_COMPAT
|
fdiv, 2, 0xd8f0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
|
||||||
fdiv, 2, 0xd8f0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
|
||||||
// alias for fdivp
|
// alias for fdivp
|
||||||
fdiv, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { 0 }
|
fdiv, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
|
||||||
#else
|
fdiv, 2, 0xd8f0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
|
||||||
fdiv, 2, 0xd8f0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
|
|
||||||
#endif
|
|
||||||
fdiv, 1, 0xd8, 0x6, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fdiv, 1, 0xd8, 0x6, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
fidiv, 1, 0xde, 0x6, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fidiv, 1, 0xde, 0x6, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
|
|
||||||
#if SYSV386_COMPAT
|
fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
|
||||||
fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg }
|
fdivp, 1, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
|
||||||
fdivp, 1, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fdivp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
|
||||||
fdivp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||||
#if OLDGCC_COMPAT
|
fdivp, 2, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
|
||||||
fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc }
|
fdivp, 1, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
|
||||||
#endif
|
fdivp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic, { 0 }
|
||||||
#else
|
|
||||||
fdivp, 2, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
|
||||||
fdivp, 1, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
|
||||||
fdivp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// divide reverse
|
// divide reverse
|
||||||
fdivr, 1, 0xd8f8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fdivr, 1, 0xd8f8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
||||||
#if SYSV386_COMPAT
|
fdivr, 2, 0xd8f8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
|
||||||
fdivr, 2, 0xd8f8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
|
|
||||||
// alias for fdivrp
|
// alias for fdivrp
|
||||||
fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { 0 }
|
fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
|
||||||
#else
|
fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
|
||||||
fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
|
|
||||||
#endif
|
|
||||||
fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
|
|
||||||
#if SYSV386_COMPAT
|
fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
|
||||||
fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg }
|
fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
|
||||||
fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
|
fdivrp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
|
||||||
fdivrp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||||
#if OLDGCC_COMPAT
|
fdivrp, 2, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
|
||||||
fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc }
|
fdivrp, 1, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
|
||||||
#endif
|
fdivrp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic, { 0 }
|
||||||
#else
|
|
||||||
fdivrp, 2, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
|
||||||
fdivrp, 1, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
|
||||||
fdivrp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
|
|
||||||
#endif
|
|
||||||
|
|
||||||
f2xm1, 0, 0xd9f0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
f2xm1, 0, 0xd9f0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||||
fyl2x, 0, 0xd9f1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
fyl2x, 0, 0xd9f1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||||
|
|
4338
opcodes/i386-tbl.h
4338
opcodes/i386-tbl.h
File diff suppressed because it is too large
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Reference in New Issue