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bfd/ 

* elf32-sh.c (sh_elf_plt_sym_val): New function.
	(elf_backend_plt_sym_val): Define.

opcodes/
	* sh-dis.c (print_insn_sh): Print the value in constant pool
	as a symbol if it looks like a symbol.

gas/testsuite/
	* gas/sh/pcrel2.d: Update.
	* gas/sh/tlsd.d: Update.
	* gas/sh/tlsnopic.d: Update.
	* gas/sh/tlspic.d: Update.

ld/testsuite/
	* ld-sh/tlsbin-1.d: Update
	* ld-sh/tlspic-1.d: Update.
This commit is contained in:
Kaz Kojima 2004-04-23 02:47:39 +00:00
parent 4d0d148db8
commit 1f1799d5ad
12 changed files with 82 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
bfd/ChangeLog
View File

@ -1,3 +1,8 @@
2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
* elf32-sh.c (sh_elf_plt_sym_val): New function.
(elf_backend_plt_sym_val): Define.
2004-04-22 Andrew Cagney <cagney@redhat.com>
* opncls.c (bfd_alloc): Fix type of "wanted" in doco.

12
bfd/elf32-sh.c
View File

@ -7480,6 +7480,17 @@ elf32_shlin_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
return TRUE;
}
/* Return address for Ith PLT stub in section PLT, for relocation REL
or (bfd_vma) -1 if it should not be included. */
static bfd_vma
sh_elf_plt_sym_val (bfd_vma i, const asection *plt,
const arelent *rel ATTRIBUTE_UNUSED)
{
return plt->vma + (i + 1) * PLT_ENTRY_SIZE;
}
#define TARGET_BIG_SYM bfd_elf32_sh_vec
#define TARGET_BIG_NAME "elf32-sh"
#define TARGET_LITTLE_SYM bfd_elf32_shl_vec
@ -7527,6 +7538,7 @@ elf32_shlin_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
#define elf_backend_finish_dynamic_sections \
sh_elf_finish_dynamic_sections
#define elf_backend_reloc_type_class sh_elf_reloc_type_class
#define elf_backend_plt_sym_val sh_elf_plt_sym_val
#define elf_backend_can_gc_sections 1
#define elf_backend_can_refcount 1

7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
* gas/sh/pcrel2.d: Update.
* gas/sh/tlsd.d: Update.
* gas/sh/tlsnopic.d: Update.
* gas/sh/tlspic.d: Update.
2004-04-22 Mark Kettenis <kettenis@gnu.org>
* lib/gas-defs.exp (is_elf_format): Add OpenBSD support.

4
gas/testsuite/gas/sh/pcrel2.d
View File

@ -8,8 +8,8 @@ Disassembly of section \.text:
00000000 <code>:
0: 8b 01 bf 6 <foo>
2: d0 02 mov\.l c <bar>,r0 ! 0x6
4: 90 02 mov\.w c <bar>,r0 ! 0x0
2: d0 02 mov\.l c <bar>,r0 ! 0x6 .*
4: 90 02 mov\.w c <bar>,r0 ! 0x0 .*
00000006 <foo>:
6: af fe bra 6 <foo>

14
gas/testsuite/gas/sh/tlsd.d
View File

@ -11,12 +11,12 @@ Disassembly of section .text:
2: 2f e6 [ ]*mov\.l r14,@-r15
4: 4f 22 [ ]*sts\.l pr,@-r15
6: c7 14 [ ]*mova 58 <fn\+0x58>,r0
8: dc 13 [ ]*mov\.l 58 <fn\+0x58>,r12[ ]+! 0x0
8: dc 13 [ ]*mov\.l 58 <fn\+0x58>,r12[ ]+! 0x0 .*
a: 3c 0c [ ]*add r0,r12
c: 6e f3 [ ]*mov r15,r14
e: d4 04 [ ]*mov\.l 20 <fn\+0x20>,r4[ ]+! 0x0
e: d4 04 [ ]*mov\.l 20 <fn\+0x20>,r4[ ]+! 0x0 .*
10: c7 04 [ ]*mova 24 <fn\+0x24>,r0
12: d1 04 [ ]*mov\.l 24 <fn\+0x24>,r1[ ]+! 0x0
12: d1 04 [ ]*mov\.l 24 <fn\+0x24>,r1[ ]+! 0x0 .*
14: 31 0c [ ]*add r0,r1
16: 41 0b [ ]*jsr @r1
18: 34 cc [ ]*add r12,r4
@ -26,9 +26,9 @@ Disassembly of section .text:
\.\.\.
[ ]+20: R_SH_TLS_GD_32 foo
[ ]+24: R_SH_PLT32 __tls_get_addr
28: d4 03 [ ]*mov\.l 38 <fn\+0x38>,r4[ ]+! 0x0
28: d4 03 [ ]*mov\.l 38 <fn\+0x38>,r4[ ]+! 0x0 .*
2a: c7 04 [ ]*mova 3c <fn\+0x3c>,r0
2c: d1 03 [ ]*mov\.l 3c <fn\+0x3c>,r1[ ]+! 0x0
2c: d1 03 [ ]*mov\.l 3c <fn\+0x3c>,r1[ ]+! 0x0 .*
2e: 31 0c [ ]*add r0,r1
30: 41 0b [ ]*jsr @r1
32: 34 cc [ ]*add r12,r4
@ -38,10 +38,10 @@ Disassembly of section .text:
[ ]+38: R_SH_TLS_LD_32 bar
[ ]+3c: R_SH_PLT32 __tls_get_addr
40: e2 01 [ ]*mov #1,r2
42: d1 06 [ ]*mov\.l 5c <fn\+0x5c>,r1[ ]+! 0x0
42: d1 06 [ ]*mov\.l 5c <fn\+0x5c>,r1[ ]+! 0x0 .*
44: 30 1c [ ]*add r1,r0
46: 20 22 [ ]*mov\.l r2,@r0
48: d1 05 [ ]*mov\.l 60 <fn\+0x60>,r1[ ]+! 0x0
48: d1 05 [ ]*mov\.l 60 <fn\+0x60>,r1[ ]+! 0x0 .*
4a: 30 1c [ ]*add r1,r0
4c: 6f e3 [ ]*mov r14,r15
4e: 4f 26 [ ]*lds\.l @r15\+,pr

2
gas/testsuite/gas/sh/tlsnopic.d
View File

@ -10,7 +10,7 @@ Disassembly of section .text:
0: 2f e6 [ ]*mov\.l r14,@-r15
2: 6e f3 [ ]*mov r15,r14
4: 01 12 [ ]*stc gbr,r1
6: d0 02 [ ]*mov\.l 10 <fn\+0x10>,r0[ ]+! 0x0
6: d0 02 [ ]*mov\.l 10 <fn\+0x10>,r0[ ]+! 0x0 .*
8: 30 1c [ ]*add r1,r0
a: 6f e3 [ ]*mov r14,r15
c: 00 0b [ ]*rts

4
gas/testsuite/gas/sh/tlspic.d
View File

@ -11,9 +11,9 @@ Disassembly of section .text:
2: 2f e6 [ ]*mov\.l r14,@-r15
4: 6e f3 [ ]*mov r15,r14
6: c7 08 [ ]*mova 28 <fn\+0x28>,r0
8: dc 07 [ ]*mov\.l 28 <fn\+0x28>,r12[ ]+! 0x0
8: dc 07 [ ]*mov\.l 28 <fn\+0x28>,r12[ ]+! 0x0 .*
a: 3c 0c [ ]*add r0,r12
c: d0 02 [ ]*mov\.l 18 <fn\+0x18>,r0[ ]+! 0x0
c: d0 02 [ ]*mov\.l 18 <fn\+0x18>,r0[ ]+! 0x0 .*
e: 01 12 [ ]*stc gbr,r1
10: 00 ce [ ]*mov\.l @\(r0,r12\),r0
12: a0 03 [ ]*bra 1c <fn\+0x1c>

5
ld/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
* ld-sh/tlsbin-1.d: Update
* ld-sh/tlspic-1.d: Update.
2004-04-22 H.J. Lu <hongjiu.lu@intel.com>
* ld-i386/tlspic.dd: Updated.

36
ld/testsuite/ld-sh/tlsbin-1.d
View File

@ -21,7 +21,7 @@ Disassembly of section \.text:
401010: 09 00 nop
401012: 09 00 nop
401014: 09 00 nop
401016: 04 d0 mov\.l 401028 <fn2\+0x28>,r0 ! 0x1c
401016: 04 d0 mov\.l 401028 <fn2\+0x28>,r0 ! 0x1c .*
401018: 12 04 stc gbr,r4
40101a: ce 00 mov\.l @\(r0,r12\),r0
40101c: 4c 30 add r4,r0
@ -38,7 +38,7 @@ Disassembly of section \.text:
401032: 09 00 nop
401034: 09 00 nop
401036: 09 00 nop
401038: 03 d0 mov\.l 401048 <fn2\+0x48>,r0 ! 0x14
401038: 03 d0 mov\.l 401048 <fn2\+0x48>,r0 ! 0x14 .*
40103a: 12 04 stc gbr,r4
40103c: ce 00 mov\.l @\(r0,r12\),r0
40103e: 4c 30 add r4,r0
@ -54,7 +54,7 @@ Disassembly of section \.text:
401052: 09 00 nop
401054: 09 00 nop
401056: 09 00 nop
401058: 03 d4 mov\.l 401068 <fn2\+0x68>,r4 ! 0x8
401058: 03 d4 mov\.l 401068 <fn2\+0x68>,r4 ! 0x8 .*
40105a: 12 00 stc gbr,r0
40105c: 4c 30 add r4,r0
40105e: 09 00 nop
@ -70,7 +70,7 @@ Disassembly of section \.text:
401072: 09 00 nop
401074: 09 00 nop
401076: 09 00 nop
401078: 03 d4 mov\.l 401088 <fn2\+0x88>,r4 ! 0x10
401078: 03 d4 mov\.l 401088 <fn2\+0x88>,r4 ! 0x10 .*
40107a: 12 00 stc gbr,r0
40107c: 4c 30 add r4,r0
40107e: 09 00 nop
@ -86,7 +86,7 @@ Disassembly of section \.text:
401092: 09 00 nop
401094: 09 00 nop
401096: 09 00 nop
401098: 03 d4 mov\.l 4010a8 <fn2\+0xa8>,r4 ! 0x18
401098: 03 d4 mov\.l 4010a8 <fn2\+0xa8>,r4 ! 0x18 .*
40109a: 12 00 stc gbr,r0
40109c: 4c 30 add r4,r0
40109e: 09 00 nop
@ -116,11 +116,11 @@ Disassembly of section \.text:
4010ce: [0-9a-f]+ [0-9a-f]+ .*[ ]*.*
4010d0: 09 00 nop
4010d2: 09 00 nop
4010d4: 2c d1 mov\.l 401188 <fn2\+0x188>,r1 ! 0x10
4010d4: 2c d1 mov\.l 401188 <fn2\+0x188>,r1 ! 0x10 .*
4010d6: 0c 31 add r0,r1
4010d8: 09 00 nop
4010da: 09 00 nop
4010dc: 2b d2 mov\.l 40118c <fn2\+0x18c>,r2 ! 0x14
4010dc: 2b d2 mov\.l 40118c <fn2\+0x18c>,r2 ! 0x14 .*
4010de: 0c 32 add r0,r2
4010e0: 09 00 nop
4010e2: 09 00 nop
@ -140,17 +140,17 @@ Disassembly of section \.text:
4010fe: [0-9a-f]+ [0-9a-f]+ .*[ ]*.*
401100: 09 00 nop
401102: 09 00 nop
401104: 22 d1 mov\.l 401190 <fn2\+0x190>,r1 ! 0x18
401104: 22 d1 mov\.l 401190 <fn2\+0x190>,r1 ! 0x18 .*
401106: 0c 31 add r0,r1
401108: 09 00 nop
40110a: 09 00 nop
40110c: 21 d2 mov\.l 401194 <fn2\+0x194>,r2 ! 0x1c
40110c: 21 d2 mov\.l 401194 <fn2\+0x194>,r2 ! 0x1c .*
40110e: 0c 32 add r0,r2
401110: 09 00 nop
401112: 09 00 nop
401114: 09 00 nop
401116: 09 00 nop
401118: 02 d0 mov\.l 401124 <fn2\+0x124>,r0 ! 0x14
401118: 02 d0 mov\.l 401124 <fn2\+0x124>,r0 ! 0x14 .*
40111a: 12 01 stc gbr,r1
40111c: ce 00 mov\.l @\(r0,r12\),r0
40111e: 03 a0 bra 401128 <fn2\+0x128>
@ -162,7 +162,7 @@ Disassembly of section \.text:
40112a: 09 00 nop
40112c: 09 00 nop
40112e: 09 00 nop
401130: 02 d0 mov\.l 40113c <fn2\+0x13c>,r0 ! 0x18
401130: 02 d0 mov\.l 40113c <fn2\+0x13c>,r0 ! 0x18 .*
401132: 12 01 stc gbr,r1
401134: ce 00 mov\.l @\(r0,r12\),r0
401136: 03 a0 bra 401140 <fn2\+0x140>
@ -174,7 +174,7 @@ Disassembly of section \.text:
401142: 09 00 nop
401144: 09 00 nop
401146: 09 00 nop
401148: 02 d0 mov\.l 401154 <fn2\+0x154>,r0 ! 0x8
401148: 02 d0 mov\.l 401154 <fn2\+0x154>,r0 ! 0x8 .*
40114a: 12 01 stc gbr,r1
40114c: 09 00 nop
40114e: 03 a0 bra 401158 <fn2\+0x158>
@ -186,7 +186,7 @@ Disassembly of section \.text:
40115a: 09 00 nop
40115c: 09 00 nop
40115e: 09 00 nop
401160: 02 d0 mov\.l 40116c <fn2\+0x16c>,r0 ! 0x18
401160: 02 d0 mov\.l 40116c <fn2\+0x16c>,r0 ! 0x18 .*
401162: 12 01 stc gbr,r1
401164: 09 00 nop
401166: 03 a0 bra 401170 <fn2\+0x170>
@ -226,7 +226,7 @@ Disassembly of section \.text:
40200e: 09 00 nop
402010: 09 00 nop
402012: 09 00 nop
402014: 02 d0 mov\.l 402020 <_start\+0x20>,r0 ! 0x10
402014: 02 d0 mov\.l 402020 <_start\+0x20>,r0 ! 0x10 .*
402016: 12 01 stc gbr,r1
402018: ce 00 mov\.l @\(r0,r12\),r0
40201a: 03 a0 bra 402024 <_start\+0x24>
@ -238,7 +238,7 @@ Disassembly of section \.text:
402026: 09 00 nop
402028: 09 00 nop
40202a: 09 00 nop
40202c: 02 d0 mov\.l 402038 <_start\+0x38>,r0 ! 0x20
40202c: 02 d0 mov\.l 402038 <_start\+0x38>,r0 ! 0x20 .*
40202e: 12 01 stc gbr,r1
402030: 09 00 nop
402032: 03 a0 bra 40203c <_start\+0x3c>
@ -262,7 +262,7 @@ Disassembly of section \.text:
402056: 09 00 nop
402058: 09 00 nop
40205a: 09 00 nop
40205c: 02 d0 mov\.l 402068 <_start\+0x68>,r0 ! 0x1c
40205c: 02 d0 mov\.l 402068 <_start\+0x68>,r0 ! 0x1c .*
40205e: 12 01 stc gbr,r1
402060: 09 00 nop
402062: 03 a0 bra 40206c <_start\+0x6c>
@ -275,7 +275,7 @@ Disassembly of section \.text:
402070: 09 00 nop
402072: 09 00 nop
402074: 12 01 stc gbr,r1
402076: 0c d0 mov\.l 4020a8 <_start\+0xa8>,r0 ! 0x8
402076: 0c d0 mov\.l 4020a8 <_start\+0xa8>,r0 ! 0x8 .*
402078: 1c 30 add r1,r0
40207a: 09 00 nop
40207c: 09 00 nop
@ -289,7 +289,7 @@ Disassembly of section \.text:
40208c: 09 00 nop
40208e: 09 00 nop
402090: 12 01 stc gbr,r1
402092: 07 d0 mov\.l 4020b0 <_start\+0xb0>,r0 ! 0x18
402092: 07 d0 mov\.l 4020b0 <_start\+0xb0>,r0 ! 0x18 .*
402094: 1c 30 add r1,r0
402096: 09 00 nop
402098: 09 00 nop

22
ld/testsuite/ld-sh/tlspic-1.d
View File

@ -54,7 +54,7 @@ Disassembly of section \.text:
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x68>,r4 ! 0x10
[0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x68>,r4 ! 0x10 .*
[0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0x6c>,r0
[0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0x6c>,r1 ! 0x[0-9a-f]+
[0-9a-f]+: 0c 31 add r0,r1
@ -70,7 +70,7 @@ Disassembly of section \.text:
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 03 d0 mov\.l [0-9a-f]+ <fn1\+0x88>,r0 ! 0x18
[0-9a-f]+: 03 d0 mov\.l [0-9a-f]+ <fn1\+0x88>,r0 ! 0x18 .*
[0-9a-f]+: 12 04 stc gbr,r4
[0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0
[0-9a-f]+: 4c 30 add r4,r0
@ -150,7 +150,7 @@ Disassembly of section \.text:
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x128>,r4 ! 0x1c
[0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x128>,r4 ! 0x1c .*
[0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0x12c>,r0
[0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0x12c>,r1 ! 0x[0-9a-f]+
[0-9a-f]+: 0c 31 add r0,r1
@ -164,11 +164,11 @@ Disassembly of section \.text:
[0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.*
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 38 d1 mov\.l [0-9a-f]+ <fn1\+0x218>,r1 ! 0x8
[0-9a-f]+: 38 d1 mov\.l [0-9a-f]+ <fn1\+0x218>,r1 ! 0x8 .*
[0-9a-f]+: 0c 31 add r0,r1
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 37 d2 mov\.l [0-9a-f]+ <fn1\+0x21c>,r2 ! 0xc
[0-9a-f]+: 37 d2 mov\.l [0-9a-f]+ <fn1\+0x21c>,r2 ! 0xc .*
[0-9a-f]+: 0c 32 add r0,r2
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
@ -188,17 +188,17 @@ Disassembly of section \.text:
[0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.*
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 2e d1 mov\.l [0-9a-f]+ <fn1\+0x220>,r1 ! 0x10
[0-9a-f]+: 2e d1 mov\.l [0-9a-f]+ <fn1\+0x220>,r1 ! 0x10 .*
[0-9a-f]+: 0c 31 add r0,r1
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 2d d2 mov\.l [0-9a-f]+ <fn1\+0x224>,r2 ! 0x14
[0-9a-f]+: 2d d2 mov\.l [0-9a-f]+ <fn1\+0x224>,r2 ! 0x14 .*
[0-9a-f]+: 0c 32 add r0,r2
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x188>,r4 ! 0x1c
[0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x188>,r4 ! 0x1c .*
[0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0x18c>,r0
[0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0x18c>,r1 ! 0x[0-9a-f]+
[0-9a-f]+: 0c 31 add r0,r1
@ -212,11 +212,11 @@ Disassembly of section \.text:
[0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.*
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 24 d1 mov\.l [0-9a-f]+ <fn1\+0x228>,r1 ! 0x18
[0-9a-f]+: 24 d1 mov\.l [0-9a-f]+ <fn1\+0x228>,r1 ! 0x18 .*
[0-9a-f]+: 0c 31 add r0,r1
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 23 d2 mov\.l [0-9a-f]+ <fn1\+0x22c>,r2 ! 0x1c
[0-9a-f]+: 23 d2 mov\.l [0-9a-f]+ <fn1\+0x22c>,r2 ! 0x1c .*
[0-9a-f]+: 0c 32 add r0,r2
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
@ -234,7 +234,7 @@ Disassembly of section \.text:
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 09 00 nop
[0-9a-f]+: 02 d0 mov\.l [0-9a-f]+ <fn1\+0x1cc>,r0 ! 0x18
[0-9a-f]+: 02 d0 mov\.l [0-9a-f]+ <fn1\+0x1cc>,r0 ! 0x18 .*
[0-9a-f]+: 12 01 stc gbr,r1
[0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0
[0-9a-f]+: 03 a0 bra [0-9a-f]+ <fn1\+0x1d0>

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
* sh-dis.c (print_insn_sh): Print the value in constant pool
as a symbol if it looks like a symbol.
2004-04-22 Peter Barada <peter@the-baradas.com>
* m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on

8
opcodes/sh-dis.c
View File

@ -855,7 +855,13 @@ print_insn_sh (memaddr, info)
else
val = bfd_getb32 (bytes);
}
fprintf_fn (stream, "\t! 0x%x", val);
if ((*info->symbol_at_address_func) (val, info))
{
fprintf_fn (stream, "\t! 0x");
(*info->print_address_func) (val, info);
}
else
fprintf_fn (stream, "\t! 0x%x", val);
}
}