[ gas/ChangeLog ]
2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * config/tc-mips.c (mips_set_options): New "ase_mips3d" member. (mips_opts): Initialize "ase_mips3d" member. (file_ase_mips3d): New variable. (CPU_HAS_MIPS3D): New macro. (md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d based on command line options and configuration defaults. (macro_build, mips_ip): Accept MIPS-3D instructions if mips_opts.ase_mips3d is set. (OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option): Add support for "-mips3d" and "-no-mips3d" options. (OPTION_ELF_BASE): Move to accomodate new options. (s_mipsset): Support ".set mips3d" and ".set nomips3d". (mips_elf_final_processing): Add a comment indicating that a MIPS-3D ASE ELF header flag should be set, when one exists. * doc/as.texinfo: Document -mips3d and -no-mips3d options. * doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set nomips3d" directives. [ gas/testsuite/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * gas/mips/mips64-mips3d.s: New file. * gas/mips/mips64-mips3d.d: Likewise. * gas/mips/mips.exp: Run new "mips64-mips3d" test. [ include/opcode/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D instructions. (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks may be passed along with the ISA bitmask. [ opcodes/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that indicate that they should dissassemble all applicable MIPS-specified ASEs. * mips-opc.c: Add support for MIPS-3D instructions. (M3D): New definition. * mips-opc.c: Update copyright years.
This commit is contained in:
Chris Demetriou
parent
376c960019
commit
1f25f5d300
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@ -1,3 +1,23 @@
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2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
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* config/tc-mips.c (mips_set_options): New "ase_mips3d" member.
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(mips_opts): Initialize "ase_mips3d" member.
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(file_ase_mips3d): New variable.
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(CPU_HAS_MIPS3D): New macro.
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(md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d
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based on command line options and configuration defaults.
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(macro_build, mips_ip): Accept MIPS-3D instructions if
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mips_opts.ase_mips3d is set.
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(OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option):
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Add support for "-mips3d" and "-no-mips3d" options.
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(OPTION_ELF_BASE): Move to accomodate new options.
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(s_mipsset): Support ".set mips3d" and ".set nomips3d".
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(mips_elf_final_processing): Add a comment indicating that a
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MIPS-3D ASE ELF header flag should be set, when one exists.
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* doc/as.texinfo: Document -mips3d and -no-mips3d options.
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* doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set
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nomips3d" directives.
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2002-03-14 Hans-Peter Nilsson <hp@bitrange.com>
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* config/tc-mmix.c (md_estimate_size_before_relax): Don't consider
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@ -137,6 +137,10 @@ struct mips_set_options
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if it has not been initialized. Changed by `.set mipsN', and the
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-mipsN command line option, and the default CPU. */
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int isa;
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/* Enabled Application Specific Extensions (ASEs). These are set to -1
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if they have not been initialized. Changed by `.set <asename>', by
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command line options, and based on the default architecture. */
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int ase_mips3d;
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/* Whether we are assembling for the mips16 processor. 0 if we are
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not, 1 if we are, and -1 if the value has not been initialized.
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Changed by `.set mips16' and `.set nomips16', and the -mips16 and
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@ -185,7 +189,7 @@ static int file_mips_fp32 = -1;
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static struct mips_set_options mips_opts =
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{
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ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
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ISA_UNKNOWN, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
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};
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/* These variables are filled in with the masks of registers used.
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@ -197,6 +201,10 @@ unsigned long mips_cprmask[4];
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/* MIPS ISA we are using for this output file. */
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static int file_mips_isa = ISA_UNKNOWN;
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/* True if -mips3d was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mips3d;
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/* The argument of the -mcpu= flag. Historical for code generation. */
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static int mips_cpu = CPU_UNKNOWN;
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@ -263,6 +271,10 @@ static int mips_32bitmode = 0;
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#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
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/* Return true if the given CPU supports the MIPS3D ASE. */
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#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
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)
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/* Whether the processor uses hardware interlocks to protect
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reads from the HI and LO registers, and thus does not
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require nops to be inserted. */
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@ -1223,6 +1235,11 @@ md_begin ()
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&& ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
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mips_32bitmode = 1;
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/* If the selected architecture includes support for ASEs, enable
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generation of code for them. */
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if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch))
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mips_opts.ase_mips3d = 1;
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
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as_warn (_("Could not set architecture and machine"));
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@ -1233,6 +1250,7 @@ md_begin ()
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file_mips_isa = mips_opts.isa;
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file_mips_abi = mips_opts.abi;
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file_ase_mips3d = mips_opts.ase_mips3d;
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mips_opts.gp32 = file_mips_gp32;
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mips_opts.fp32 = file_mips_fp32;
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@ -2885,7 +2903,10 @@ macro_build (place, counter, ep, name, fmt, va_alist)
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{
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if (strcmp (fmt, insn.insn_mo->args) == 0
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&& insn.insn_mo->pinfo != INSN_MACRO
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&& OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
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&& OPCODE_IS_MEMBER (insn.insn_mo,
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(mips_opts.isa
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| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
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mips_arch)
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&& (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
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break;
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@ -7670,7 +7691,10 @@ mips_ip (str, ip)
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assert (strcmp (insn->name, str) == 0);
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if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch))
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if (OPCODE_IS_MEMBER (insn,
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(mips_opts.isa
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| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
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mips_arch))
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ok = true;
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else
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ok = false;
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@ -9738,8 +9762,12 @@ struct option md_longopts[] =
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{"no-m3900", no_argument, NULL, OPTION_NO_M3900},
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#define OPTION_GP64 (OPTION_MD_BASE + 32)
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{"mgp64", no_argument, NULL, OPTION_GP64},
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#define OPTION_MIPS3D (OPTION_MD_BASE + 33)
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{"mips3d", no_argument, NULL, OPTION_MIPS3D},
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#define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
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{"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
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#ifdef OBJ_ELF
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#define OPTION_ELF_BASE (OPTION_MD_BASE + 33)
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#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
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#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
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{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
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{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
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@ -9954,6 +9982,14 @@ md_parse_option (c, arg)
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mips_no_prev_insn (false);
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break;
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case OPTION_MIPS3D:
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mips_opts.ase_mips3d = 1;
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break;
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case OPTION_NO_MIPS3D:
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mips_opts.ase_mips3d = 0;
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break;
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case OPTION_MEMBEDDED_PIC:
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mips_pic = EMBEDDED_PIC;
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if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
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@ -11275,6 +11311,10 @@ s_mipsset (x)
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else if (strcmp (name, "nomips16") == 0
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|| strcmp (name, "noMIPS-16") == 0)
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mips_opts.mips16 = 0;
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else if (strcmp (name, "mips3d") == 0)
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mips_opts.ase_mips3d = 1;
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else if (strcmp (name, "nomips3d") == 0)
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mips_opts.ase_mips3d = 0;
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else if (strncmp (name, "mips", 4) == 0)
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{
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int isa;
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@ -12763,6 +12803,12 @@ mips_elf_final_processing ()
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if (mips_pic != NO_PIC)
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elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
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/* Set MIPS ELF flags for ASEs. */
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#if 0 /* XXX FIXME */
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if (file_ase_mips3d)
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elf_elfheader (stdoutput)->e_flags |= ???;
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#endif
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/* Set the MIPS ELF ABI flags. */
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if (file_mips_abi == NO_ABI)
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;
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@ -374,6 +374,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mips1}] [@b{-mips2}] [@b{-mips3}] [@b{-mips4}] [@b{-mips5}]
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[@b{-mips32}] [@b{-mips64}]
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[@b{-m4650}] [@b{-no-m4650}]
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[@b{-mips3d}] [@b{-no-mips3d}]
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[@b{--trap}] [@b{--break}] [@b{-n}]
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[@b{--emulation}=@var{name} ]
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@end ifset
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@ -881,6 +882,12 @@ the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
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instructions around accesses to the @samp{HI} and @samp{LO} registers.
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@samp{-no-m4650} turns off this option.
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@item -mips3d
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@itemx -no-mips3d
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Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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@samp{-no-mips3d} turns off this option.
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@item -mcpu=@var{CPU}
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Generate code for a particular MIPS cpu. It is exactly equivalent to
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@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
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@ -97,6 +97,12 @@ Generate code for the MIPS 16 processor. This is equivalent to putting
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@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
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turns off this option.
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@item -mips3d
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@itemx -no-mips3d
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Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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@samp{-no-mips3d} turns off this option.
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@item -mfix7000
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@itemx -no-mfix7000
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Cause nops to be inserted if the read of the destination register
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@ -323,3 +329,16 @@ option such as the ISA level or instruction reordering but does not want
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to change the state of the code which invoked the macro.
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Traditional @sc{mips} assemblers do not support these directives.
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@node MIPS ASE instruction generation overrides
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@section Directives to control generation of MIPS ASE instructions
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@cindex MIPS MIPS-3D instruction generation override
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@kindex @code{.set mips3d}
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@kindex @code{.set nomips3d}
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The directive @code{.set mips3d} makes the assembler accept instructions
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from the MIPS-3D Application Specific Extension from that point on
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in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
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instructions from being accepted.
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Traditional @sc{mips} assemblers do not support these directives.
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@ -1,3 +1,9 @@
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2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
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* gas/mips/mips64-mips3d.s: New file.
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* gas/mips/mips64-mips3d.d: Likewise.
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* gas/mips/mips.exp: Run new "mips64-mips3d" test.
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2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
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* gas/mips/mips.exp: Use elf-rel2 and elfel-rel2 for
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@ -142,6 +142,7 @@ if { [istarget mips*-*-*] } then {
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run_dump_test "sync"
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run_dump_test "mips32"
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run_dump_test "mips64"
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run_dump_test "mips64-mips3d"
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run_dump_test "sb1-ext-ps"
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# It will always fail until someone fixes it.
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@ -0,0 +1,138 @@
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#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa64
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#name: MIPS MIPS64 MIPS-3D ASE instructions
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#as: -mips64 -mips3d
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# Check MIPS64 MIPS-3D ASE instruction assembly and disassembly
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> 46d34118 addr\.ps \$f4,\$f8,\$f19
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0+0004 <[^>]*> 4520fffe bc1any2f \$fcc0,0+0000 <text_label>
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0+0008 <[^>]*> 00000000 nop
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0+000c <[^>]*> 4528fffc bc1any2f \$fcc2,0+0000 <text_label>
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0+0010 <[^>]*> 00000000 nop
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0+0014 <[^>]*> 4521fffa bc1any2t \$fcc0,0+0000 <text_label>
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0+0018 <[^>]*> 00000000 nop
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0+001c <[^>]*> 4531fff8 bc1any2t \$fcc4,0+0000 <text_label>
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0+0020 <[^>]*> 00000000 nop
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0+0024 <[^>]*> 4540fff6 bc1any4f \$fcc0,0+0000 <text_label>
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0+0028 <[^>]*> 00000000 nop
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0+002c <[^>]*> 4550fff4 bc1any4f \$fcc4,0+0000 <text_label>
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0+0030 <[^>]*> 00000000 nop
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0+0034 <[^>]*> 4541fff2 bc1any4t \$fcc0,0+0000 <text_label>
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0+0038 <[^>]*> 00000000 nop
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0+003c <[^>]*> 4551fff0 bc1any4t \$fcc4,0+0000 <text_label>
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0+0040 <[^>]*> 00000000 nop
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0+0044 <[^>]*> 46334070 cabs\.f\.d \$fcc0,\$f8,\$f19
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0+0048 <[^>]*> 46334270 cabs\.f\.d \$fcc2,\$f8,\$f19
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0+004c <[^>]*> 46134070 cabs\.f\.s \$fcc0,\$f8,\$f19
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0+0050 <[^>]*> 46134270 cabs\.f\.s \$fcc2,\$f8,\$f19
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0+0054 <[^>]*> 46d34070 cabs\.f\.ps \$fcc0,\$f8,\$f19
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0+0058 <[^>]*> 46d34270 cabs\.f\.ps \$fcc2,\$f8,\$f19
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0+005c <[^>]*> 46334071 cabs\.un\.d \$fcc0,\$f8,\$f19
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0+0060 <[^>]*> 46334271 cabs\.un\.d \$fcc2,\$f8,\$f19
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0+0064 <[^>]*> 46134071 cabs\.un\.s \$fcc0,\$f8,\$f19
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0+0068 <[^>]*> 46134271 cabs\.un\.s \$fcc2,\$f8,\$f19
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0+006c <[^>]*> 46d34071 cabs\.un\.ps \$fcc0,\$f8,\$f19
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0+0070 <[^>]*> 46d34271 cabs\.un\.ps \$fcc2,\$f8,\$f19
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0+0074 <[^>]*> 46334072 cabs\.eq\.d \$fcc0,\$f8,\$f19
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0+0078 <[^>]*> 46334272 cabs\.eq\.d \$fcc2,\$f8,\$f19
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0+007c <[^>]*> 46134072 cabs\.eq\.s \$fcc0,\$f8,\$f19
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0+0080 <[^>]*> 46134272 cabs\.eq\.s \$fcc2,\$f8,\$f19
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0+0084 <[^>]*> 46d34072 cabs\.eq\.ps \$fcc0,\$f8,\$f19
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0+0088 <[^>]*> 46d34272 cabs\.eq\.ps \$fcc2,\$f8,\$f19
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0+008c <[^>]*> 46334073 cabs\.ueq\.d \$fcc0,\$f8,\$f19
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0+0090 <[^>]*> 46334273 cabs\.ueq\.d \$fcc2,\$f8,\$f19
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0+0094 <[^>]*> 46134073 cabs\.ueq\.s \$fcc0,\$f8,\$f19
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0+0098 <[^>]*> 46134273 cabs\.ueq\.s \$fcc2,\$f8,\$f19
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0+009c <[^>]*> 46d34073 cabs\.ueq\.ps \$fcc0,\$f8,\$f19
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0+00a0 <[^>]*> 46d34273 cabs\.ueq\.ps \$fcc2,\$f8,\$f19
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0+00a4 <[^>]*> 46334074 cabs\.olt\.d \$fcc0,\$f8,\$f19
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0+00a8 <[^>]*> 46334274 cabs\.olt\.d \$fcc2,\$f8,\$f19
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0+00ac <[^>]*> 46134074 cabs\.olt\.s \$fcc0,\$f8,\$f19
|
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0+00b0 <[^>]*> 46134274 cabs\.olt\.s \$fcc2,\$f8,\$f19
|
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0+00b4 <[^>]*> 46d34074 cabs\.olt\.ps \$fcc0,\$f8,\$f19
|
||||
0+00b8 <[^>]*> 46d34274 cabs\.olt\.ps \$fcc2,\$f8,\$f19
|
||||
0+00bc <[^>]*> 46334075 cabs\.ult\.d \$fcc0,\$f8,\$f19
|
||||
0+00c0 <[^>]*> 46334275 cabs\.ult\.d \$fcc2,\$f8,\$f19
|
||||
0+00c4 <[^>]*> 46134075 cabs\.ult\.s \$fcc0,\$f8,\$f19
|
||||
0+00c8 <[^>]*> 46134275 cabs\.ult\.s \$fcc2,\$f8,\$f19
|
||||
0+00cc <[^>]*> 46d34075 cabs\.ult\.ps \$fcc0,\$f8,\$f19
|
||||
0+00d0 <[^>]*> 46d34275 cabs\.ult\.ps \$fcc2,\$f8,\$f19
|
||||
0+00d4 <[^>]*> 46334076 cabs\.ole\.d \$fcc0,\$f8,\$f19
|
||||
0+00d8 <[^>]*> 46334276 cabs\.ole\.d \$fcc2,\$f8,\$f19
|
||||
0+00dc <[^>]*> 46134076 cabs\.ole\.s \$fcc0,\$f8,\$f19
|
||||
0+00e0 <[^>]*> 46134276 cabs\.ole\.s \$fcc2,\$f8,\$f19
|
||||
0+00e4 <[^>]*> 46d34076 cabs\.ole\.ps \$fcc0,\$f8,\$f19
|
||||
0+00e8 <[^>]*> 46d34276 cabs\.ole\.ps \$fcc2,\$f8,\$f19
|
||||
0+00ec <[^>]*> 46334077 cabs\.ule\.d \$fcc0,\$f8,\$f19
|
||||
0+00f0 <[^>]*> 46334277 cabs\.ule\.d \$fcc2,\$f8,\$f19
|
||||
0+00f4 <[^>]*> 46134077 cabs\.ule\.s \$fcc0,\$f8,\$f19
|
||||
0+00f8 <[^>]*> 46134277 cabs\.ule\.s \$fcc2,\$f8,\$f19
|
||||
0+00fc <[^>]*> 46d34077 cabs\.ule\.ps \$fcc0,\$f8,\$f19
|
||||
0+0100 <[^>]*> 46d34277 cabs\.ule\.ps \$fcc2,\$f8,\$f19
|
||||
0+0104 <[^>]*> 46334078 cabs\.sf\.d \$fcc0,\$f8,\$f19
|
||||
0+0108 <[^>]*> 46334278 cabs\.sf\.d \$fcc2,\$f8,\$f19
|
||||
0+010c <[^>]*> 46134078 cabs\.sf\.s \$fcc0,\$f8,\$f19
|
||||
0+0110 <[^>]*> 46134278 cabs\.sf\.s \$fcc2,\$f8,\$f19
|
||||
0+0114 <[^>]*> 46d34078 cabs\.sf\.ps \$fcc0,\$f8,\$f19
|
||||
0+0118 <[^>]*> 46d34278 cabs\.sf\.ps \$fcc2,\$f8,\$f19
|
||||
0+011c <[^>]*> 46334079 cabs\.ngle\.d \$fcc0,\$f8,\$f19
|
||||
0+0120 <[^>]*> 46334279 cabs\.ngle\.d \$fcc2,\$f8,\$f19
|
||||
0+0124 <[^>]*> 46134079 cabs\.ngle\.s \$fcc0,\$f8,\$f19
|
||||
0+0128 <[^>]*> 46134279 cabs\.ngle\.s \$fcc2,\$f8,\$f19
|
||||
0+012c <[^>]*> 46d34079 cabs\.ngle\.ps \$fcc0,\$f8,\$f19
|
||||
0+0130 <[^>]*> 46d34279 cabs\.ngle\.ps \$fcc2,\$f8,\$f19
|
||||
0+0134 <[^>]*> 4633407a cabs\.seq\.d \$fcc0,\$f8,\$f19
|
||||
0+0138 <[^>]*> 4633427a cabs\.seq\.d \$fcc2,\$f8,\$f19
|
||||
0+013c <[^>]*> 4613407a cabs\.seq\.s \$fcc0,\$f8,\$f19
|
||||
0+0140 <[^>]*> 4613427a cabs\.seq\.s \$fcc2,\$f8,\$f19
|
||||
0+0144 <[^>]*> 46d3407a cabs\.seq\.ps \$fcc0,\$f8,\$f19
|
||||
0+0148 <[^>]*> 46d3427a cabs\.seq\.ps \$fcc2,\$f8,\$f19
|
||||
0+014c <[^>]*> 4633407b cabs\.ngl\.d \$fcc0,\$f8,\$f19
|
||||
0+0150 <[^>]*> 4633427b cabs\.ngl\.d \$fcc2,\$f8,\$f19
|
||||
0+0154 <[^>]*> 4613407b cabs\.ngl\.s \$fcc0,\$f8,\$f19
|
||||
0+0158 <[^>]*> 4613427b cabs\.ngl\.s \$fcc2,\$f8,\$f19
|
||||
0+015c <[^>]*> 46d3407b cabs\.ngl\.ps \$fcc0,\$f8,\$f19
|
||||
0+0160 <[^>]*> 46d3427b cabs\.ngl\.ps \$fcc2,\$f8,\$f19
|
||||
0+0164 <[^>]*> 4633407c cabs\.lt\.d \$fcc0,\$f8,\$f19
|
||||
0+0168 <[^>]*> 4633427c cabs\.lt\.d \$fcc2,\$f8,\$f19
|
||||
0+016c <[^>]*> 4613407c cabs\.lt\.s \$fcc0,\$f8,\$f19
|
||||
0+0170 <[^>]*> 4613427c cabs\.lt\.s \$fcc2,\$f8,\$f19
|
||||
0+0174 <[^>]*> 46d3407c cabs\.lt\.ps \$fcc0,\$f8,\$f19
|
||||
0+0178 <[^>]*> 46d3427c cabs\.lt\.ps \$fcc2,\$f8,\$f19
|
||||
0+017c <[^>]*> 4633407d cabs\.nge\.d \$fcc0,\$f8,\$f19
|
||||
0+0180 <[^>]*> 4633427d cabs\.nge\.d \$fcc2,\$f8,\$f19
|
||||
0+0184 <[^>]*> 4613407d cabs\.nge\.s \$fcc0,\$f8,\$f19
|
||||
0+0188 <[^>]*> 4613427d cabs\.nge\.s \$fcc2,\$f8,\$f19
|
||||
0+018c <[^>]*> 46d3407d cabs\.nge\.ps \$fcc0,\$f8,\$f19
|
||||
0+0190 <[^>]*> 46d3427d cabs\.nge\.ps \$fcc2,\$f8,\$f19
|
||||
0+0194 <[^>]*> 4633407e cabs\.le\.d \$fcc0,\$f8,\$f19
|
||||
0+0198 <[^>]*> 4633427e cabs\.le\.d \$fcc2,\$f8,\$f19
|
||||
0+019c <[^>]*> 4613407e cabs\.le\.s \$fcc0,\$f8,\$f19
|
||||
0+01a0 <[^>]*> 4613427e cabs\.le\.s \$fcc2,\$f8,\$f19
|
||||
0+01a4 <[^>]*> 46d3407e cabs\.le\.ps \$fcc0,\$f8,\$f19
|
||||
0+01a8 <[^>]*> 46d3427e cabs\.le\.ps \$fcc2,\$f8,\$f19
|
||||
0+01ac <[^>]*> 4633407f cabs\.ngt\.d \$fcc0,\$f8,\$f19
|
||||
0+01b0 <[^>]*> 4633427f cabs\.ngt\.d \$fcc2,\$f8,\$f19
|
||||
0+01b4 <[^>]*> 4613407f cabs\.ngt\.s \$fcc0,\$f8,\$f19
|
||||
0+01b8 <[^>]*> 4613427f cabs\.ngt\.s \$fcc2,\$f8,\$f19
|
||||
0+01bc <[^>]*> 46d3407f cabs\.ngt\.ps \$fcc0,\$f8,\$f19
|
||||
0+01c0 <[^>]*> 46d3427f cabs\.ngt\.ps \$fcc2,\$f8,\$f19
|
||||
0+01c4 <[^>]*> 46c09924 cvt\.pw\.ps \$f4,\$f19
|
||||
0+01c8 <[^>]*> 46809926 cvt\.ps\.pw \$f4,\$f19
|
||||
0+01cc <[^>]*> 46d3411a mulr\.ps \$f4,\$f8,\$f19
|
||||
0+01d0 <[^>]*> 46209a1d recip1\.d \$f8,\$f19
|
||||
0+01d4 <[^>]*> 46009a1d recip1\.s \$f8,\$f19
|
||||
0+01d8 <[^>]*> 46c09a1d recip1\.ps \$f8,\$f19
|
||||
0+01dc <[^>]*> 4633411c recip2\.d \$f4,\$f8,\$f19
|
||||
0+01e0 <[^>]*> 4613411c recip2\.s \$f4,\$f8,\$f19
|
||||
0+01e4 <[^>]*> 46d3411c recip2\.ps \$f4,\$f8,\$f19
|
||||
0+01e8 <[^>]*> 46209a1e rsqrt1\.d \$f8,\$f19
|
||||
0+01ec <[^>]*> 46009a1e rsqrt1\.s \$f8,\$f19
|
||||
0+01f0 <[^>]*> 46c09a1e rsqrt1\.ps \$f8,\$f19
|
||||
0+01f4 <[^>]*> 4633411f rsqrt2\.d \$f4,\$f8,\$f19
|
||||
0+01f8 <[^>]*> 4613411f rsqrt2\.s \$f4,\$f8,\$f19
|
||||
0+01fc <[^>]*> 46d3411f rsqrt2\.ps \$f4,\$f8,\$f19
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
# source file to test assembly of mips64 MIPS-3D ASE instructions
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.globl text_label .text
|
||||
text_label:
|
||||
|
||||
addr.ps $f4, $f8, $f19
|
||||
|
||||
bc1any2f $fcc0, text_label
|
||||
nop
|
||||
bc1any2f $fcc2, text_label
|
||||
nop
|
||||
|
||||
bc1any2t $fcc0, text_label
|
||||
nop
|
||||
bc1any2t $fcc4, text_label
|
||||
nop
|
||||
|
||||
bc1any4f $fcc0, text_label
|
||||
nop
|
||||
bc1any4f $fcc4, text_label
|
||||
nop
|
||||
|
||||
bc1any4t $fcc0, text_label
|
||||
nop
|
||||
bc1any4t $fcc4, text_label
|
||||
nop
|
||||
|
||||
cabs.f.d $fcc0, $f8, $f19
|
||||
cabs.f.d $fcc2, $f8, $f19
|
||||
cabs.f.s $fcc0, $f8, $f19
|
||||
cabs.f.s $fcc2, $f8, $f19
|
||||
cabs.f.ps $fcc0, $f8, $f19
|
||||
cabs.f.ps $fcc2, $f8, $f19
|
||||
cabs.un.d $fcc0, $f8, $f19
|
||||
cabs.un.d $fcc2, $f8, $f19
|
||||
cabs.un.s $fcc0, $f8, $f19
|
||||
cabs.un.s $fcc2, $f8, $f19
|
||||
cabs.un.ps $fcc0, $f8, $f19
|
||||
cabs.un.ps $fcc2, $f8, $f19
|
||||
cabs.eq.d $fcc0, $f8, $f19
|
||||
cabs.eq.d $fcc2, $f8, $f19
|
||||
cabs.eq.s $fcc0, $f8, $f19
|
||||
cabs.eq.s $fcc2, $f8, $f19
|
||||
cabs.eq.ps $fcc0, $f8, $f19
|
||||
cabs.eq.ps $fcc2, $f8, $f19
|
||||
cabs.ueq.d $fcc0, $f8, $f19
|
||||
cabs.ueq.d $fcc2, $f8, $f19
|
||||
cabs.ueq.s $fcc0, $f8, $f19
|
||||
cabs.ueq.s $fcc2, $f8, $f19
|
||||
cabs.ueq.ps $fcc0, $f8, $f19
|
||||
cabs.ueq.ps $fcc2, $f8, $f19
|
||||
cabs.olt.d $fcc0, $f8, $f19
|
||||
cabs.olt.d $fcc2, $f8, $f19
|
||||
cabs.olt.s $fcc0, $f8, $f19
|
||||
cabs.olt.s $fcc2, $f8, $f19
|
||||
cabs.olt.ps $fcc0, $f8, $f19
|
||||
cabs.olt.ps $fcc2, $f8, $f19
|
||||
cabs.ult.d $fcc0, $f8, $f19
|
||||
cabs.ult.d $fcc2, $f8, $f19
|
||||
cabs.ult.s $fcc0, $f8, $f19
|
||||
cabs.ult.s $fcc2, $f8, $f19
|
||||
cabs.ult.ps $fcc0, $f8, $f19
|
||||
cabs.ult.ps $fcc2, $f8, $f19
|
||||
cabs.ole.d $fcc0, $f8, $f19
|
||||
cabs.ole.d $fcc2, $f8, $f19
|
||||
cabs.ole.s $fcc0, $f8, $f19
|
||||
cabs.ole.s $fcc2, $f8, $f19
|
||||
cabs.ole.ps $fcc0, $f8, $f19
|
||||
cabs.ole.ps $fcc2, $f8, $f19
|
||||
cabs.ule.d $fcc0, $f8, $f19
|
||||
cabs.ule.d $fcc2, $f8, $f19
|
||||
cabs.ule.s $fcc0, $f8, $f19
|
||||
cabs.ule.s $fcc2, $f8, $f19
|
||||
cabs.ule.ps $fcc0, $f8, $f19
|
||||
cabs.ule.ps $fcc2, $f8, $f19
|
||||
cabs.sf.d $fcc0, $f8, $f19
|
||||
cabs.sf.d $fcc2, $f8, $f19
|
||||
cabs.sf.s $fcc0, $f8, $f19
|
||||
cabs.sf.s $fcc2, $f8, $f19
|
||||
cabs.sf.ps $fcc0, $f8, $f19
|
||||
cabs.sf.ps $fcc2, $f8, $f19
|
||||
cabs.ngle.d $fcc0, $f8, $f19
|
||||
cabs.ngle.d $fcc2, $f8, $f19
|
||||
cabs.ngle.s $fcc0, $f8, $f19
|
||||
cabs.ngle.s $fcc2, $f8, $f19
|
||||
cabs.ngle.ps $fcc0, $f8, $f19
|
||||
cabs.ngle.ps $fcc2, $f8, $f19
|
||||
cabs.seq.d $fcc0, $f8, $f19
|
||||
cabs.seq.d $fcc2, $f8, $f19
|
||||
cabs.seq.s $fcc0, $f8, $f19
|
||||
cabs.seq.s $fcc2, $f8, $f19
|
||||
cabs.seq.ps $fcc0, $f8, $f19
|
||||
cabs.seq.ps $fcc2, $f8, $f19
|
||||
cabs.ngl.d $fcc0, $f8, $f19
|
||||
cabs.ngl.d $fcc2, $f8, $f19
|
||||
cabs.ngl.s $fcc0, $f8, $f19
|
||||
cabs.ngl.s $fcc2, $f8, $f19
|
||||
cabs.ngl.ps $fcc0, $f8, $f19
|
||||
cabs.ngl.ps $fcc2, $f8, $f19
|
||||
cabs.lt.d $fcc0, $f8, $f19
|
||||
cabs.lt.d $fcc2, $f8, $f19
|
||||
cabs.lt.s $fcc0, $f8, $f19
|
||||
cabs.lt.s $fcc2, $f8, $f19
|
||||
cabs.lt.ps $fcc0, $f8, $f19
|
||||
cabs.lt.ps $fcc2, $f8, $f19
|
||||
cabs.nge.d $fcc0, $f8, $f19
|
||||
cabs.nge.d $fcc2, $f8, $f19
|
||||
cabs.nge.s $fcc0, $f8, $f19
|
||||
cabs.nge.s $fcc2, $f8, $f19
|
||||
cabs.nge.ps $fcc0, $f8, $f19
|
||||
cabs.nge.ps $fcc2, $f8, $f19
|
||||
cabs.le.d $fcc0, $f8, $f19
|
||||
cabs.le.d $fcc2, $f8, $f19
|
||||
cabs.le.s $fcc0, $f8, $f19
|
||||
cabs.le.s $fcc2, $f8, $f19
|
||||
cabs.le.ps $fcc0, $f8, $f19
|
||||
cabs.le.ps $fcc2, $f8, $f19
|
||||
cabs.ngt.d $fcc0, $f8, $f19
|
||||
cabs.ngt.d $fcc2, $f8, $f19
|
||||
cabs.ngt.s $fcc0, $f8, $f19
|
||||
cabs.ngt.s $fcc2, $f8, $f19
|
||||
cabs.ngt.ps $fcc0, $f8, $f19
|
||||
cabs.ngt.ps $fcc2, $f8, $f19
|
||||
|
||||
cvt.pw.ps $f4, $f19
|
||||
|
||||
cvt.ps.pw $f4, $f19
|
||||
|
||||
mulr.ps $f4, $f8, $f19
|
||||
|
||||
recip1.d $f8, $f19
|
||||
recip1.s $f8, $f19
|
||||
recip1.ps $f8, $f19
|
||||
|
||||
recip2.d $f4, $f8, $f19
|
||||
recip2.s $f4, $f8, $f19
|
||||
recip2.ps $f4, $f8, $f19
|
||||
|
||||
rsqrt1.d $f8, $f19
|
||||
rsqrt1.s $f8, $f19
|
||||
rsqrt1.ps $f8, $f19
|
||||
|
||||
rsqrt2.d $f4, $f8, $f19
|
||||
rsqrt2.s $f4, $f8, $f19
|
||||
rsqrt2.ps $f4, $f8, $f19
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
|
|
@ -1,3 +1,10 @@
|
|||
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
|
||||
|
||||
* mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
|
||||
instructions.
|
||||
(OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
|
||||
may be passed along with the ISA bitmask.
|
||||
|
||||
2002-03-05 Paul Koning <pkoning@equallogic.com>
|
||||
|
||||
* pdp11.h: Add format codes for float instruction formats.
|
||||
|
|
|
|||
|
|
@ -316,6 +316,11 @@ struct mips_opcode
|
|||
#define INSN_ISA32 0x00000200
|
||||
#define INSN_ISA64 0x00000400
|
||||
|
||||
/* Masks used for MIPS-defined ASEs. */
|
||||
|
||||
/* MIPS-3D ASE */
|
||||
#define INSN_MIPS3D 0x00004000
|
||||
|
||||
/* Chip specific instructions. These are bitmasks. */
|
||||
|
||||
/* MIPS R4650 instruction. */
|
||||
|
|
@ -367,10 +372,10 @@ struct mips_opcode
|
|||
#define CPU_MIPS64 64
|
||||
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
||||
|
||||
/* Test for membership in an ISA including chip specific ISAs.
|
||||
INSN is pointer to an element of the opcode table; ISA is the
|
||||
specified ISA to test against; and CPU is the CPU specific ISA
|
||||
to test, or zero if no CPU specific ISA test is desired. */
|
||||
/* Test for membership in an ISA including chip specific ISAs. INSN
|
||||
is pointer to an element of the opcode table; ISA is the specified
|
||||
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
||||
test, or zero if no CPU specific ISA test is desired. */
|
||||
|
||||
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
|
||||
(((insn)->membership & isa) != 0 \
|
||||
|
|
|
|||
|
|
@ -1,3 +1,15 @@
|
|||
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
|
||||
|
||||
* mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA
|
||||
bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add
|
||||
comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that
|
||||
indicate that they should dissassemble all applicable
|
||||
MIPS-specified ASEs.
|
||||
* mips-opc.c: Add support for MIPS-3D instructions.
|
||||
(M3D): New definition.
|
||||
|
||||
* mips-opc.c: Update copyright years.
|
||||
|
||||
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
|
||||
|
||||
* mips-opc.c (mips_builtin_opcodes): Sort bc<N> opcodes by name.
|
||||
|
|
|
|||
|
|
@ -373,15 +373,21 @@ mips_isa_type (mach, isa, cputype)
|
|||
break;
|
||||
case bfd_mach_mips_sb1:
|
||||
*cputype = CPU_SB1;
|
||||
*isa = ISA_MIPS64 | INSN_SB1;
|
||||
*isa = ISA_MIPS64 | INSN_MIPS3D | INSN_SB1;
|
||||
break;
|
||||
case bfd_mach_mipsisa32:
|
||||
*cputype = CPU_MIPS32;
|
||||
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
|
||||
Note that MIPS-3D is not applicable to MIPS32. (See _MIPS32
|
||||
Architecture For Programmers Volume I: Introduction to the
|
||||
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
|
||||
page 1. */
|
||||
*isa = ISA_MIPS32;
|
||||
break;
|
||||
case bfd_mach_mipsisa64:
|
||||
*cputype = CPU_MIPS64;
|
||||
*isa = ISA_MIPS64;
|
||||
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
|
||||
*isa = ISA_MIPS64 | INSN_MIPS3D;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
/* mips-opc.c -- MIPS opcode list.
|
||||
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
|
||||
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Ralph Campbell and OSF
|
||||
Commented and modified by Ian Lance Taylor, Cygnus Support
|
||||
Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
|
||||
MIPS-3D support added by Broadcom Corporation (SiByte).
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
|
|
@ -82,6 +83,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
|||
#define I32 INSN_ISA32
|
||||
#define I64 INSN_ISA64
|
||||
|
||||
/* MIPS-3D support. */
|
||||
#define M3D INSN_MIPS3D
|
||||
|
||||
#define P3 INSN_4650
|
||||
#define L1 INSN_4010
|
||||
#define V1 INSN_4100
|
||||
|
|
@ -140,6 +144,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
|
||||
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
|
||||
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
|
|
@ -152,6 +157,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
|
||||
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
|
||||
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
|
||||
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
|
||||
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
|
||||
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
|
||||
{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
|
||||
{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
|
||||
{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
|
||||
{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
|
||||
|
|
@ -324,6 +333,54 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
|
||||
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
|
||||
{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
|
||||
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3},
|
||||
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
|
|
@ -353,7 +410,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
|
||||
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D },
|
||||
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D },
|
||||
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
|
||||
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
|
||||
|
|
@ -623,6 +682,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
|
||||
{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
|
||||
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
|
||||
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
|
||||
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
|
||||
|
|
@ -657,6 +717,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
|
||||
{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
|
||||
{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
|
||||
{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, M3D },
|
||||
{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
|
||||
{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
|
||||
{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
|
||||
{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
|
||||
{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
|
||||
{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
|
||||
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
|
||||
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
|
||||
|
|
@ -675,6 +741,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
|
||||
{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
|
||||
{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
|
||||
{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D },
|
||||
{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
|
||||
{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
|
||||
{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
|
||||
{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
|
||||
{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
|
||||
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
|
||||
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
|
||||
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue