[PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): Add new instructions. (do_t_loloop): Changed to handle tail predication variants. (md_apply_fix): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-tailpredloop-bad.d: New test. * testsuite/gas/arm/mve-tailpredloop-bad.l: New test. * testsuite/gas/arm/mve-tailpredloop-bad.s: New test. * testsuite/gas/arm/mve-tailpredloop.d: New test.
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Andre Vieira
parent
acca563074
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1f6234a335
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@ -1,3 +1,14 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (T16_32_TAB): Add new instructions.
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(do_t_loloop): Changed to handle tail predication variants.
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(md_apply_fix): Likewise.
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(insns): Add entries for MVE mnemonics.
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* testsuite/gas/arm/mve-tailpredloop-bad.d: New test.
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* testsuite/gas/arm/mve-tailpredloop-bad.l: New test.
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* testsuite/gas/arm/mve-tailpredloop-bad.s: New test.
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* testsuite/gas/arm/mve-tailpredloop.d: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vshll): New encoding function.
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@ -11134,9 +11134,11 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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X(_cpy, 4600, ea4f0000), \
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X(_dec_sp,80dd, f1ad0d00), \
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X(_dls, 0000, f040e001), \
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X(_dlstp, 0000, f000e001), \
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X(_eor, 4040, ea800000), \
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X(_eors, 4040, ea900000), \
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X(_inc_sp,00dd, f10d0d00), \
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X(_lctp, 0000, f00fe001), \
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X(_ldmia, c800, e8900000), \
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X(_ldr, 6800, f8500000), \
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X(_ldrb, 7800, f8100000), \
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@ -11147,6 +11149,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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X(_ldr_pc2,4800, f85f0000), \
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X(_ldr_sp,9800, f85d0000), \
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X(_le, 0000, f00fc001), \
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X(_letp, 0000, f01fc001), \
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X(_lsl, 0000, fa00f000), \
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X(_lsls, 0000, fa10f000), \
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X(_lsr, 0800, fa20f000), \
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@ -11189,6 +11192,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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X(_wfe, bf20, f3af8002), \
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X(_wfi, bf30, f3af8003), \
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X(_wls, 0000, f040c001), \
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X(_wlstp, 0000, f000c001), \
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X(_sev, bf40, f3af8004), \
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X(_sevl, bf50, f3af8005), \
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X(_udf, de00, f7f0a000)
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@ -14114,38 +14118,6 @@ v8_1_loop_reloc (int is_le)
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}
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}
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/* To handle the Scalar Low Overhead Loop instructions
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in Armv8.1-M Mainline. */
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static void
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do_t_loloop (void)
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{
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unsigned long insn = inst.instruction;
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set_pred_insn_type (OUTSIDE_PRED_INSN);
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inst.instruction = THUMB_OP32 (inst.instruction);
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switch (insn)
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{
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case T_MNEM_le:
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/* le <label>. */
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if (!inst.operands[0].present)
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inst.instruction |= 1 << 21;
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v8_1_loop_reloc (TRUE);
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break;
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case T_MNEM_wls:
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v8_1_loop_reloc (FALSE);
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/* Fall through. */
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case T_MNEM_dls:
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constraint (inst.operands[1].isreg != 1, BAD_ARGS);
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inst.instruction |= (inst.operands[1].reg << 16);
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break;
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default: abort();
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}
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}
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/* MVE instruction encoder helpers. */
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#define M_MNEM_vabav 0xee800f01
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#define M_MNEM_vmladav 0xeef00e00
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@ -14444,6 +14416,8 @@ NEON_ENC_TAB
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X(2, (R, S), SINGLE), \
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X(2, (F, R), SINGLE), \
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X(2, (R, F), SINGLE), \
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/* Used for MVE tail predicated loop instructions. */\
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X(2, (R, R), QUAD), \
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/* Half float shape supported so far. */\
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X (2, (H, D), MIXED), \
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X (2, (D, H), MIXED), \
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@ -15985,6 +15959,66 @@ do_mve_vcmul (void)
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inst.is_neon = 1;
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}
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/* To handle the Low Overhead Loop instructions
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in Armv8.1-M Mainline and MVE. */
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static void
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do_t_loloop (void)
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{
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unsigned long insn = inst.instruction;
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inst.instruction = THUMB_OP32 (inst.instruction);
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if (insn == T_MNEM_lctp)
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return;
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set_pred_insn_type (MVE_OUTSIDE_PRED_INSN);
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if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
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{
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struct neon_type_el et
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= neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
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inst.instruction |= neon_logbits (et.size) << 20;
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inst.is_neon = 1;
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}
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switch (insn)
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{
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case T_MNEM_letp:
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constraint (!inst.operands[0].present,
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_("expected LR"));
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/* fall through. */
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case T_MNEM_le:
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/* le <label>. */
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if (!inst.operands[0].present)
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inst.instruction |= 1 << 21;
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v8_1_loop_reloc (TRUE);
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break;
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case T_MNEM_wls:
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case T_MNEM_wlstp:
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v8_1_loop_reloc (FALSE);
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/* fall through. */
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case T_MNEM_dlstp:
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case T_MNEM_dls:
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constraint (inst.operands[1].isreg != 1, BAD_ARGS);
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if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
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constraint (inst.operands[1].reg == REG_PC, BAD_PC);
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else if (inst.operands[1].reg == REG_PC)
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as_tsktsk (MVE_BAD_PC);
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if (inst.operands[1].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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inst.instruction |= (inst.operands[1].reg << 16);
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break;
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default:
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abort ();
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}
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}
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static void
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do_vfp_nsyn_cmp (void)
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{
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@ -25240,6 +25274,11 @@ static const struct asm_opcode insns[] =
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mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll),
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mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll),
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toU("dlstp", _dlstp, 2, (LR, RR), t_loloop),
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toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop),
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toU("letp", _letp, 2, (LR, EXP), t_loloop),
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toU("lctp", _lctp, 0, (), t_loloop),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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@ -28641,9 +28680,10 @@ md_apply_fix (fixS * fixP,
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}
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bfd_vma insn = get_thumb32_insn (buf);
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/* le lr, <label> or le <label> */
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/* le lr, <label>, le <label> or letp lr, <label> */
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if (((insn & 0xffffffff) == 0xf00fc001)
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|| ((insn & 0xffffffff) == 0xf02fc001))
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|| ((insn & 0xffffffff) == 0xf02fc001)
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|| ((insn & 0xffffffff) == 0xf01fc001))
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value = -value;
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if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
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@ -0,0 +1,5 @@
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#name: bad MVE WLSTP, DLSTP and LETP instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-tailpredloop-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,26 @@
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[^:]*: Assembler messages:
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Error: r15 not allowed here -- `wlstp.8 lr,pc,.label'
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[^:]*:29: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:30: Error: r15 not allowed here -- `dlstp.16 lr,pc'
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[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:33: Error: ARM register expected -- `letp .label_back'
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[^:]*:34: Error: branch out of range or not a multiple of 2
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[^:]*:35: Error: branch out of range or not a multiple of 2
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@ -0,0 +1,36 @@
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.macro cond1
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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wlstp.8 lr, r0, .label
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.endr
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.endm
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.macro cond2
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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dlstp.8 lr, r0
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.endr
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.endm
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.macro cond3
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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letp lr, .label_back
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.endr
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.endm
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.label_back:
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.syntax unified
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.thumb
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cond1
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cond2
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cond3
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wlstp.8 lr, pc, .label
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wlstp.8 lr, sp, .label
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dlstp.16 lr, pc
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dlstp.16 lr, sp
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.label:
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letp .label_back
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wlstp.8 lr, r0, .label
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letp lr, .label2
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.label2:
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