Sync up x86-gcc-cpuid.h with cpuid.h from gcc-6 branch.
Pedro suggested a separate patch synching with GCCs cpuid.h
instead of just adding new bits for PKU feature.
gdb/Changelog:
2016-11-14 Michael Sturm <michael.sturm@intel.com>
* nat/x86-gcc-cpuid.h: Replace with copy of cpuid.h
from gcc-6 branch.
Change-Id: I16f8f7f2d0aa7c2e815701d15ed831a6c6b33d21
Signed-off-by: Michael Sturm <michael.sturm@intel.com>
This commit is contained in:
Michael Sturm
parent
262a40a540
commit
1f85ef5042
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@ -1,5 +1,5 @@
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/*
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* Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not
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* Helper cpuid.h file copied from gcc-6.0.0. Code in gdb should not
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* include this directly, but pull in x86-cpuid.h and use that func.
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*/
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/*
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@ -61,31 +61,56 @@
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#define bit_LWP (1 << 15)
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#define bit_FMA4 (1 << 16)
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#define bit_TBM (1 << 21)
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#define bit_MWAITX (1 << 29)
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/* %edx */
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#define bit_AVX5124VNNIW (1 << 2)
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#define bit_AVX5124FMAPS (1 << 3)
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#define bit_MMXEXT (1 << 22)
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#define bit_LM (1 << 29)
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#define bit_3DNOWP (1 << 30)
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#define bit_3DNOW (1 << 31)
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/* %ebx. */
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#define bit_CLZERO (1 << 0)
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/* Extended Features (%eax == 7) */
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/* %ebx */
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#define bit_FSGSBASE (1 << 0)
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#define bit_BMI (1 << 3)
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#define bit_HLE (1 << 4)
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#define bit_AVX2 (1 << 5)
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#define bit_BMI2 (1 << 8)
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#define bit_RTM (1 << 11)
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#define bit_MPX (1 << 14)
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#define bit_AVX512F (1 << 16)
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#define bit_MPX (1 << 14)
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#define bit_AVX512DQ (1 << 17)
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#define bit_RDSEED (1 << 18)
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#define bit_ADX (1 << 19)
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#define bit_AVX512IFMA (1 << 21)
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#define bit_CLFLUSHOPT (1 << 23)
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#define bit_CLWB (1 << 24)
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#define bit_AVX512PF (1 << 26)
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#define bit_AVX512ER (1 << 27)
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#define bit_AVX512CD (1 << 28)
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#define bit_SHA (1 << 29)
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#define bit_AVX512BW (1 << 30)
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#define bit_AVX512VL (1 << 31)
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/* %ecx */
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#define bit_PREFETCHWT1 (1 << 0)
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#define bit_AVX512VBMI (1 << 1)
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#define bit_PKU (1 << 3)
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#define bit_OSPKE (1 << 4)
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/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
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#define bit_BNDREGS (1 << 3)
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#define bit_BNDCSR (1 << 4)
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/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
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#define bit_XSAVEOPT (1 << 0)
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#define bit_XSAVEC (1 << 1)
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#define bit_XSAVES (1 << 3)
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/* Signatures for different CPU implementations as returned in uses
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of cpuid with level 0. */
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@ -141,55 +166,6 @@
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#define signature_VORTEX_ecx 0x436f5320
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#define signature_VORTEX_edx 0x36387865
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#if defined(__i386__) && defined(__PIC__)
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/* %ebx may be the PIC register. */
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#if __GNUC__ >= 3
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchg{l}\t{%%}ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchg{l}\t{%%}ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#else
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/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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nor alternatives in i386 code. */
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("xchgl\t%%ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchgl\t%%ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#endif
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#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
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/* %rbx may be the PIC register. */
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
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"cpuid\n\t" \
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"xchg{q}\t{%%}rbx, %q1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
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"cpuid\n\t" \
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"xchg{q}\t{%%}rbx, %q1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#else
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("cpuid\n\t" \
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: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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@ -199,7 +175,7 @@
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__asm__ ("cpuid\n\t" \
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: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#endif
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/* Return highest supported input value for cpuid instruction. ext can
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be either 0x0 or 0x8000000 to return highest supported value for
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@ -258,21 +234,37 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
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return __eax;
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}
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/* Return cpuid data for requested cpuid level, as found in returned
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/* Return cpuid data for requested cpuid leaf, as found in returned
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eax, ebx, ecx and edx registers. The function checks if cpuid is
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supported and returns 1 for valid cpuid information or 0 for
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unsupported cpuid level. All pointers are required to be non-null. */
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unsupported cpuid leaf. All pointers are required to be non-null. */
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static __inline int
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__get_cpuid (unsigned int __level,
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__get_cpuid (unsigned int __leaf,
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unsigned int *__eax, unsigned int *__ebx,
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unsigned int *__ecx, unsigned int *__edx)
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{
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unsigned int __ext = __level & 0x80000000;
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unsigned int __ext = __leaf & 0x80000000;
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if (__get_cpuid_max (__ext, 0) < __level)
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if (__get_cpuid_max (__ext, 0) < __leaf)
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return 0;
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__cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
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__cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
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return 1;
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}
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/* Same as above, but sub-leaf can be specified. */
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static __inline int
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__get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
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unsigned int *__eax, unsigned int *__ebx,
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unsigned int *__ecx, unsigned int *__edx)
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{
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unsigned int __ext = __leaf & 0x80000000;
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if (__get_cpuid_max (__ext, 0) < __leaf)
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return 0;
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__cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
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return 1;
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}
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