[ppc64] Add POWER8/ISA 2.07 atomic sequences single-stepping support
gdb/ 2017-02-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com> * rs6000-tdep.c (LOAD_AND_RESERVE_MASK): Rename from LWARX_MASK. (STORE_CONDITIONAL_MASK): Rename from STWCX_MASK. (LBARX_INSTRUCTION, LHARX_INSTRUCTION, LQARX_INSTRUCTION, STBCX_INSTRUCTION, STHCX_INSTRUCTION, STQCX_INSTRUCTION): New defines. (IS_LOAD_AND_RESERVE_INSN, IS_STORE_CONDITIONAL_INSN): New macros. (ppc_displaced_step_copy_insn): Use IS_LOAD_AND_RESERVE_INSN. (ppc_deal_with_atomic_sequence): Use IS_LOAD_AND_RESERVE_INSN and IS_STORE_CONDITIONAL_INSN. gdb/testsuite/ 2017-02-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com> * gdb.arch/ppc64-isa207-atomic-inst.exp: New testcase based on gdb.arch/ppc64-atomic-inst.exp. Add tests for lbarx/stbcx, lharx/sthcx and lqarx/stqcx. * gdb.arch/ppc64-isa207-atomic-inst.S: New file. * gdb.arch/ppc64-isa207-atomic-inst.c: Likewise.
This commit is contained in:
Edjunior Barbosa Machado
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a51d7ecf3d
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2039d74e78
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@ -1,3 +1,14 @@
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2017-02-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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* rs6000-tdep.c (LOAD_AND_RESERVE_MASK): Rename from LWARX_MASK.
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(STORE_CONDITIONAL_MASK): Rename from STWCX_MASK.
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(LBARX_INSTRUCTION, LHARX_INSTRUCTION, LQARX_INSTRUCTION,
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STBCX_INSTRUCTION, STHCX_INSTRUCTION, STQCX_INSTRUCTION): New defines.
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(IS_LOAD_AND_RESERVE_INSN, IS_STORE_CONDITIONAL_INSN): New macros.
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(ppc_displaced_step_copy_insn): Use IS_LOAD_AND_RESERVE_INSN.
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(ppc_deal_with_atomic_sequence): Use IS_LOAD_AND_RESERVE_INSN and
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IS_STORE_CONDITIONAL_INSN.
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2017-02-21 Jan Kratochvil <jan.kratochvil@redhat.com>
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* dwarf2_rnglists_process: Initialize range_beginning and range_end.
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@ -983,12 +983,33 @@ typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint)
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/* Instruction masks used during single-stepping of atomic
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sequences. */
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#define LWARX_MASK 0xfc0007fe
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#define LOAD_AND_RESERVE_MASK 0xfc0007fe
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#define LWARX_INSTRUCTION 0x7c000028
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#define LDARX_INSTRUCTION 0x7c0000A8
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#define STWCX_MASK 0xfc0007ff
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#define LBARX_INSTRUCTION 0x7c000068
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#define LHARX_INSTRUCTION 0x7c0000e8
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#define LQARX_INSTRUCTION 0x7c000228
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#define STORE_CONDITIONAL_MASK 0xfc0007ff
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#define STWCX_INSTRUCTION 0x7c00012d
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#define STDCX_INSTRUCTION 0x7c0001ad
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#define STBCX_INSTRUCTION 0x7c00056d
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#define STHCX_INSTRUCTION 0x7c0005ad
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#define STQCX_INSTRUCTION 0x7c00016d
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/* Check if insn is one of the Load And Reserve instructions used for atomic
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sequences. */
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#define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
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|| (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
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|| (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
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|| (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
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|| (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
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/* Check if insn is one of the Store Conditional instructions used for atomic
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sequences. */
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#define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
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|| (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
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|| (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
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|| (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
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|| (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
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/* We can't displaced step atomic sequences. Otherwise this is just
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like simple_displaced_step_copy_insn. */
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@ -1008,9 +1029,8 @@ ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
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insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order);
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/* Assume all atomic sequences start with a lwarx/ldarx instruction. */
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if ((insn & LWARX_MASK) == LWARX_INSTRUCTION
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|| (insn & LWARX_MASK) == LDARX_INSTRUCTION)
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/* Assume all atomic sequences start with a Load and Reserve instruction. */
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if (IS_LOAD_AND_RESERVE_INSN (insn))
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{
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if (debug_displaced)
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{
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@ -1138,11 +1158,10 @@ ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
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return 1;
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}
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/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
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instruction and ending with a STWCX/STDCX instruction. If such a sequence
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is found, attempt to step through it. A breakpoint is placed at the end of
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the sequence. */
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/* Checks for an atomic sequence of instructions beginning with a
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Load And Reserve instruction and ending with a Store Conditional
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instruction. If such a sequence is found, attempt to step through it.
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A breakpoint is placed at the end of the sequence. */
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VEC (CORE_ADDR) *
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ppc_deal_with_atomic_sequence (struct regcache *regcache)
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{
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@ -1160,9 +1179,8 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
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int bc_insn_count = 0; /* Conditional branch instruction count. */
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VEC (CORE_ADDR) *next_pcs = NULL;
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/* Assume all atomic sequences start with a lwarx/ldarx instruction. */
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if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
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&& (insn & LWARX_MASK) != LDARX_INSTRUCTION)
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/* Assume all atomic sequences start with a Load And Reserve instruction. */
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if (!IS_LOAD_AND_RESERVE_INSN (insn))
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return NULL;
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/* Assume that no atomic sequence is longer than "atomic_sequence_length"
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@ -1193,14 +1211,13 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
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last_breakpoint++;
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}
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if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
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|| (insn & STWCX_MASK) == STDCX_INSTRUCTION)
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if (IS_STORE_CONDITIONAL_INSN (insn))
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break;
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}
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/* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
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if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
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&& (insn & STWCX_MASK) != STDCX_INSTRUCTION)
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/* Assume that the atomic sequence ends with a Store Conditional
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instruction. */
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if (!IS_STORE_CONDITIONAL_INSN (insn))
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return NULL;
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closing_insn = loc;
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@ -1,3 +1,11 @@
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2017-02-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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* gdb.arch/ppc64-isa207-atomic-inst.exp: New testcase based on
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gdb.arch/ppc64-atomic-inst.exp. Add tests for lbarx/stbcx, lharx/sthcx
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and lqarx/stqcx.
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* gdb.arch/ppc64-isa207-atomic-inst.S: New file.
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* gdb.arch/ppc64-isa207-atomic-inst.c: Likewise.
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2017-02-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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* gdb.arch/ppc64-atomic-inst.exp: Fix test names starting with
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@ -0,0 +1,100 @@
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/* This file is part of GDB, the GNU debugger.
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Copyright 2017 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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.align 2
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.globl test_atomic_sequences
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#if _CALL_ELF == 2
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.type test_atomic_sequences,@function
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test_atomic_sequences:
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#else
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.section ".opd","aw"
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.align 3
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test_atomic_sequences:
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.quad .test_atomic_sequences,.TOC.@tocbase,0
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.size test_atomic_sequences,.-test_atomic_sequences
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.previous
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.globl .test_atomic_sequences
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.type .test_atomic_sequences,@function
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.test_atomic_sequences:
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#endif
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li 0,0
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addi 4,1,-8
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stb 0,0(4)
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1: lbarx 5,0,4
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cmpdi 5,0
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bne 2f
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addi 5,5,1
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stbcx. 5,0,4
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bne 1b
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sth 0,0(4)
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2: lharx 5,0,4
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cmpdi 5,0
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bne 3f
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addi 5,5,1
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sthcx. 5,0,4
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bne 2b
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#ifdef __BIG_ENDIAN__
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li 10,0
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li 6,0
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li 7,1
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std 10,-16(1)
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li 10,1
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std 10,-8(1)
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addi 4,1,-16
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#else
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std 9,40(1)
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li 9,1
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addi 4,1,32
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std 9,32(1)
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mr 8,9
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ld 3,8(4)
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#endif
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3: lqarx 10,0,4
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#ifdef __BIG_ENDIAN__
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li 8,0
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li 9,2
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mr 5,10
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xor 10,11,7
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xor 5,5,6
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or. 4,5,10
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bne 4f
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addi 10,1,-16
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stqcx. 8,0,10
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#else
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xor 9,11,8
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mr 6,11
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xor 11,10,3
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or. 0,9,11
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bne 4f
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li 14,0
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li 15,2
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stqcx. 14,0,4
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#endif
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bne 3b
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4: li 3,0
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blr
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#if _CALL_ELF == 2
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.size test_atomic_sequences,.-test_atomic_sequences
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#else
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.size .test_atomic_sequences,.-.test_atomic_sequences
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#endif
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@ -0,0 +1,42 @@
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/* Copyright 2017 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <elf.h>
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typedef Elf64_auxv_t auxv_t;
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#ifndef PPC_FEATURE2_ARCH_2_07
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#define PPC_FEATURE2_ARCH_2_07 0x80000000
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#endif
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extern void test_atomic_sequences (void);
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int
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main (int argc, char *argv[], char *envp[], auxv_t auxv[])
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{
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int i;
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for (i = 0; auxv[i].a_type != AT_NULL; i++)
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if (auxv[i].a_type == AT_HWCAP2) {
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if (!(auxv[i].a_un.a_val & PPC_FEATURE2_ARCH_2_07))
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return 1;
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break;
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}
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test_atomic_sequences ();
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return 0;
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}
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@ -0,0 +1,99 @@
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# Copyright 2017 Free Software Foundation, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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#
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# This file is part of the gdb testsuite.
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# Test single stepping through POWER8/ISA 2.07 atomic sequences beginning with
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# a lbarx/lharx/lqarx instruction and ending with a stbcx/sthcx/stqxc
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# instruction. Note that although lbarx, lharx, stbcx and sthcx instructions
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# were introduced in ISA 2.06, they were implemented only in POWER8 (ISA 2.07).
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if {![istarget "powerpc*"] || ![is_lp64_target]} {
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untested "skipping powerpc isa 207 atomic sequences test"
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return
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}
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standard_testfile .c .S
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if { [prepare_for_testing "failed to prepare" $testfile "$srcfile $srcfile2" \
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{debug quiet}] } {
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return -1
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}
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# The test proper. DISPLACED is true if we should try with displaced
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# stepping.
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proc do_test { displaced } {
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global decimal hex
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global gdb_prompt inferior_exited_re srcfile srcfile2
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if ![runto_main] then {
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untested "could not run to main"
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return -1
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}
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gdb_test_no_output "set displaced-stepping $displaced"
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gdb_breakpoint "test_atomic_sequences" "Breakpoint $decimal at $hex" \
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"set the breakpoint at the start of the test function"
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gdb_test_multiple "continue" "Continue until lbarx/stbcx start breakpoint" {
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-re "$inferior_exited_re with code 01.\[\r\n\]+$gdb_prompt $" {
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unsupported "POWER8/ISA 2.07 atomic instructions not supported."
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return -1
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}
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-re "Continuing.*Breakpoint $decimal.*$gdb_prompt $" {
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pass "continue until test_atomic_sequences function"
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}
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}
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set bp1 [gdb_get_line_number "lbarx" "$srcfile2"]
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gdb_breakpoint "$bp1" "Breakpoint $decimal at $hex" \
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"set the breakpoint at the start of the lbarx/stbcx sequence"
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set bp2 [gdb_get_line_number "lharx" "$srcfile2"]
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gdb_breakpoint "$bp2" "Breakpoint $decimal at $hex" \
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"set the breakpoint at the start of the lharx/sthcx sequence"
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set bp3 [gdb_get_line_number "lqarx" "$srcfile2"]
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gdb_breakpoint "$bp3" "Breakpoint $decimal at $hex" \
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"set the breakpoint at the start of the lqarx/stqcx sequence"
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gdb_test continue "Continuing.*Breakpoint $decimal.*" \
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"continue until lbarx/stbcx start breakpoint"
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gdb_test nexti "bne.*1b" \
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"step through the lbarx/stbcx sequence"
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gdb_test continue "Continuing.*Breakpoint $decimal.*" \
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"continue until lharx/sthcx start breakpoint"
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gdb_test nexti "bne.*2b" \
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"step through the lharx/sthcx sequence"
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gdb_test continue "Continuing.*Breakpoint $decimal.*" \
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"continue until ldqrx/stqcx start breakpoint"
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gdb_test nexti "bne.*3b" \
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"step through the lqarx/stqcx sequence"
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}
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foreach displaced { "off" "on" } {
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with_test_prefix "displaced=$displaced" {
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do_test $displaced
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}
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}
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