* simops.c: Fix simulation of division instructions.
Fix typos/thinkos in several "cmp" and "sub" instructions. Another couple dozen c-torture failures fixed.
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@ -1320,7 +1320,7 @@ void OP_FCC40000 ()
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int z, c, n, v;
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int z, c, n, v;
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unsigned long reg1, imm, value;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
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reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
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imm = ((insn & 0xffff) << 16) | extension;
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 - imm;
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value = reg1 - imm;
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@ -1333,7 +1333,7 @@ void OP_FCC40000 ()
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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State.regs[REG_D0 + ((insn & 0x300) >> 16)] = value;
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
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}
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}
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/* sub imm32, an */
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/* sub imm32, an */
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@ -1342,7 +1342,7 @@ void OP_FCD40000 ()
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int z, c, n, v;
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int z, c, n, v;
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unsigned long reg1, imm, value;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
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reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
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imm = ((insn & 0xffff) << 16) | extension;
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 - imm;
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value = reg1 - imm;
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@ -1355,7 +1355,7 @@ void OP_FCD40000 ()
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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State.regs[REG_A0 + ((insn & 0x300) >> 16)] = value;
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
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}
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}
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/* subc dm, dn */
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/* subc dm, dn */
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@ -1423,8 +1423,6 @@ void OP_F260 ()
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temp |= State.regs[REG_D0 + (insn & 0x3)];
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temp |= State.regs[REG_D0 + (insn & 0x3)];
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State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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temp = (State.regs[REG_D0 + (insn & 0x3)]
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* State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
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State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
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State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
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State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
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State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
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z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
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z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
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@ -1444,8 +1442,6 @@ void OP_F270 ()
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temp |= State.regs[REG_D0 + (insn & 0x3)];
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temp |= State.regs[REG_D0 + (insn & 0x3)];
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State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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temp = (State.regs[REG_D0 + (insn & 0x3)]
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* State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
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State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
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State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
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State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
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State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
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z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
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z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
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@ -1604,7 +1600,7 @@ void OP_FAC80000 ()
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int z, c, n, v;
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int z, c, n, v;
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unsigned long reg1, imm, value;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
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reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
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imm = SEXT16 (insn & 0xffff);
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imm = SEXT16 (insn & 0xffff);
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value = reg1 - imm;
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value = reg1 - imm;
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@ -1625,7 +1621,7 @@ void OP_FCC80000 ()
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int z, c, n, v;
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int z, c, n, v;
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unsigned long reg1, imm, value;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
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reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
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imm = ((insn & 0xffff) << 16) | extension;
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 - imm;
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value = reg1 - imm;
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@ -1646,7 +1642,7 @@ void OP_FAD80000 ()
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int z, c, n, v;
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int z, c, n, v;
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unsigned long reg1, imm, value;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
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reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
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imm = insn & 0xffff;
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imm = insn & 0xffff;
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value = reg1 - imm;
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value = reg1 - imm;
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@ -1667,7 +1663,7 @@ void OP_FCD80000 ()
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int z, c, n, v;
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int z, c, n, v;
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unsigned long reg1, imm, value;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
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reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
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imm = ((insn & 0xffff) << 16) | extension;
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 - imm;
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value = reg1 - imm;
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