Fix generation of AArhc64 instruction table.
* aarch64-gen.c (VERIFIER): Define. * aarch64-opc.c (VERIFIER): Define. (verify_ldpsw): Use static linkage. * aarch64-opc.h (verify_ldpsw): Remove. * aarch64-tbl.h: Use VERIFIER for verifiers.
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@ -1,3 +1,11 @@
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2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-gen.c (VERIFIER): Define.
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* aarch64-opc.c (VERIFIER): Define.
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(verify_ldpsw): Use static linkage.
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* aarch64-opc.h (verify_ldpsw): Remove.
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* aarch64-tbl.h: Use VERIFIER for verifiers.
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2016-04-28 Nick Clifton <nickc@redhat.com>
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PR target/19722
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@ -28,6 +28,7 @@
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#include "getopt.h"
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#include "opcode/aarch64.h"
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#define VERIFIER(x) NULL
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#include "aarch64-tbl.h"
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static int debug = 0;
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@ -3420,7 +3420,7 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
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#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
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#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
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bfd_boolean
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static bfd_boolean
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verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
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const aarch64_insn insn)
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{
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@ -3447,4 +3447,5 @@ verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
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/* Include the opcode description table as well as the operand description
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table. */
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#define VERIFIER(x) verify_##x
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#include "aarch64-tbl.h"
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@ -390,7 +390,4 @@ get_logsz (unsigned int size)
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return ls[size - 1];
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}
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/* Instruction Verifiers. */
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extern bfd_boolean verify_ldpsw (const struct aarch64_opcode *, const aarch64_insn);
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#endif /* OPCODES_AARCH64_OPC_H */
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@ -21,6 +21,10 @@
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#include "aarch64-opc.h"
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#ifndef VERIFIER
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#error VERIFIER must be defined.
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#endif
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/* Operand type. */
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#define OPND(x) AARCH64_OPND_##x
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@ -2383,13 +2387,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
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CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
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CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
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{"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, verify_ldpsw},
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{"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)},
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/* Load/store register pair (indexed). */
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CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
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CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
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CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
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CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
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{"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, verify_ldpsw},
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{"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)},
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/* Load register (literal). */
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{"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q, NULL},
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{"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0, NULL},
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