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Add support for MIPS R6 evp and dvp instructions.

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opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

gas/testsuite/
	* gas/mips/r6.s: Add evp and dvp instructions.
	* gas/mips/r6.d: Likewise.
	* gas/mips/r6-n32.d: Likewise.
	* gas/mips/r6-n64.d: Likewise.
This commit is contained in:
Andrew Bennett 2015-03-13 22:02:16 +00:00
parent 61a12cfa7b
commit 21e20815a2
7 changed files with 32 additions and 0 deletions
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7
gas/testsuite/ChangeLog
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@ -1,3 +1,10 @@
2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
* gas/mips/r6.s: Add evp and dvp instructions.
* gas/mips/r6.d: Likewise.
* gas/mips/r6-n32.d: Likewise.
* gas/mips/r6-n64.d: Likewise.
2015-03-13 Jiong Wang <jiong.wang@arm.com>
* gas/aarch64/diagnostic.s: New testcases.

4
gas/testsuite/gas/mips/r6-n32.d
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@ -493,4 +493,8 @@ Disassembly of section .text:
0+0588 <[^>]*> f8040000 jalrc a0
0+058c <[^>]*> 04100000 nal
0+0590 <[^>]*> 00000000 nop
0+0594 <[^>]*> 41600004 evp
0+0598 <[^>]*> 41600024 dvp
0+059c <[^>]*> 41620004 evp v0
0+05a0 <[^>]*> 41620024 dvp v0
\.\.\.

4
gas/testsuite/gas/mips/r6-n64.d
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@ -749,4 +749,8 @@ Disassembly of section .text:
0+0588 <[^>]*> f8040000 jalrc a0
0+058c <[^>]*> 04100000 nal
0+0590 <[^>]*> 00000000 nop
0+0594 <[^>]*> 41600004 evp
0+0598 <[^>]*> 41600024 dvp
0+059c <[^>]*> 41620004 evp v0
0+05a0 <[^>]*> 41620024 dvp v0
\.\.\.

4
gas/testsuite/gas/mips/r6.d
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@ -492,4 +492,8 @@ Disassembly of section .text:
0+0588 <[^>]*> f8040000 jalrc a0
0+058c <[^>]*> 04100000 nal
0+0590 <[^>]*> 00000000 nop
0+0594 <[^>]*> 41600004 evp
0+0598 <[^>]*> 41600024 dvp
0+059c <[^>]*> 41620004 evp v0
0+05a0 <[^>]*> 41620024 dvp v0
\.\.\.

5
gas/testsuite/gas/mips/r6.s
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@ -261,6 +261,11 @@ new: maddf.s $f0,$f1,$f2
jalrc $4
nal
evp
dvp
evp $2
dvp $2
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add new IBM z13 instructions.

4
opcodes/mips-opc.c
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@ -1147,6 +1147,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"dvpe", "t", 0x41600001, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I37, 0, 0 },
{"dvp", "t", 0x41600024, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 },
{"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 },
{"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 },
{"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 },
@ -1156,6 +1158,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 },
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I37, 0, 0 },
{"evp", "t", 0x41600004, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 },
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 },
{"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
{"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */