x86: CET v2.0: Update incssp and setssbsy

Update x86 assembler and disassembler for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf 1. incsspd and incsspq are changed to take a register opeand with a different opcode. 2. setssbsy is changed to take no opeand with a different opcode. gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (RM_0FAE_REG_5): Removed. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_0): New. (PREFIX_MOD_3_0FAE_REG_5): Likewise. (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add PREFIX_MOD_3_0F01_REG_5_RM_0. (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add PREFIX_MOD_3_0FAE_REG_5. (mod_table): Update MOD_0FAE_REG_5. (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. * i386-opc.tbl: Update incsspd, incsspq and setssbsy. * i386-tbl.h: Regenerated.
2017-06-21 08:32:38 -07:00 · 2017-06-21 08:32:38 -07:00 · 2234eee61c
parent c2f7640243
commit 2234eee61c
11 changed files with 80 additions and 55 deletions
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@ -1,3 +1,12 @@
+2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* testsuite/gas/i386/cet-intel.d: Updated.
+	* testsuite/gas/i386/cet.d: Likewise.
+	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
+	* testsuite/gas/i386/x86-64-cet.d: Likewise.
+	* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
+	* testsuite/gas/i386/x86-64-cet.s: Likewise.
+
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>

 	* testsuite/gas/i386/cet-intel.d: Updated.
--- a/gas/testsuite/gas/i386/cet-intel.d
+++ b/gas/testsuite/gas/i386/cet-intel.d
@ -8,23 +8,23 @@
 Disassembly of section .text:

 0+ <_start>:
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f ae e9          	incsspd ecx
 +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
 +[a-f0-9]+:	f3 0f 01 29          	rstorssp QWORD PTR \[ecx\]
 +[a-f0-9]+:	0f 38 f6 04 02       	wrssd  \[edx\+eax\*1\],eax
 +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd \[edi\+ebp\*1\],edx
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[eax\]
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy QWORD PTR \[esp\+eax\*1\]
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f ae e9          	incsspd ecx
 +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
 +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp QWORD PTR \[ecx\+eax\*1\]
 +[a-f0-9]+:	0f 38 f6 02          	wrssd  \[edx\],eax
 +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd \[edi\+ebp\*1\],edx
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[eax\]
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy QWORD PTR \[esp\+eax\*1\]
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
--- a/gas/testsuite/gas/i386/cet.d
+++ b/gas/testsuite/gas/i386/cet.d
@ -6,23 +6,23 @@
 Disassembly of section .text:

 0+ <_start>:
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f ae e9          	incsspd %ecx
 +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
 +[a-f0-9]+:	f3 0f 01 29          	rstorssp \(%ecx\)
 +[a-f0-9]+:	0f 38 f6 04 02       	wrssd  %eax,\(%edx,%eax,1\)
 +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd %edx,\(%edi,%ebp,1\)
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%eax\)
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy \(%esp,%eax,1\)
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f ae e9          	incsspd %ecx
 +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
 +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp \(%ecx,%eax,1\)
 +[a-f0-9]+:	0f 38 f6 02          	wrssd  %eax,\(%edx\)
 +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd %edx,\(%edi,%ebp,1\)
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%eax\)
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy \(%esp,%eax,1\)
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
--- a/gas/testsuite/gas/i386/cet.s
+++ b/gas/testsuite/gas/i386/cet.s
@ -1,25 +1,25 @@
 # Check CET instructions
 	.text
 _start:
-	incsspd
+	incsspd %ecx
 	rdsspd %ecx
 	saveprevssp
 	rstorssp (%ecx)
 	wrssd %eax, (%edx, %eax)
 	wrussd %edx, (%edi, %ebp)
-	setssbsy (%eax)
+	setssbsy
 	clrssbsy (%esp, %eax)
 	endbr64
 	endbr32

 	.intel_syntax noprefix
-	incsspd
+	incsspd ecx
 	rdsspd ecx
 	saveprevssp
 	rstorssp QWORD PTR [ecx + eax]
 	wrssd [edx],eax
 	wrussd [edi + ebp],edx
-	setssbsy QWORD PTR [eax]
+	setssbsy
 	clrssbsy QWORD PTR [esp + eax]
 	endbr64
 	endbr32
--- a/gas/testsuite/gas/i386/x86-64-cet-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-cet-intel.d
@ -7,8 +7,8 @@
 Disassembly of section .text:

 0+ <_start>:
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
- +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f ae ec       	incsspd r12d
+ +[a-f0-9]+:	f3 48 0f ae e8       	incsspq rax
 +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd r12d
 +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq rax
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
@ -17,12 +17,12 @@ Disassembly of section .text:
 +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  \[rcx\+r15\*1\],rdx
 +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd \[r12\],eax
 +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq \[rbx\+rax\*1\],rcx
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[rax\]
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy QWORD PTR \[rsi\+r12\*1\]
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
- +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f ae ec       	incsspd r12d
+ +[a-f0-9]+:	f3 48 0f ae e8       	incsspq rax
 +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd r12d
 +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq rax
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
@ -31,7 +31,7 @@ Disassembly of section .text:
 +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  \[rcx\+r15\*1\],rdx
 +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd \[r12\],eax
 +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq \[rbx\+rax\*1\],rcx
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[rax\]
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy QWORD PTR \[rsi\+r12\*1\]
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
--- a/gas/testsuite/gas/i386/x86-64-cet.d
+++ b/gas/testsuite/gas/i386/x86-64-cet.d
@ -6,8 +6,8 @@
 Disassembly of section .text:

 0+ <_start>:
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
- +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f ae ec       	incsspd %r12d
+ +[a-f0-9]+:	f3 48 0f ae e8       	incsspq %rax
 +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd %r12d
 +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq %rax
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
@ -16,12 +16,12 @@ Disassembly of section .text:
 +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  %rdx,\(%rcx,%r15,1\)
 +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd %eax,\(%r12\)
 +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq %rcx,\(%rbx,%rax,1\)
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%rax\)
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy \(%rsi,%r12,1\)
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
- +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
- +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f ae ec       	incsspd %r12d
+ +[a-f0-9]+:	f3 48 0f ae e8       	incsspq %rax
 +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd %r12d
 +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq %rax
 +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
@ -30,7 +30,7 @@ Disassembly of section .text:
 +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  %rdx,\(%rcx,%r15,1\)
 +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd %eax,\(%r12\)
 +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq %rcx,\(%rbx,%rax,1\)
- +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%rax\)
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
 +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy \(%rsi,%r12,1\)
 +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
 +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
--- a/gas/testsuite/gas/i386/x86-64-cet.s
+++ b/gas/testsuite/gas/i386/x86-64-cet.s
@ -1,8 +1,8 @@
 # Check 64bit CET instructions
 	.text
 _start:
-	incsspd
-	incsspq
+	incsspd %r12d
+	incsspq %rax
 	rdsspd %r12d
 	rdsspq %rax
 	saveprevssp
@ -11,14 +11,14 @@ _start:
 	wrssq %rdx, (%rcx, %r15)
 	wrussd %eax, (%r12)
 	wrussq %rcx, (%rbx, %rax)
-	setssbsy (%rax)
+	setssbsy
 	clrssbsy (%rsi, %r12)
 	endbr64
 	endbr32

 	.intel_syntax noprefix
-	incsspd
-	incsspq
+	incsspd r12d
+	incsspq rax
 	rdsspd r12d
 	rdsspq rax
 	saveprevssp
@ -27,7 +27,7 @@ _start:
 	wrssq [rcx+r15],rdx
 	wrussd [r12],eax
 	wrussq [rbx+rax],rcx
-	setssbsy QWORD PTR [rax]
+	setssbsy
 	clrssbsy QWORD PTR [rsi+r12]
 	endbr64
 	endbr32
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@ -1,3 +1,18 @@
+2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (RM_0FAE_REG_5): Removed.
+	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
+	(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
+	(PREFIX_MOD_3_0FAE_REG_5): Likewise.
+	(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
+	PREFIX_MOD_3_0F01_REG_5_RM_0.
+	(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
+	PREFIX_MOD_3_0FAE_REG_5.
+	(mod_table): Update MOD_0FAE_REG_5.
+	(rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
+	* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
+	* i386-tbl.h: Regenerated.
+
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>

 	* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@ -940,7 +940,6 @@ enum
  RM_0F01_REG_5,
  RM_0F01_REG_7,
  RM_0F1E_MOD_3_REG_7,
-  RM_0FAE_REG_5,
  RM_0FAE_REG_6,
  RM_0FAE_REG_7
 };
@ -949,7 +948,7 @@ enum
 {
  PREFIX_90 = 0,
  PREFIX_MOD_0_0F01_REG_5,
-  PREFIX_MOD_3_0F01_REG_5_RM_1,
+  PREFIX_MOD_3_0F01_REG_5_RM_0,
  PREFIX_MOD_3_0F01_REG_5_RM_2,
  PREFIX_0F10,
  PREFIX_0F11,
@ -997,6 +996,7 @@ enum
  PREFIX_MOD_0_0FAE_REG_4,
  PREFIX_MOD_3_0FAE_REG_4,
  PREFIX_MOD_0_0FAE_REG_5,
+  PREFIX_MOD_3_0FAE_REG_5,
  PREFIX_0FAE_REG_6,
  PREFIX_0FAE_REG_7,
  PREFIX_0FB8,
@ -3789,10 +3789,10 @@ static const struct dis386 prefix_table[][4] = {
    { "rstorssp",	{ Mq }, PREFIX_OPCODE },
  },

-  /* PREFIX_MOD_3_0F01_REG_5_RM_1 */
+  /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
  {
    { Bad_Opcode },
-    { "incsspK",	{ Skip_MODRM }, PREFIX_OPCODE },
+    { "setssbsy",	{ Skip_MODRM }, PREFIX_OPCODE },
  },

  /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
@ -4134,7 +4134,12 @@ static const struct dis386 prefix_table[][4] = {
  /* PREFIX_MOD_0_0FAE_REG_5 */
  {
    { "xrstor",		{ FXSAVE }, PREFIX_OPCODE },
-    { "setssbsy",	{ Mq }, PREFIX_OPCODE },
+  },
+
+  /* PREFIX_MOD_3_0FAE_REG_5 */
+  {
+    { "lfence",		{ Skip_MODRM }, 0 },
+    { "incsspK",	{ Rdq }, PREFIX_OPCODE },
  },

  /* PREFIX_0FAE_REG_6 */
@ -11657,7 +11662,7 @@ static const struct dis386 mod_table[][2] = {
  {
    /* MOD_0FAE_REG_5 */
    { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
-    { RM_TABLE (RM_0FAE_REG_5) },
+    { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
  },
  {
    /* MOD_0FAE_REG_6 */
@ -12233,8 +12238,8 @@ static const struct dis386 rm_table[][8] = {
  },
  {
    /* RM_0F01_REG_5 */
+    { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
    { Bad_Opcode },
-    { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1) },
    { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
    { Bad_Opcode },
    { Bad_Opcode },
@ -12261,10 +12266,6 @@ static const struct dis386 rm_table[][8] = {
    { "nopQ",		{ Ev }, 0 },
    { "nopQ",		{ Ev }, 0 },
  },
-  {
-    /* RM_0FAE_REG_5 */
-    { "lfence",		{ Skip_MODRM }, 0 },
-  },
  {
    /* RM_0FAE_REG_6 */
    { "mfence",		{ Skip_MODRM }, 0 },
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@ -6009,8 +6009,8 @@ ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_

 // CET instructions.

-incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 }
+incsspd, 1, 0xf30fae, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
+incsspq, 1, 0xf30fae, 0x5, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
 rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
 rdsspq, 1, 0xf30f1e, 0x1, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
 saveprevssp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@ -6019,7 +6019,7 @@ wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No
 wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 wrussd, 2, 0x660f38f5, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 wrussq, 2, 0x660f38f5, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-setssbsy, 1, 0xf30fae, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+setssbsy, 0, 0xf30f01e8, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 clrssbsy, 1, 0xf30fae, 0x6, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 endbr64, 0, 0xf30f1efa, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 endbr32, 0, 0xf30f1efb, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@ -91993,30 +91993,30 @@ const insn_template i386_optab[] =
    { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
 	  1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
-  { "incsspd", 0, 0xf30f01e9, None, 3,
+  { "incsspd", 1, 0xf30fae, 0x5, 2,
    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
-  { "incsspq", 0, 0xf30f01e9, None, 3,
+  { "incsspq", 1, 0xf30fae, 0x5, 2,
    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
  { "rdsspd", 1, 0xf30f1e, 0x1, 2,
@ -92135,19 +92135,19 @@ const insn_template i386_optab[] =
      { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
-  { "setssbsy", 1, 0xf30fae, 0x5, 2,
+  { "setssbsy", 0, 0xf30f01e8, None, 3,
    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
-      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0 },
    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
  { "clrssbsy", 1, 0xf30fae, 0x6, 2,
    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,