x86: CET v2.0: Update incssp and setssbsy
Update x86 assembler and disassembler for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf 1. incsspd and incsspq are changed to take a register opeand with a different opcode. 2. setssbsy is changed to take no opeand with a different opcode. gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (RM_0FAE_REG_5): Removed. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_0): New. (PREFIX_MOD_3_0FAE_REG_5): Likewise. (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add PREFIX_MOD_3_0F01_REG_5_RM_0. (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add PREFIX_MOD_3_0FAE_REG_5. (mod_table): Update MOD_0FAE_REG_5. (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. * i386-opc.tbl: Update incsspd, incsspq and setssbsy. * i386-tbl.h: Regenerated.
This commit is contained in:
parent
c2f7640243
commit
2234eee61c
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@ -1,3 +1,12 @@
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2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/cet-intel.d: Updated.
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* testsuite/gas/i386/cet.d: Likewise.
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* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
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* testsuite/gas/i386/x86-64-cet.d: Likewise.
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* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
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* testsuite/gas/i386/x86-64-cet.s: Likewise.
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2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/cet-intel.d: Updated.
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@ -8,23 +8,23 @@
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f ae e9 incsspd ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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+[a-f0-9]+: f3 0f 01 29 rstorssp QWORD PTR \[ecx\]
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+[a-f0-9]+: 0f 38 f6 04 02 wrssd \[edx\+eax\*1\],eax
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[eax\]
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f ae e9 incsspd ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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+[a-f0-9]+: f3 0f 01 2c 01 rstorssp QWORD PTR \[ecx\+eax\*1\]
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+[a-f0-9]+: 0f 38 f6 02 wrssd \[edx\],eax
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[eax\]
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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@ -6,23 +6,23 @@
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f ae e9 incsspd %ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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+[a-f0-9]+: f3 0f 01 29 rstorssp \(%ecx\)
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+[a-f0-9]+: 0f 38 f6 04 02 wrssd %eax,\(%edx,%eax,1\)
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%eax\)
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f ae e9 incsspd %ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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+[a-f0-9]+: f3 0f 01 2c 01 rstorssp \(%ecx,%eax,1\)
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+[a-f0-9]+: 0f 38 f6 02 wrssd %eax,\(%edx\)
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%eax\)
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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@ -1,25 +1,25 @@
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# Check CET instructions
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.text
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_start:
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incsspd
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incsspd %ecx
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rdsspd %ecx
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saveprevssp
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rstorssp (%ecx)
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wrssd %eax, (%edx, %eax)
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wrussd %edx, (%edi, %ebp)
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setssbsy (%eax)
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setssbsy
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clrssbsy (%esp, %eax)
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endbr64
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endbr32
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.intel_syntax noprefix
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incsspd
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incsspd ecx
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rdsspd ecx
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saveprevssp
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rstorssp QWORD PTR [ecx + eax]
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wrssd [edx],eax
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wrussd [edi + ebp],edx
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setssbsy QWORD PTR [eax]
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setssbsy
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clrssbsy QWORD PTR [esp + eax]
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endbr64
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endbr32
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@ -7,8 +7,8 @@
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f ae ec incsspd r12d
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+[a-f0-9]+: f3 48 0f ae e8 incsspq rax
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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@ -17,12 +17,12 @@ Disassembly of section .text:
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[rax\]
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f ae ec incsspd r12d
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+[a-f0-9]+: f3 48 0f ae e8 incsspq rax
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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@ -31,7 +31,7 @@ Disassembly of section .text:
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[rax\]
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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@ -6,8 +6,8 @@
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f ae ec incsspd %r12d
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+[a-f0-9]+: f3 48 0f ae e8 incsspq %rax
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd %r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq %rax
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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@ -16,12 +16,12 @@ Disassembly of section .text:
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq %rdx,\(%rcx,%r15,1\)
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd %eax,\(%r12\)
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq %rcx,\(%rbx,%rax,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%rax\)
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy \(%rsi,%r12,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f ae ec incsspd %r12d
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+[a-f0-9]+: f3 48 0f ae e8 incsspq %rax
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd %r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq %rax
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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@ -30,7 +30,7 @@ Disassembly of section .text:
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq %rdx,\(%rcx,%r15,1\)
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd %eax,\(%r12\)
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq %rcx,\(%rbx,%rax,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%rax\)
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy \(%rsi,%r12,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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# Check 64bit CET instructions
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.text
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_start:
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incsspd
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incsspq
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incsspd %r12d
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incsspq %rax
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rdsspd %r12d
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rdsspq %rax
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saveprevssp
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@ -11,14 +11,14 @@ _start:
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wrssq %rdx, (%rcx, %r15)
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wrussd %eax, (%r12)
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wrussq %rcx, (%rbx, %rax)
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setssbsy (%rax)
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setssbsy
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clrssbsy (%rsi, %r12)
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endbr64
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endbr32
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.intel_syntax noprefix
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incsspd
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incsspq
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incsspd r12d
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incsspq rax
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rdsspd r12d
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rdsspq rax
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saveprevssp
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wrssq [rcx+r15],rdx
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wrussd [r12],eax
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wrussq [rbx+rax],rcx
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setssbsy QWORD PTR [rax]
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setssbsy
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clrssbsy QWORD PTR [rsi+r12]
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endbr64
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endbr32
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@ -1,3 +1,18 @@
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2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (RM_0FAE_REG_5): Removed.
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(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
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(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
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(PREFIX_MOD_3_0FAE_REG_5): Likewise.
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(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
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PREFIX_MOD_3_0F01_REG_5_RM_0.
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(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
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PREFIX_MOD_3_0FAE_REG_5.
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(mod_table): Update MOD_0FAE_REG_5.
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(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
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* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
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* i386-tbl.h: Regenerated.
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2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
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@ -940,7 +940,6 @@ enum
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RM_0F01_REG_5,
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RM_0F01_REG_7,
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RM_0F1E_MOD_3_REG_7,
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RM_0FAE_REG_5,
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RM_0FAE_REG_6,
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RM_0FAE_REG_7
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};
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@ -949,7 +948,7 @@ enum
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{
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PREFIX_90 = 0,
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PREFIX_MOD_0_0F01_REG_5,
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PREFIX_MOD_3_0F01_REG_5_RM_1,
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PREFIX_MOD_3_0F01_REG_5_RM_0,
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PREFIX_MOD_3_0F01_REG_5_RM_2,
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PREFIX_0F10,
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PREFIX_0F11,
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PREFIX_MOD_0_0FAE_REG_4,
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PREFIX_MOD_3_0FAE_REG_4,
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PREFIX_MOD_0_0FAE_REG_5,
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PREFIX_MOD_3_0FAE_REG_5,
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PREFIX_0FAE_REG_6,
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PREFIX_0FAE_REG_7,
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PREFIX_0FB8,
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@ -3789,10 +3789,10 @@ static const struct dis386 prefix_table[][4] = {
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{ "rstorssp", { Mq }, PREFIX_OPCODE },
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},
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/* PREFIX_MOD_3_0F01_REG_5_RM_1 */
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/* PREFIX_MOD_3_0F01_REG_5_RM_0 */
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{
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{ Bad_Opcode },
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{ "incsspK", { Skip_MODRM }, PREFIX_OPCODE },
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{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
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},
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/* PREFIX_MOD_3_0F01_REG_5_RM_2 */
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@ -4134,7 +4134,12 @@ static const struct dis386 prefix_table[][4] = {
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/* PREFIX_MOD_0_0FAE_REG_5 */
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{
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{ "xrstor", { FXSAVE }, PREFIX_OPCODE },
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{ "setssbsy", { Mq }, PREFIX_OPCODE },
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},
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/* PREFIX_MOD_3_0FAE_REG_5 */
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{
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{ "lfence", { Skip_MODRM }, 0 },
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{ "incsspK", { Rdq }, PREFIX_OPCODE },
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},
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/* PREFIX_0FAE_REG_6 */
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@ -11657,7 +11662,7 @@ static const struct dis386 mod_table[][2] = {
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{
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/* MOD_0FAE_REG_5 */
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{ PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
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{ RM_TABLE (RM_0FAE_REG_5) },
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{ PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
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},
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{
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/* MOD_0FAE_REG_6 */
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@ -12233,8 +12238,8 @@ static const struct dis386 rm_table[][8] = {
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},
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{
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/* RM_0F01_REG_5 */
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{ PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1) },
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{ PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
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{ Bad_Opcode },
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{ Bad_Opcode },
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@ -12261,10 +12266,6 @@ static const struct dis386 rm_table[][8] = {
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{ "nopQ", { Ev }, 0 },
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{ "nopQ", { Ev }, 0 },
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},
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{
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/* RM_0FAE_REG_5 */
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{ "lfence", { Skip_MODRM }, 0 },
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},
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{
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/* RM_0FAE_REG_6 */
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{ "mfence", { Skip_MODRM }, 0 },
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@ -6009,8 +6009,8 @@ ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_
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// CET instructions.
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|
||||
incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 }
|
||||
incsspd, 1, 0xf30fae, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
|
||||
incsspq, 1, 0xf30fae, 0x5, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
|
||||
rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
|
||||
rdsspq, 1, 0xf30f1e, 0x1, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
|
||||
saveprevssp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
@ -6019,7 +6019,7 @@ wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No
|
|||
wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
wrussd, 2, 0x660f38f5, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
wrussq, 2, 0x660f38f5, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
setssbsy, 1, 0xf30fae, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
setssbsy, 0, 0xf30f01e8, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
clrssbsy, 1, 0xf30fae, 0x6, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
endbr64, 0, 0xf30f1efa, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
endbr32, 0, 0xf30f1efb, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
|
|
@ -91993,30 +91993,30 @@ const insn_template i386_optab[] =
|
|||
{ { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
|
||||
{ "incsspd", 0, 0xf30f01e9, None, 3,
|
||||
{ "incsspd", 1, 0xf30fae, 0x5, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "incsspq", 0, 0xf30f01e9, None, 3,
|
||||
{ "incsspq", 1, 0xf30fae, 0x5, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "rdsspd", 1, 0xf30f1e, 0x1, 2,
|
||||
|
@ -92135,19 +92135,19 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
|
||||
{ "setssbsy", 1, 0xf30fae, 0x5, 2,
|
||||
{ "setssbsy", 0, 0xf30f01e8, None, 3,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "clrssbsy", 1, 0xf30fae, 0x6, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
Loading…
Reference in New Issue