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[Aarch64] Support ARMv8.2 AT instructions

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ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
	AT S1E1WP.
	* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
	(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
	feature test for "s1e1rp" and "s1e1wp".

Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
This commit is contained in:
Matthew Wahab 2015-12-10 16:58:51 +00:00
parent b1236ac35a
commit 22a5455c6c
5 changed files with 27 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for dc instruction.

2
gas/testsuite/gas/aarch64/sysreg-2.d
View File

@ -30,3 +30,5 @@ Disassembly of section .text:
[0-9a-f]+: d50b7a20 dc cvac, x0
[0-9a-f]+: d50b7b21 dc cvau, x1
[0-9a-f]+: d50b7c22 dc cvap, x2
[0-9a-f]+: d5087900 at s1e1rp, x0
[0-9a-f]+: d5087921 at s1e1wp, x1

5
gas/testsuite/gas/aarch64/sysreg-2.s
View File

@ -36,3 +36,8 @@
dc cvac, x0
dc cvau, x1
dc cvap, x2
/* AT. */
at s1e1rp, x0
at s1e1wp, x1

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".

8
opcodes/aarch64-opc.c
View File

@ -3245,6 +3245,12 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
if ((reg->value == CPENS (0, C7, C9, 0)
|| reg->value == CPENS (0, C7, C9, 1))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
return TRUE;
}
@ -3284,6 +3290,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
{ "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
{ "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
{ "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
{ "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
{ 0, CPENS(0,0,0,0), 0 }
};