x86: restrict %tr<N> visibility
First of all, these registers have never been available on any 64-bit CPU, and hence should not be recognized in 64-bit mode. But even before that they had already disappeared - also don't recognize them when 586 or 686 architectures were explicitly set.
This commit is contained in:
parent
1ab84e0251
commit
22e00a3f4d
|
@ -1,3 +1,12 @@
|
||||||
|
2020-06-08 Jan Beulich <jbeulich@suse.com>
|
||||||
|
|
||||||
|
* config/tc-i386.c (check_register): Split RegTR handling, to
|
||||||
|
fail recognition also in 64-bit mode as well as with i586 or
|
||||||
|
i686 explicitly enabled.
|
||||||
|
* testsuite/gas/i386/x86_64.s: Add insns referencing tr<N>.
|
||||||
|
* testsuite/gas/i386/x86_64-intel.d,
|
||||||
|
testsuite/gas/i386/x86_64.d: Adjust expectations.
|
||||||
|
|
||||||
2020-06-08 Jan Beulich <jbeulich@suse.com>
|
2020-06-08 Jan Beulich <jbeulich@suse.com>
|
||||||
|
|
||||||
* testsuite/gas/cfi/cfi-i386-2.d: Adjust expectations.
|
* testsuite/gas/cfi/cfi-i386-2.d: Adjust expectations.
|
||||||
|
|
|
@ -12358,11 +12358,17 @@ static bfd_boolean check_register (const reg_entry *r)
|
||||||
if ((r->reg_type.bitfield.dword
|
if ((r->reg_type.bitfield.dword
|
||||||
|| (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
|
|| (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
|
||||||
|| r->reg_type.bitfield.class == RegCR
|
|| r->reg_type.bitfield.class == RegCR
|
||||||
|| r->reg_type.bitfield.class == RegDR
|
|| r->reg_type.bitfield.class == RegDR)
|
||||||
|| r->reg_type.bitfield.class == RegTR)
|
|
||||||
&& !cpu_arch_flags.bitfield.cpui386)
|
&& !cpu_arch_flags.bitfield.cpui386)
|
||||||
return FALSE;
|
return FALSE;
|
||||||
|
|
||||||
|
if (r->reg_type.bitfield.class == RegTR
|
||||||
|
&& (flag_code == CODE_64BIT
|
||||||
|
|| !cpu_arch_flags.bitfield.cpui386
|
||||||
|
|| cpu_arch_isa_flags.bitfield.cpui586
|
||||||
|
|| cpu_arch_isa_flags.bitfield.cpui686))
|
||||||
|
return FALSE;
|
||||||
|
|
||||||
if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
|
if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
|
||||||
return FALSE;
|
return FALSE;
|
||||||
|
|
||||||
|
|
|
@ -256,4 +256,6 @@ Disassembly of section .text:
|
||||||
[ ]*[a-f0-9]+: 48 0f b7 00 movzx rax,WORD PTR \[rax\]
|
[ ]*[a-f0-9]+: 48 0f b7 00 movzx rax,WORD PTR \[rax\]
|
||||||
[ ]*[a-f0-9]+: 0f c3 00 movnti DWORD PTR \[rax\],eax
|
[ ]*[a-f0-9]+: 0f c3 00 movnti DWORD PTR \[rax\],eax
|
||||||
[ ]*[a-f0-9]+: 48 0f c3 00 movnti QWORD PTR \[rax\],rax
|
[ ]*[a-f0-9]+: 48 0f c3 00 movnti QWORD PTR \[rax\],rax
|
||||||
|
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov eax,DWORD PTR (ds:)?0x0
|
||||||
|
[ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov QWORD PTR (ds:)?0x0,rcx
|
||||||
#pass
|
#pass
|
||||||
|
|
|
@ -256,4 +256,6 @@ Disassembly of section .text:
|
||||||
[ ]*[a-f0-9]+: 48 0f b7 00 movzwq \(%rax\),%rax
|
[ ]*[a-f0-9]+: 48 0f b7 00 movzwq \(%rax\),%rax
|
||||||
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
|
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
|
||||||
[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)
|
[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)
|
||||||
|
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
|
||||||
|
[ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov %rcx,0x0
|
||||||
#pass
|
#pass
|
||||||
|
|
|
@ -307,3 +307,6 @@ movzx rax, WORD PTR [rax]
|
||||||
|
|
||||||
movnti dword ptr [rax], eax
|
movnti dword ptr [rax], eax
|
||||||
movnti qword ptr [rax], rax
|
movnti qword ptr [rax], rax
|
||||||
|
|
||||||
|
mov eax, tr1
|
||||||
|
mov tr0, rcx
|
||||||
|
|
Loading…
Reference in New Issue