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cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler 

This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling.  This
matches better with the current practice, vs. cBPF.

It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.

cpu/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
	%a and %ctx.

opcodes/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerated.

gas/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
	* testsuite/gas/bpf/lddw-be.d: Likewise.
	* testsuite/gas/bpf/lddw.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
This commit is contained in:
Jose E. Marchesi 2019-07-19 15:35:43 +02:00
parent 1802aae844
commit 231097b03a
11 changed files with 75 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
cpu/ChangeLog
View File

@ -1,3 +1,8 @@
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
%a and %ctx.
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (dlabs): New pmacro. * bpf.cpu (dlabs): New pmacro.

4
cpu/bpf.cpu
View File

@ -156,10 +156,10 @@
;; XXX the frame pointer fp is read-only, so it should ;; XXX the frame pointer fp is read-only, so it should
;; go in a different hardware. ;; go in a different hardware.
(;; ABI names. Take priority when disassembling. (;; ABI names. Take priority when disassembling.
(a 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (ctx 6) (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
(r7 7) (r8 8) (r9 9) (fp 10) (r7 7) (r8 8) (r9 9) (fp 10)
;; Additional names recognized when assembling. ;; Additional names recognized when assembling.
(r0 0) (r6 6) (r10 10)))) (a 0) (ctx 6) (r10 10))))
;; The program counter. CGEN requires it, even if it is not visible ;; The program counter. CGEN requires it, even if it is not visible
;; to eBPF programs. ;; to eBPF programs.

8
gas/ChangeLog
View File

@ -1,3 +1,11 @@
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
* testsuite/gas/bpf/lddw-be.d: Likewise.
* testsuite/gas/bpf/lddw.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c. * config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c.

24
gas/testsuite/gas/bpf/alu-be.d
View File

@ -11,49 +11,49 @@ Disassembly of section .text:
0: 07 20 00 00 00 00 02 9a add %r2,0x29a 0: 07 20 00 00 00 00 02 9a add %r2,0x29a
8: 07 30 00 00 ff ff fd 66 add %r3,-666 8: 07 30 00 00 ff ff fd 66 add %r3,-666
10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
18: 0f 56 00 00 00 00 00 00 add %r5,%ctx 18: 0f 56 00 00 00 00 00 00 add %r5,%r6
20: 17 20 00 00 00 00 02 9a sub %r2,0x29a 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
28: 17 30 00 00 ff ff fd 66 sub %r3,-666 28: 17 30 00 00 ff ff fd 66 sub %r3,-666
30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
38: 1f 56 00 00 00 00 00 00 sub %r5,%ctx 38: 1f 56 00 00 00 00 00 00 sub %r5,%r6
40: 27 20 00 00 00 00 02 9a mul %r2,0x29a 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
48: 27 30 00 00 ff ff fd 66 mul %r3,-666 48: 27 30 00 00 ff ff fd 66 mul %r3,-666
50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
58: 2f 56 00 00 00 00 00 00 mul %r5,%ctx 58: 2f 56 00 00 00 00 00 00 mul %r5,%r6
60: 37 20 00 00 00 00 02 9a div %r2,0x29a 60: 37 20 00 00 00 00 02 9a div %r2,0x29a
68: 37 30 00 00 ff ff fd 66 div %r3,-666 68: 37 30 00 00 ff ff fd 66 div %r3,-666
70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
78: 3f 56 00 00 00 00 00 00 div %r5,%ctx 78: 3f 56 00 00 00 00 00 00 div %r5,%r6
80: 47 20 00 00 00 00 02 9a or %r2,0x29a 80: 47 20 00 00 00 00 02 9a or %r2,0x29a
88: 47 30 00 00 ff ff fd 66 or %r3,-666 88: 47 30 00 00 ff ff fd 66 or %r3,-666
90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
98: 4f 56 00 00 00 00 00 00 or %r5,%ctx 98: 4f 56 00 00 00 00 00 00 or %r5,%r6
a0: 57 20 00 00 00 00 02 9a and %r2,0x29a a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
a8: 57 30 00 00 ff ff fd 66 and %r3,-666 a8: 57 30 00 00 ff ff fd 66 and %r3,-666
b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
b8: 5f 56 00 00 00 00 00 00 and %r5,%ctx b8: 5f 56 00 00 00 00 00 00 and %r5,%r6
c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666 c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666
d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
d8: 6f 56 00 00 00 00 00 00 lsh %r5,%ctx d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666 e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666
f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
f8: 7f 56 00 00 00 00 00 00 rsh %r5,%ctx f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6
100: 97 20 00 00 00 00 02 9a mod %r2,0x29a 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
108: 97 30 00 00 ff ff fd 66 mod %r3,-666 108: 97 30 00 00 ff ff fd 66 mod %r3,-666
110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
118: 9f 56 00 00 00 00 00 00 mod %r5,%ctx 118: 9f 56 00 00 00 00 00 00 mod %r5,%r6
120: a7 20 00 00 00 00 02 9a xor %r2,0x29a 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
128: a7 30 00 00 ff ff fd 66 xor %r3,-666 128: a7 30 00 00 ff ff fd 66 xor %r3,-666
130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
138: af 56 00 00 00 00 00 00 xor %r5,%ctx 138: af 56 00 00 00 00 00 00 xor %r5,%r6
140: b7 20 00 00 00 00 02 9a mov %r2,0x29a 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
148: b7 30 00 00 ff ff fd 66 mov %r3,-666 148: b7 30 00 00 ff ff fd 66 mov %r3,-666
150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
158: bf 56 00 00 00 00 00 00 mov %r5,%ctx 158: bf 56 00 00 00 00 00 00 mov %r5,%r6
160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
168: c7 30 00 00 ff ff fd 66 arsh %r3,-666 168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
178: cf 56 00 00 00 00 00 00 arsh %r5,%ctx 178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
180: 8f 20 00 00 00 00 00 00 neg %r2 180: 8f 20 00 00 00 00 00 00 neg %r2

24
gas/testsuite/gas/bpf/alu.d
View File

@ -10,49 +10,49 @@ Disassembly of section .text:
0: 07 02 00 00 9a 02 00 00 add %r2,0x29a 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
8: 07 03 00 00 66 fd ff ff add %r3,-666 8: 07 03 00 00 66 fd ff ff add %r3,-666
10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
18: 0f 65 00 00 00 00 00 00 add %r5,%ctx 18: 0f 65 00 00 00 00 00 00 add %r5,%r6
20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
28: 17 03 00 00 66 fd ff ff sub %r3,-666 28: 17 03 00 00 66 fd ff ff sub %r3,-666
30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
38: 1f 65 00 00 00 00 00 00 sub %r5,%ctx 38: 1f 65 00 00 00 00 00 00 sub %r5,%r6
40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
48: 27 03 00 00 66 fd ff ff mul %r3,-666 48: 27 03 00 00 66 fd ff ff mul %r3,-666
50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
58: 2f 65 00 00 00 00 00 00 mul %r5,%ctx 58: 2f 65 00 00 00 00 00 00 mul %r5,%r6
60: 37 02 00 00 9a 02 00 00 div %r2,0x29a 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
68: 37 03 00 00 66 fd ff ff div %r3,-666 68: 37 03 00 00 66 fd ff ff div %r3,-666
70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
78: 3f 65 00 00 00 00 00 00 div %r5,%ctx 78: 3f 65 00 00 00 00 00 00 div %r5,%r6
80: 47 02 00 00 9a 02 00 00 or %r2,0x29a 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
88: 47 03 00 00 66 fd ff ff or %r3,-666 88: 47 03 00 00 66 fd ff ff or %r3,-666
90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
98: 4f 65 00 00 00 00 00 00 or %r5,%ctx 98: 4f 65 00 00 00 00 00 00 or %r5,%r6
a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
a8: 57 03 00 00 66 fd ff ff and %r3,-666 a8: 57 03 00 00 66 fd ff ff and %r3,-666
b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
b8: 5f 65 00 00 00 00 00 00 and %r5,%ctx b8: 5f 65 00 00 00 00 00 00 and %r5,%r6
c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
c8: 67 03 00 00 66 fd ff ff lsh %r3,-666 c8: 67 03 00 00 66 fd ff ff lsh %r3,-666
d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
d8: 6f 65 00 00 00 00 00 00 lsh %r5,%ctx d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
e8: 77 03 00 00 66 fd ff ff rsh %r3,-666 e8: 77 03 00 00 66 fd ff ff rsh %r3,-666
f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
f8: 7f 65 00 00 00 00 00 00 rsh %r5,%ctx f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6
100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
108: 97 03 00 00 66 fd ff ff mod %r3,-666 108: 97 03 00 00 66 fd ff ff mod %r3,-666
110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
118: 9f 65 00 00 00 00 00 00 mod %r5,%ctx 118: 9f 65 00 00 00 00 00 00 mod %r5,%r6
120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
128: a7 03 00 00 66 fd ff ff xor %r3,-666 128: a7 03 00 00 66 fd ff ff xor %r3,-666
130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
138: af 65 00 00 00 00 00 00 xor %r5,%ctx 138: af 65 00 00 00 00 00 00 xor %r5,%r6
140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
148: b7 03 00 00 66 fd ff ff mov %r3,-666 148: b7 03 00 00 66 fd ff ff mov %r3,-666
150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
158: bf 65 00 00 00 00 00 00 mov %r5,%ctx 158: bf 65 00 00 00 00 00 00 mov %r5,%r6
160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
168: c7 03 00 00 66 fd ff ff arsh %r3,-666 168: c7 03 00 00 66 fd ff ff arsh %r3,-666
170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
178: cf 65 00 00 00 00 00 00 arsh %r5,%ctx 178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
180: 8f 02 00 00 00 00 00 00 neg %r2 180: 8f 02 00 00 00 00 00 00 neg %r2

26
gas/testsuite/gas/bpf/alu32-be.d
View File

@ -11,55 +11,55 @@ Disassembly of section .text:
0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
8: 04 30 00 00 ff ff fd 66 add32 %r3,-666 8: 04 30 00 00 ff ff fd 66 add32 %r3,-666
10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
18: 0c 56 00 00 00 00 00 00 add32 %r5,%ctx 18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6
20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666 28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666
30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
38: 1c 56 00 00 00 00 00 00 sub32 %r5,%ctx 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666 48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666
50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
58: 2c 56 00 00 00 00 00 00 mul32 %r5,%ctx 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
68: 34 30 00 00 ff ff fd 66 div32 %r3,-666 68: 34 30 00 00 ff ff fd 66 div32 %r3,-666
70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
78: 3c 56 00 00 00 00 00 00 div32 %r5,%ctx 78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6
80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
88: 44 30 00 00 ff ff fd 66 or32 %r3,-666 88: 44 30 00 00 ff ff fd 66 or32 %r3,-666
90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
98: 4c 56 00 00 00 00 00 00 or32 %r5,%ctx 98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666 a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666
b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
b8: 5c 56 00 00 00 00 00 00 and32 %r5,%ctx b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666 c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666
d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%ctx d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666 e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666
f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%ctx f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666 108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666
110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
118: 9c 56 00 00 00 00 00 00 mod32 %r5,%ctx 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666 128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666
130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
138: ac 56 00 00 00 00 00 00 xor32 %r5,%ctx 138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666 148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666
150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
158: bc 56 00 00 00 00 00 00 mov32 %r5,%ctx 158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
178: cc 56 00 00 00 00 00 00 arsh32 %r5,%ctx 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
180: 8c 20 00 00 00 00 00 00 neg32 %r2 180: 8c 20 00 00 00 00 00 00 neg32 %r2
188: d4 90 00 00 00 00 00 10 endle %r9,16 188: d4 90 00 00 00 00 00 10 endle %r9,16
190: d4 80 00 00 00 00 00 20 endle %r8,32 190: d4 80 00 00 00 00 00 20 endle %r8,32
198: d4 70 00 00 00 00 00 40 endle %r7,64 198: d4 70 00 00 00 00 00 40 endle %r7,64
1a0: dc 60 00 00 00 00 00 10 endbe %ctx,16 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16
1a8: dc 50 00 00 00 00 00 20 endbe %r5,32 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
1b0: dc 40 00 00 00 00 00 40 endbe %r4,64 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64

26
gas/testsuite/gas/bpf/alu32.d
View File

@ -10,55 +10,55 @@ Disassembly of section .text:
0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
8: 04 03 00 00 66 fd ff ff add32 %r3,-666 8: 04 03 00 00 66 fd ff ff add32 %r3,-666
10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
18: 0c 65 00 00 00 00 00 00 add32 %r5,%ctx 18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6
20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
28: 14 03 00 00 66 fd ff ff sub32 %r3,-666 28: 14 03 00 00 66 fd ff ff sub32 %r3,-666
30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
38: 1c 65 00 00 00 00 00 00 sub32 %r5,%ctx 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
48: 24 03 00 00 66 fd ff ff mul32 %r3,-666 48: 24 03 00 00 66 fd ff ff mul32 %r3,-666
50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
58: 2c 65 00 00 00 00 00 00 mul32 %r5,%ctx 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
68: 34 03 00 00 66 fd ff ff div32 %r3,-666 68: 34 03 00 00 66 fd ff ff div32 %r3,-666
70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
78: 3c 65 00 00 00 00 00 00 div32 %r5,%ctx 78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6
80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
88: 44 03 00 00 66 fd ff ff or32 %r3,-666 88: 44 03 00 00 66 fd ff ff or32 %r3,-666
90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
98: 4c 65 00 00 00 00 00 00 or32 %r5,%ctx 98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
a8: 54 03 00 00 66 fd ff ff and32 %r3,-666 a8: 54 03 00 00 66 fd ff ff and32 %r3,-666
b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
b8: 5c 65 00 00 00 00 00 00 and32 %r5,%ctx b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666 c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666
d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%ctx d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666 e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666
f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%ctx f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
108: 94 03 00 00 66 fd ff ff mod32 %r3,-666 108: 94 03 00 00 66 fd ff ff mod32 %r3,-666
110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
118: 9c 65 00 00 00 00 00 00 mod32 %r5,%ctx 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
128: a4 03 00 00 66 fd ff ff xor32 %r3,-666 128: a4 03 00 00 66 fd ff ff xor32 %r3,-666
130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
138: ac 65 00 00 00 00 00 00 xor32 %r5,%ctx 138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
148: b4 03 00 00 66 fd ff ff mov32 %r3,-666 148: b4 03 00 00 66 fd ff ff mov32 %r3,-666
150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
158: bc 65 00 00 00 00 00 00 mov32 %r5,%ctx 158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666 168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
178: cc 65 00 00 00 00 00 00 arsh32 %r5,%ctx 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
180: 8c 02 00 00 00 00 00 00 neg32 %r2 180: 8c 02 00 00 00 00 00 00 neg32 %r2
188: d4 09 00 00 10 00 00 00 endle %r9,16 188: d4 09 00 00 10 00 00 00 endle %r9,16
190: d4 08 00 00 20 00 00 00 endle %r8,32 190: d4 08 00 00 20 00 00 00 endle %r8,32
198: d4 07 00 00 40 00 00 00 endle %r7,64 198: d4 07 00 00 40 00 00 00 endle %r7,64
1a0: dc 06 00 00 10 00 00 00 endbe %ctx,16 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16
1a8: dc 05 00 00 20 00 00 00 endbe %r5,32 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
1b0: dc 04 00 00 40 00 00 00 endbe %r4,64 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64

2
gas/testsuite/gas/bpf/lddw-be.d
View File

@ -14,5 +14,5 @@ Disassembly of section .text:
18: 00 00 00 00 00 00 00 00 18: 00 00 00 00 00 00 00 00
20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
28: 00 00 00 00 11 22 33 44 28: 00 00 00 00 11 22 33 44
30: 18 60 00 00 ff ff ff fe lddw %ctx,-2 30: 18 60 00 00 ff ff ff fe lddw %r6,-2
38: 00 00 00 00 ff ff ff ff 38: 00 00 00 00 ff ff ff ff

2
gas/testsuite/gas/bpf/lddw.d
View File

@ -13,5 +13,5 @@ Disassembly of section .text:
18: 00 00 00 00 00 00 00 00 18: 00 00 00 00 00 00 00 00
20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
28: 00 00 00 00 44 33 22 11 28: 00 00 00 00 44 33 22 11
30: 18 06 00 00 fe ff ff ff lddw %ctx,-2 30: 18 06 00 00 fe ff ff ff lddw %r6,-2
38: 00 00 00 00 ff ff ff ff 38: 00 00 00 00 ff ff ff ff

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerated.
2019-07-17 Jan Beulich <jbeulich@suse.com> 2019-07-17 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (static_assert): Define. * i386-gen.c (static_assert): Define.

8
opcodes/bpf-desc.c
View File

@ -133,19 +133,19 @@ static const CGEN_MACH bpf_cgen_mach_table[] = {
static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] = static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
{ {
{ "%a", 0, {0, {{{0, 0}}}}, 0, 0 }, { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "%r1", 1, {0, {{{0, 0}}}}, 0, 0 }, { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "%r2", 2, {0, {{{0, 0}}}}, 0, 0 }, { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "%r3", 3, {0, {{{0, 0}}}}, 0, 0 }, { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
{ "%r4", 4, {0, {{{0, 0}}}}, 0, 0 }, { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "%r5", 5, {0, {{{0, 0}}}}, 0, 0 }, { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 }, { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "%r7", 7, {0, {{{0, 0}}}}, 0, 0 }, { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "%r8", 8, {0, {{{0, 0}}}}, 0, 0 }, { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "%r9", 9, {0, {{{0, 0}}}}, 0, 0 }, { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "%fp", 10, {0, {{{0, 0}}}}, 0, 0 }, { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "%r0", 0, {0, {{{0, 0}}}}, 0, 0 }, { "%a", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "%r6", 6, {0, {{{0, 0}}}}, 0, 0 }, { "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "%r10", 10, {0, {{{0, 0}}}}, 0, 0 } { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
}; };