This patch addresses the change in the June Armv8.1-M Mainline specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size.
The instructions that this change apply to are: VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf Fixed this by removing the check for this warning from GAS as well as opcodes. Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size and the same source and destination operand. Also fixed tests that would previously check for this warning. gas * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE. * testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmladh.d: New tests. * testsuite/gas/arm/mve-vqdmladh.s: New tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh.d: New tests. * testsuite/gas/arm/mve-vqdmlsdh.s: New tests. opcodes * arm-dis.c (is_mve_unpredictable): Stop marking some MVE instructions as UNPREDICTABLE.
This commit is contained in:
Barnaby Wilks
Nick Clifton
parent
a8e9d24718
commit
236ab0c60c
@ -1,3 +1,15 @@
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2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
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* config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
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* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
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* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
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* testsuite/gas/arm/mve-vqdmladh.d: New tests.
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* testsuite/gas/arm/mve-vqdmladh.s: New tests.
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* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
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* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
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* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
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* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.
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2019-07-19 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/noextreg.d: Pass -O0 to assembler.
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@ -17922,11 +17922,6 @@ do_mve_vqdmladh (void)
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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if (et.size == 32
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&& (inst.operands[0].reg == inst.operands[1].reg
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|| inst.operands[0].reg == inst.operands[2].reg))
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as_tsktsk (BAD_MVE_SRCDEST);
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mve_encode_qqq (0, et.size);
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}
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@ -1,61 +1,53 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
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[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:14: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
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[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
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[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
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[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
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[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
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[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:32: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:34: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
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[^:]*:39: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:40: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:42: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
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[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
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[^:]*:47: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:48: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:50: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
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[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
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[^:]*:55: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:56: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:58: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
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[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'
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[^:]*:12: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
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[^:]*:13: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
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[^:]*:14: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
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[^:]*:16: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
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[^:]*:17: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:24: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:26: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
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[^:]*:29: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
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[^:]*:31: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:32: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:34: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
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[^:]*:39: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:40: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:42: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
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[^:]*:45: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
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[^:]*:47: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:48: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:50: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
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[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'
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@ -9,20 +9,12 @@ it \cond
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.thumb
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vqdmladh.u32 q0, q1, q2
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vqdmladh.s64 q0, q1, q2
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vqdmladh.s32 q0, q0, q2
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vqdmladh.s32 q0, q1, q0
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vqdmladhx.u32 q0, q1, q2
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vqdmladhx.s64 q0, q1, q2
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vqdmladhx.s32 q0, q0, q2
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vqdmladhx.s32 q0, q1, q0
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vqrdmladh.u32 q0, q1, q2
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vqrdmladh.s64 q0, q1, q2
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vqrdmladh.s32 q0, q0, q2
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vqrdmladh.s32 q0, q1, q0
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vqrdmladhx.u32 q0, q1, q2
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vqrdmladhx.s64 q0, q1, q2
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vqrdmladhx.s32 q0, q0, q2
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vqrdmladhx.s32 q0, q1, q0
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cond vqdmladh
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cond vqdmladhx
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cond vqrdmladh
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@ -1399,3 +1399,9 @@ Disassembly of section .text:
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[^>]*> ee22 0e05 vqrdmladhe.s32 q0, q1, q2
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[^>]*> ee12 1e05 vqrdmladhxt.s16 q0, q1, q2
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[^>]*> ee12 1e05 vqrdmladhxe.s16 q0, q1, q2
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[^>]*> ee20 0e00 vqdmladh.s32 q0, q0, q0
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[^>]*> ee20 0e01 vqrdmladh.s32 q0, q0, q0
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[^>]*> ee20 0e02 vqdmladh.s32 q0, q0, q1
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[^>]*> ee22 2e05 vqrdmladh.s32 q1, q1, q2
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[^>]*> ee26 4e04 vqdmladh.s32 q2, q3, q2
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[^>]*> ee28 6e07 vqrdmladh.s32 q3, q4, q3
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@ -73,3 +73,9 @@ vqrdmladht.s32 q0, q1, q2
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vqrdmladhe.s32 q0, q1, q2
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vqrdmladhxt.s16 q0, q1, q2
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vqrdmladhxe.s16 q0, q1, q2
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vqdmladh.s32 q0, q0, q0
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vqrdmladh.s32 q0, q0, q0
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vqdmladh.s32 q0, q0, q1
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vqrdmladh.s32 q1, q1, q2
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vqdmladh.s32 q2, q3, q2
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vqrdmladh.s32 q3, q4, q3
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@ -1,61 +1,53 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
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[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:14: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
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[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
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[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
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[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
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[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
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[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
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[^:]*:32: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
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[^:]*:34: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
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[^:]*:39: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:40: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:42: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
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[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
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[^:]*:47: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
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[^:]*:48: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
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[^:]*:50: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
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[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
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[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
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[^:]*:55: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:56: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:58: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
|
||||
[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
|
||||
[^:]*:14: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
|
||||
[^:]*:15: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
|
||||
[^:]*:17: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:23: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
|
||||
[^:]*:24: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
|
||||
[^:]*:26: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
|
||||
[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
|
||||
[^:]*:29: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
|
||||
[^:]*:31: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:32: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:34: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
|
||||
[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
|
||||
[^:]*:39: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
|
||||
[^:]*:40: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
|
||||
[^:]*:42: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
|
||||
[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
|
||||
[^:]*:45: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
|
||||
[^:]*:47: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:48: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:50: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
|
||||
[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
|
||||
[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'
|
||||
|
||||
@ -9,20 +9,12 @@ it \cond
|
||||
.thumb
|
||||
vqdmlsdh.u32 q0, q1, q2
|
||||
vqdmlsdh.s64 q0, q1, q2
|
||||
vqdmlsdh.s32 q0, q0, q2
|
||||
vqdmlsdh.s32 q0, q1, q0
|
||||
vqdmlsdhx.u32 q0, q1, q2
|
||||
vqdmlsdhx.s64 q0, q1, q2
|
||||
vqdmlsdhx.s32 q0, q0, q2
|
||||
vqdmlsdhx.s32 q0, q1, q0
|
||||
vqrdmlsdh.u32 q0, q1, q2
|
||||
vqrdmlsdh.s64 q0, q1, q2
|
||||
vqrdmlsdh.s32 q0, q0, q2
|
||||
vqrdmlsdh.s32 q0, q1, q0
|
||||
vqrdmlsdhx.u32 q0, q1, q2
|
||||
vqrdmlsdhx.s64 q0, q1, q2
|
||||
vqrdmlsdhx.s32 q0, q0, q2
|
||||
vqrdmlsdhx.s32 q0, q1, q0
|
||||
cond vqdmlsdh
|
||||
cond vqdmlsdhx
|
||||
cond vqrdmlsdh
|
||||
|
||||
@ -1399,3 +1399,9 @@ Disassembly of section .text:
|
||||
[^>]*> fe22 0e05 vqrdmlsdhe.s32 q0, q1, q2
|
||||
[^>]*> fe12 1e05 vqrdmlsdhxt.s16 q0, q1, q2
|
||||
[^>]*> fe12 1e05 vqrdmlsdhxe.s16 q0, q1, q2
|
||||
[^>]*> fe20 0e00 vqdmlsdh.s32 q0, q0, q0
|
||||
[^>]*> fe20 0e01 vqrdmlsdh.s32 q0, q0, q0
|
||||
[^>]*> fe22 2e04 vqdmlsdh.s32 q1, q1, q2
|
||||
[^>]*> fe24 4e07 vqrdmlsdh.s32 q2, q2, q3
|
||||
[^>]*> fe28 6e06 vqdmlsdh.s32 q3, q4, q3
|
||||
[^>]*> fe2a 8e09 vqrdmlsdh.s32 q4, q5, q4
|
||||
|
||||
@ -71,3 +71,9 @@ vqrdmlsdht.s32 q0, q1, q2
|
||||
vqrdmlsdhe.s32 q0, q1, q2
|
||||
vqrdmlsdhxt.s16 q0, q1, q2
|
||||
vqrdmlsdhxe.s16 q0, q1, q2
|
||||
vqdmlsdh.s32 q0, q0, q0
|
||||
vqrdmlsdh.s32 q0, q0, q0
|
||||
vqdmlsdh.s32 q1, q1, q2
|
||||
vqrdmlsdh.s32 q2, q2, q3
|
||||
vqdmlsdh.s32 q3, q4, q3
|
||||
vqrdmlsdh.s32 q4, q5, q4
|
||||
|
||||
@ -6546,10 +6546,6 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
case MVE_VQRDMLADH:
|
||||
case MVE_VQDMLSDH:
|
||||
case MVE_VQRDMLSDH:
|
||||
case MVE_VQDMLADH:
|
||||
case MVE_VMULL_INT:
|
||||
{
|
||||
unsigned long Qd;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user