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RXv2 support update 

2015-12-22  Yoshinori Sato <ysato@users.sourceforge.jp>

opcodes/
	* rx-decode.opc (movco): Use uniqe id.
	(movli): Likewise.
	(stnz): Condition fix.
	(mvtacgu): Destination fix.
	* rx-decode.c: Regenerate.

bfd/
	* archures.c: Add bfd_mach_rx_v2.
	* bfd-in2.h: Regenerate.
	* cpu-rx.c (arch_info_struct): Add v2 information.
	* elf32-rx.c (elf32_rx_machine): Add v2 support.
This commit is contained in:
Yoshinori Sato 2015-12-17 01:42:34 +09:00
parent ac4c9b0459
commit 239efab164
4 changed files with 24 additions and 8 deletions
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7
bfd/ChangeLog
View File

@ -1,3 +1,10 @@
2015-12-22 Yoshinori Sato <ysato@users.sourceforge.jp>
* archures.c: Add bfd_mach_rx_v2.
* bfd-in2.h: Regenerate.
* cpu-rx.c (arch_info_struct): Add v2 information.
* elf32-rx.c (elf32_rx_machine): Add v2 support.
2015-12-22 Mickael Guene <mickael.guene@st.com>
* bfd-in2.h: Regenerate.

9
opcodes/ChangeLog
View File

@ -1,3 +1,12 @@
2015-12-22 Yoshinori Sato <ysato@users.sourceforge.jp>
opcodes/
* rx-decode.opc (movco): Use uniqe id.
(movli): Likewise.
(stnz): Condition fix.
(mvtacgu): Destination fix.
* rx-decode.c: Regenerate.
2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
* rx-deocde.opc: Add new instructions pattern.

8
opcodes/rx-decode.c
View File

@ -8039,7 +8039,7 @@ rx_decode_opcode (unsigned long pc AU,
}
SYNTAX("stnz %1, %0");
#line 1055 "rx-decode.opc"
ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_nz);
}
break;
@ -10270,7 +10270,7 @@ rx_decode_opcode (unsigned long pc AU,
}
SYNTAX("mvtacgu %0, %1");
#line 1085 "rx-decode.opc"
ID(mvtacgu); SR(a+32); DR(rdst); F_____;
ID(mvtacgu); DR(a+32); SR(rdst); F_____;
}
break;
@ -10615,7 +10615,7 @@ rx_decode_opcode (unsigned long pc AU,
}
SYNTAX("movco %1, [%0]");
#line 1046 "rx-decode.opc"
ID(mov); SR(rsrc); DR(rdst); F_____;
ID(movco); SR(rsrc); DR(rdst); F_____;
}
break;
@ -10722,7 +10722,7 @@ rx_decode_opcode (unsigned long pc AU,
}
SYNTAX("movli [%1], %0");
#line 1049 "rx-decode.opc"
ID(mov); SR(rsrc); DR(rdst); F_____;
ID(movli); SR(rsrc); DR(rdst); F_____;
}
break;

8
opcodes/rx-decode.opc
View File

@ -1043,16 +1043,16 @@ rx_decode_opcode (unsigned long pc AU,
/* RXv2 enhanced */
/** 1111 1101 0010 0111 rdst rsrc movco %1, [%0] */
ID(mov); SR(rsrc); DR(rdst); F_____;
ID(movco); SR(rsrc); DR(rdst); F_____;
/** 1111 1101 0010 1111 rsrc rdst movli [%1], %0 */
ID(mov); SR(rsrc); DR(rdst); F_____;
ID(movli); SR(rsrc); DR(rdst); F_____;
/** 1111 1100 0100 1011 rsrc rdst stz %1, %0 */
ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
/** 1111 1100 0100 1111 rsrc rdst stnz %1, %0 */
ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_nz);
/** 1111 1101 0000 a111 srca srcb emaca %1, %2, %0 */
ID(emaca); DR(a+32); SR(srca); S2R(srcb); F_____;
@ -1082,7 +1082,7 @@ rx_decode_opcode (unsigned long pc AU,
ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */
ID(mvtacgu); SR(a+32); DR(rdst); F_____;
ID(mvtacgu); DR(a+32); SR(rdst); F_____;
/** 1111 1101 0001 1001 a00i 0000 racl #%1, %0 */
ID(racl); SC(i+1); DR(a+32); F_____;